A Primer on Simulation, Modeling, and Design of the Control Loops of Switching Regulators

Transcription

1 A Primer on Simulation, Modeling, and Design of the Control Loops of Switching egulators Bob Erickson and Dragan Maksimovic Colorado Power Electronics Center University of Colorado, Boulder IEEE APEC 3 Tutorial seminar Introduction Objective: maintain v equal to an accurate, constant value V. There are disturbances: in v g in There are uncertainties: in element values in V g in Power input v g A simple dc-dc regulator system, employing a buck converter transistor gate driver δ δ Switching converter pulse-width modulator v c compensator v c G c (s) dt s T s t t Controller v voltage reference Load v ref v feedback connection

2 Objective of Seminar Develop tools for modeling, analysis, and design of converter control systems Need dynamic models of converters: How do ac variations in v g,, or d affect the output voltage v? What are the small-signal transfer functions of the converter? Averaged switch modeling approach for ac modeling and simulation Construction of converter small-signal transfer functions Design of converter control systems Design of input EMI filters that don't disrupt control loops Current-programmed control of converters Averaged switch modeling averaging Switching network d Averaged switch model Switching converter circuit Large-signal averaged circuit model - D 4 A ccm-dcm simulation model linearization S 5 3 K duty Dd^ Model implementation for simulation DC, AC and Transient simulation DC and small-signal averaged circuit model s / ws Gc ( s) = Gco (/ Q) s / w ( s / w ) Analytical results: steady-state characteristics and small-signal dynamics o o

3 Define a switch network, containing all of the converter switching elements. The remainder of the converter is linear and timeinvariant. The terminal voltages and currents of the switch network can be arbitrarily defined. v g i L L i v C v C Q L i L Switch network Duty cycle D d v i C v C v v C v C v Ts L C dt s T s t v g i L v C L C v C i i L i L i L i T dt s v v C v C T s t i v Switch network Q D v i dt s v T T s t Duty cycle d i i L i L i Ts dt s T s t

4 The basic assumption is made that the natural time constants of the converter are much longer than the switching period, so that the converter contains low-pass filtering of the switching harmonics: One may average the waveforms over an interval that is short compared to the system natural time constants, without significantly altering the system response. In particular, averaging over the switching period T s removes the switching harmonics, while preserving the low-frequency components of the waveforms. This step removes the small but mathematically-complicated switching harmonics, leading to a relatively simple and tractable converter model. In practice, the only work needed for this step is to average the switch dependent waveforms. (small switching ripple is neglected) v v C v C v v C v C v Ts v T dt s T s t dt s T s t v Ts = d' v C Ts v C Ts v Ts = d v C Ts v C Ts i i L i L i i L i L i T i Ts dt s T s t dt s T s t i Ts = d i L Ts i L Ts i Ts = d' i L Ts i L Ts

5 We can write esult i L Ts i L Ts = i Ts d i Ts Hence v C Ts v C Ts = v Ts d v Ts = d' d i Ts = d' d v Ts i Ts v Ts d' d v Ts d' d i Ts Averaged switch network i Ts Modeling the switch network via averaged dependent sources v Ts Original switch network i Switch network i v v Q D Duty cycle d Averaged steady-state model: DC transformer Correctly represents the relationships between the dc and low-frequency components of the terminal waveforms of the switch network V I D' : D I V

6 eplace switch network with dc transformer model L C I L V C V g L C V C I L I V D' : D V Can now let inductors become short circuits, capacitors become open circuits, and solve for dc conditions. I Can simulate this model using PSPICE, to find transient waveforms When duty cycle varies, the transformer becomes a nonlinear element. Linearization of the model about a quiescent operating point yields: I i D' : D V v V DD' d I V v DD' d I i Transistor port Diode port A general small-signal ac model for the PWM switch network operating in CCM.

7 eplace switch network with small-signal ac model: L C I L i L V C v C V g v g L C V C v C I L i L D' : D V DD' d I DD' d Can now solve this model to determine ac transfer functions i v i v I i : D I i V d V v I d V v i v i v I i D' : I i V v V d I d V v i v i v I i D' : D I i V v V DD' d I V v DD' d

8 Control-to-output and line-to-output transfer functions G vd (s) and G vg (s) Converter G g G d ω Q ω z V buck D D C LC L V D' boost D' D' D' C D' LC L L buck-boost D D' V DD' D' LC D' C L D' DL where the transfer functions are written in the standard forms G vd (s)=g d s ω z s Qω s ω G vg (s)=g g s Qω s ω ccm i v _ D S switch network 3 K A 4 i v _ averaging v _ i -d d v averaged-switch model 3 D(sub-circuit) K E t G d S A 5 4 duty d i -d d i v _ Controlled voltage source E t replaces the transistor, controlled current source G d replaces the diode Duty ratio d is input to the subcircuit Large-signal, nonlinear model suitable for DC, AC or Transient simulation The same model can be applied in any two-switch PWM converter (the transistor and the diode need not have a common node) Limitations: ideal switches, CCM only, valid for two-switch converters without isolation transformer

9 CCM Averaged-Switch Model PSpice Implementation: ccm D S averaged-switch network (sub-circuit) E t G d 5 duty U D 4 A ccm 3 S 5 K duty 3 4 K A ********************************************************** * MODEL: ccm * Application: two-switch PWM converters * Limitations: ideal switches, CCM only, no transformer ********************************************************** * Parameters: none ********************************************************** * Nodes: * : transistor (D) * : transistor- (S) * 3: diode cathode (K) * 4: diode anode (A) * 5: duty ratio (duty) **********************************************************.subckt ccm Et value={(-v(5))*v(3,4)/v(5)} Gd 4 3 value={(-v(5))*i(et)/v(5)}.ends ********************************************************** Comments Subcircuit ccm is implementation of a large-signal, nonlinear averaged model of the switch network Averaged circuit model of the converter is obtained simply by replacing switching devices with the averaged-switch subcircuit model Linearization and AC small-signal analysis are performed by the simulator Small-signal dynamic responses can be easily generated for different operating points or different sets of parameter values

10 The buck converter illustrated in Fig. operates in the continuous conduction mode, and supplies 5 V at A to load. The element values are L = 6 µh, C = µf. All elements are ideal. Q L 6 µh V g C D µf V v Fig. CCM buck converter. (a) Use averaged switch modeling and computer simulation to plot the magnitude and phase of the control-to-output transfer function G vd (s). You should turn in: the plots of G vd and G vd, and your netlist or schematic. L f Q L 3 µh 6 µh V g C C f D µf µf v Fig. Addition of an input filter to the CCM buck converter of Fig.. (b) An input filter is now added, as illustrated in Fig.. epeat Part (a): use averaged switch modeling and computer simulation to plot the magnitude and phase of the control-to-output transfer function G vd (s). You should again turn in the plots of G vd and G vd, and your netlist or schematic. Does the input filter substantially change the magnitude of G vd? the phase? How many poles and zeroes does G vd (s) now contain? (c) In the circuit of Fig., the load takes a step change from A to A (i.e., the value of changes). Use computer simulation to plot the output voltage response to this change in load current. How long is the settling time (i.e., the time from the step until the output voltage remains within % of 5 V)? Basic CCM Bu ck Example (Part a) Netlist CCM Simulation Problem, part (a) Vg dc g L g a u L 3 Xswitch a 4 CCM a a.lib switch.lib L a 6u V g C L a 3 u C 3 u 3.5 vd 4 dc ac.probe.ac DEC k.end Xswitch CCM 3 V d v

11 Probe output: part (a) Control-to-output transfer function Bu ck w ith input filter: Part (b) Netlist CCM Simulation Problem, part (b) Vg dc g L f L b L g a u a a 3 Lf a b 3u Cf b u V g C f C Xswitch b 4 CCM.lib switch.lib Xswitch L a 6u CCM L a 3 u 3 C 3 u 3.5 vd 4 dc ac 5 4.probe 4.ac DEC k V d.end v

12 Bu ck w ith input filter: Part (b) Probe output, control-to-output transfer function Bu ck w ith input filter: Part (c) Transient response: netlist CCM Simulation Problem, part (c) Vg dc g a u g L f L b L Lf a b 3u IC=4.67 a a 3 Cf b u IC= Xswitch b 4 CCMV g.lib switch.lib C f C L a 6u IC= L a 3 u C 3 u IC=5 Xswitch 3 5 Sload 3 5 load CCM.model load VSWITCH on=.5 off=.5 V LC VLC 5 PULSE(- 5M M) Pulse LC 5 Meg vd 4 dc d 4 Meg 5 4.probe V.tran 5u m uic d d.end Sload on =.5 off =.5 LC

13 Part (c): Probe output Output voltage transient response to step change in load Discontinuous Conduction Mode (DCM) Occurs at light load, when inductor current ripple causes diode current to reach zero before end of switching period Leads to major change in switch network characteristics: Steady-state output voltage becomes load dependent Dynamics become simpler: one pole (and possibly right halfplane zero) are moved to very high frequency, and can normally be ignored We need to incorporate DCM into our averaged switch model

14 DCM waveforms Buck-Boost example i L v L v g v g L i pk v L t i v Area q i pk i Ts v g v v Ts v g v i i pk Area q v g i Switch network i v v v L L i L C v v T s i Ts v g v v Ts v d T s d T s d 3 T s t i Ts = d T s L v Ts i Ts i Ts = v Ts e (d ) e (d )= L d T s v Ts e (d ) Low-frequency components of input port waveforms obey Ohm s law

15 i Ts = d T s L i Ts v Ts v Ts v Ts = v Ts = p e (d ) Ts p i v Output port is a source of power p Power p is independent of load characteristics Power p is dependent on (equal to) the power apparently consumed by the switch network input port Original circuit Switch network i i v v v g v L L i L C v Averaged model i Ts v Ts e (d) p Ts i Ts v Ts v g Ts C v Ts L

16 Determine averaged terminal waveforms of switch network In each case, averaged transistor waveforms obey Ohm s law, while averaged diode waveforms behave as dependent power source Can simply replace transistor and diode with the averaged model as follows: i i i Ts p Ts i Ts v v v Ts e (d ) v Ts Buck e (d) L e = L d T s v g Ts p Ts C v Ts Boost L v g Ts e (d) p Ts C v Ts

17 i i i i v v v v In any event, a small-signal two-port model is used, of the form i i v r j d g v g v j d r v Small-signal DCM switch model parameters i i v r j d g v g v j d r v Small-signal DCM switch model parameters Switch network g j r g j r General two-switch V D e e M e V DM e M e Buck Boost e ( M)V D e e M M e ( M)V DM e (M ) e MV D(M ) e (M ) M e M (M ) e V D(M ) e M e (M ) e

18 Buck, boost, and buck-boost converter models all reduce to DCM switch network small-signal ac model v g r j d g v g v j d r C v Transfer functions control-to-output line-to-output G vd (s)= v d vg == G d ω s with G d = j r p ω p = r C G vg (s)= v = G g v g d = ω s G g = g r = M p Converter G d G g ω p Buck V D M M M M ( M)C Boost V D M M M M (M)C Buck-boost V D M C

19 i v switch network 3 i v _ 4 _ i averaged-switch model CCM i i averaged-switch model DCM i 3 3 v _ -d d v E t G d 5 duty d 4 -d d i i v _ v averaged-switch model CCM/DCM _ i e (d) p 5 duty d 4 v? 5 duty d 3 4 v _ Combined CCM/DCM Averaged Switch Model v _ i -u u v D averaged-switch model CCM/DCM E t S G d 5 duty d CCM/DCM boundary: 3 K A 4 i -u u i v _ u = MAX d, d, u = d, i d Lf s v d d Lf s i v CCM DCM u = equivalent switch duty ratio

20 CCM/DCM Averaged-Switch Model PSpice Implementation: ccm-dcm ************************************************************************************** * MODEL: ccm-dcm * Application: two-switch PWM converters, CCM or DCM * Limitations: ideal switches, no transformer ************************************************************************************** * Parameters: * L=equivalent inductance (relevant for DCM) * fs=switching frequency ************************************************************************************** * Nodes: (same as in ccm) **************************************************************************************.subckt ccm-dcm params: L= fs=e6 Et value={(-v(u))*v(3,4)/v(u)} Gd 4 3 value={(-v(u))*i(et)/v(u)} Ga a value={max(i(et),)} Va a b dummy b Eu u table {MAX(v(5), v(5)*v(5)/(v(5)*v(5)*l*fs*i(va)/v(3,4)))} ( ) ( ).ends ************************************************************************************** The flyback converter illustrated in Fig. can operate open-loop with the following conditions: Table Converter operating points Operating point Load resistance A Ω B Ω C 3 Ω In all three cases, the terminal voltages are V g = 48 V and V = 5 V. The switching frequency is 5 khz. The transformer has negligible leakage inductance, and its magnetizing inductance is µh referred to the primary. All elements are ideal. : v g L µh C 68 µf v Z out f s = 5 khz Fig. Flyback converter. (a) Determine the operating mode (CCM or DCM) and duty cycle for each operating point listed in Table. For parts (b) to (d), use the switch.lib model CCM-DCM. You may also find the switch.lib subcircuit transformer to be useful. It is suggested that you plot the operating point A, B, and C data on the same chart. For each of these parts, you should turn in: (i) your netlist or schematic, and (ii) your plots. (b) Use computer simulation to plot the magnitude and phase of the control-to-output transfer function G vd, at operating points A, B, and C. Compare. (c) Use computer simulation to plot the magnitude and phase of the line-to-output transfer function Gvg, at operating points A, B, and C. Compare. (d) Use computer simulation to plot the magnitude and phase of the output impedance Z out (as defined in Fig. ) at operating points A, B, and C. Compare.

21 Solution to DCM/CCM simulation problem Calculations Part (a) Operating Point Load esistance Mode Duty Cycle A Ohm CCM.5 B Ohms CCM.5 C 3 Ohms DCM.466 Part (b): Gvd Green: A, ed: B (higher Q-factor), Blue: C (DCM) Part (c): Gvg Comments similar to Gvd above, but no HP zero. Part (d): Zout Note low-frequency asymptote is inductive in CCM and resistive in DCM. Simulation of control-output transfer function Netlist DCM-CCM Gvd Simulation Problem, point A. Change for points B and C Vg dc 48 g a u a 3 Xfmr a 3 transformer PAAMS: Lm=u n=. dum 3 Meg Xswitch CCM-DCM PAAMS: L=u fs=5k n=..lib switch.lib C 4 68u 4 vd 5 dc.5 ac.probe.ac DEC k.end Uses Xfmr model: dependent sources plus magnetizing inductance. Must account for turns ratio in averaged switch model as well as transformer model. V g g dum C Xfmr 4 3 CCM-DCM 5 5 V d 3 4 4

22 Part (b): Probe output Control-to-output transfer function Simulation of line-output transfer function Netlist DCM-CCM Gvg Simulation Problem, point A Vg dc 48 ac g a u Xfmr a 3 transformer PAAMS: Lm=u n=. a 3 4 g Xfmr 4 dum 3 Meg Xswitch CCM-DCM dum C PAAMS: L=u fs=5k n=..lib switch.lib V 3 C 4 68u g 4 vd 5 dc.5 CCM-DCM 3.probe.ac DEC k.end Similar to Gvd simulation, but move ac component out of independent source vd and into independent source Vg. 5 5 V d 4

23 Part (c): Probe output Line-to-output transfer function Simulation of output impedance Netlist DCM-CCM Zout Simulation Problem, point A Vg dc 48 g a u a 3 4 Xfmr a 3 transformer g Xfmr 4 I load PAAMS: Lm=u n=. dum 3 Meg dum C Xswitch CCM-DCM PAAMS: L=u fs=5k n=. V 3 g.lib switch.lib C 4 68u 4 CCM-DCM 3 Iload 4 ac vd 5 dc.5.probe.ac DEC k 4 5.end 5 emove ac components from vd and Vg. V d Introduce ac current source Iload at output. Zout = V(4)/Iload.

24 Part (d): Probe output Output impedance i load (s) load current variation v ref (s) reference input compensator v e (s) error signal G c (s) v c (s) v g (s) ac line variation pulse-width modulator d(s) V M duty cycle variation Z out (s) G vg (s) G vd (s) converter power stage v(s) output voltage variation H(s) v(s) H(s) sensor gain

25 Manipulate block diagram to solve for v(s). esult is G v = v c G vd / V M G vg Z ref v HG c G vd / V g i out M HG c G vd / V load M HG c G vd / V M which is of the form v = v ref H T T v g G vg T i load Z out T with T(s)=H(s) G c (s) G vd (s)/v M ="loop gain" Loop gain T(s) = products of the gains around the negative feedback loop. Closed-loop transfer function from to v(s) is: v(s) v ref (s) v g = i load = = H(s) T(s) T(s) If the loop gain is large in magnitude, i.e., T >>, then (T) T and T/(T) T/T =. The transfer function then becomes v(s) v ref (s) H(s) which is independent of the gains in the forward path of the loop. This result applies equally well to dc values: V = V T() ref H() T() H() v ref

26 8 db 6 db T for T >> T T for T << 4 db f p T db db db T T f z db/decade Crossover frequency f c f p 4 db/decade 4 db Hz Hz Hz khz khz khz f Original (open-loop) line-to-output transfer function: G vg (s)= v(s) v g (s) d = i load = With addition of negative feedback, the line-to-output transfer function becomes: v(s) v g (s) v ref = i load = = G vg(s) T(s) Feedback reduces the line-to-output transfer function by a factor of T(s) If T(s) is large in magnitude, then the line-to-output transfer function becomes small.

27 Original (open-loop) output impedance: Z out (s)= With addition of negative feedback, the output impedance becomes: Feedback reduces the output impedance by a factor of T(s) v(s) i load (s) d = v g = v(s) = Z out(s) i load (s) v ref = T(s) v g = If T(s) is large in magnitude, then the output impedance is greatly reduced in magnitude. 8 db 6 db 4 db db db db 4 db 6 db T db f p 4 db/decade T db f p Q db T f z db/decade db/decade f z 4 db/decade Q db f c Crossover frequency T T(s) for T >> T(s) for T << f p 4 db/decade 8 db Hz Hz Hz khz khz khz f

28 T 6dB 4dB db db db 4dB T T f p f z crossover frequency f c Hz Hz Hz khz khz khz T(jπf c ) = ϕ m = 8 = 68 f ϕ m 9 T 8 7 Closed-loop system is stable if phase margin is positive Phase margin affects Q-factor of poles at f c in closed-loop transfer functions. Closed-loop Q vs. ϕ m Q Q-factor of closedloop poles (in T/(T)) db 5dB db 5dB db -5dB -db -5dB Q = db m = 5 Q =.5 6dB m = 76 -db Phase margin m

29 Closed-loop transient response vs. Q-factor v.5 Q=5 Q= Q=4 Q=.5 Q= Q=.75 Q=.5 Q=.3 Q=. Q=. Q=.5 Q=. 5 5 c t, radians L 5µH i load v g 8V transistor gate driver δ pulse-width modulator C 5µF f s = khz V M = 4V v c G c (s) v compensator error signal v e 3Ω v ref 5V Hv H(s) sensor gain

30 With G c =, the loop gain is T u (s)=t u s Q ω s ω T u = HV DV M = dB 4dB T u T u db db db 4dB T u T u T u dB 8 Q f =.khz 7 Hz Hz Hz khz khz khz f f khz Q f = 9Hz f c =.8kHz, ϕ m = 5 Q = dB 4 db/decade 9 Obtain a crossover frequency of 5kHz, with phase margin of 5 T u has phase of approximately -8 at 5kHz, hence lead (PD) compensator is needed to increase phase margin 4dB G c f p G G c c f db G c z f G p c f c fz db = f z f p db 4dB G c Hz Hz Hz khz khz khz Lead compensator should have phase of 5 at 5kHz T u has magnitude of -.6dB at 5kHz Lead compensator gain should have magnitude of.6db at 5kHz f z / f f p / f z 9 9 8

31 s ω z T(s)=T u G c s ω p 4dB T T T T db = dB Q = dB db db f khz f z.7khz f c 5kHz f p 9Hz 4kHz 4dB T 7Hz 7 Hz Hz Hz khz khz khz f s Q ω s ω.4khz 7kHz ϕ.khz m =5 9 8 Good phase margin Wide bandwidth Lowfrequency loop gain is low hence not much rejection of disturbances 4dB db db db T T = dB T / T =. 8.7dB f f z Q = dB f c f p Q need more low-frequency loop gain hence, add inverted zero (PID controller) 4dB Hz Hz Hz khz khz khz f

32 4dB G c G c G c db f p G f cm c f f db L z db 4dB G c 9 ω s ω L z s G c (s)=g cm ω s p f L / f z / f p / 9 /dec Hz Hz Hz khz khz khz f f L 45 /dec f z 45 /dec add inverted zero to PD compensator, without changing dc gain or corner frequencies choose f L to be f c /, so that phase margin is unchanged 6dB 4dB T db Q db f L f fz f c db 4dB T Q f p 6dB 8dB Hz Hz Hz khz khz khz f

33 v v g db db db 4dB 6dB Gvg () = D open-loop G vg db/dec D T u G cm f L f f z Q f c 8dB closed-loop G vg T 4dB/dec db Hz Hz Hz khz khz khz f Block Block A Z (s) v ref (s) v e (s) G (s) v e (s) v x (s) Z (s) G (s) v x (s)=v(s) T(s) H(s) Objective: experimentally determine loop gain T(s), by making measurements at point A Correct result is Z T(s)=G (s) (s) G (s) H(s) Z (s)z (s)

34 V CC Block Block dc bias Z (s) v ref (s) v e (s) G (s) v e (s) v y (s) v z v x (s) Z (s) G (s) v x (s)=v(s) T m (s) H(s) measured gain is T m (s)= v y(s) v x (s) v ref = v g = T m (s)=g (s) G (s) H(s) T m (s) T(s) provided that Z >> Z Block v z Block i(s) Z (s) Z s (s) v ref (s) v e (s) G (s) v e (s) v y (s) v x (s) Z (s) G (s) v x (s)=v(s) T v (s) H(s) Ac injection source v z is connected between blocks and Dc bias is determined by biasing circuits of the system itself Injection source does modify loading of block on block T v (s) T(s) provided (i) Z (s) << Z (s), and (ii) T(s) >> Z (s) Z (s)

35 Block Block Z (s) i y i z i x v ref (s) v e (s) G (s) v e (s) Z s (s) Z (s) G (s) v x (s)=v(s) T i (s) H(s) T i (s)= i y(s) i x (s) v ref = v g = Now require: (i) Z (s) << Z (s), and (ii) T(s) >> Z (s) Z (s) Example: voltage injection after error amplifier PSPICE issues Divergence!. Use.nodeset to improve convergence. Limit maximum and minimum duty cycles V g 8 V L 3 5 µh V M = 4 V CCM-DCM 3 X switch L = 5 µη f s = kηz v x v z E pwm value = {LIMIT(.5 v x,.,.9)} 7 v y C 5 µf 3 C 3 kω LM34 V.nodeset v(3)=5 v(5)=5 v(6)=4.44 v(8)= kω.7 nf v ref 5 V 4 47 kω i LOAD kω 4 5 C. nf v

36 Buck voltage regulator, closed-loop.param =.param L=5uH fs=khz.step PAAM LIST 3,,5.ac dec 5 5KHz.nodeset v(3)=5 v(5)=5 v(6)=4.44 v(8)=.536.lib switch.lib.lib nom.lib Vg 8V Xswitch 8 CCM-DCM PAAMS: L={L} fs={fs} L 3 {L} C 3 5uF load 3 {} Vcc p V Vref ref 5V Xopamp ref 5 p 6 LM K K C 4 5.nF K 3 6 6x K C3 6x 5.7nF Vz 6 7 dc ac Epwm 8 value={limit(v(7)*.5,.,.9)}.probe.end Plotting the loop gain via injection v z Use POBE to plot v y /v x Loop gain is plotted at three values of load resistance File included on website also plots transient response If.nodeset is omitted, PSPICE diverges 6 db T T T 4 db = 3 Ω db = 5 Ω f c = 39 Hz f c = 5.3 khz db db 4 db = 3 Ω = 5 Ω T 9 ϕ m = 55 ϕ m = Hz 5 Hz 5 Hz 5 khz 5 khz f esults at full load (nominal design point, = 3 Ω) are close to design goals Very different results at light load (in DCM at = 5 Ω)! As load current is reduced: Q at first increases because of reduced damping. Then Q decreases in DCM

37 G vg db db Open loop, d = constant db = 3 Ω 4 db 6 db Closed loop = 5 Ω 8 db 5 Hz 5 Hz 5 Hz 5 khz 5 khz f v 6 V 5 V Closed loop 4 V Open loop d = constant. ms.4 ms.6 ms.8 ms. ms. ms.4 ms.6 ms.8 ms. ms 6 A i LOAD 4 A A. ms.4 ms.6 ms.8 ms. ms. ms.4 ms.6 ms.8 ms. ms t PSPICE-generated transient response, same closed-loop buck example

38 A typical design approach:. Engineer designs switching regulator that meets specifications (stability, transient response, output impedance, etc.). In performing this design, a basic converter model is employed, such as the one below: (no input filter) (buck converter example) g I Converter model : D V g L C. Later, the problem of conducted EMI is addressed. An input filter is added, that attenuates harmonics sufficiently to meet regulations. 3. A new problem arises: the controller no longer meets dynamic response specifications. The controller may even become unstable. eason: input filter changes converter transfer functions Converter ac model is modified by input filter g Input filter L f C f I Converter model : D V g L C

39 4 db G vd 3 db db G vd G vd db G vd db db 8 36 Effect of L-C input filter on control-tooutput transfer function G vd (s), buck converter example. Dashed lines: original magnitude and phase Solid lines: with addition of input filter Hz 54 khz khz f G vd (s)= G vd (s) Zo (s)= Z o(s) Z N (s) Z o(s) Z D (s) G vd (s) Zo (s)= is the original transfer function, before addition of input filter Z D (s)= Z i (s) (s)= Z N (s)= Z i (s) (s) is the converter input impedance, with set to zero is the converter input impedance, with the output nulled to zero (Proof using Middlebrook's extra element theorem)

40 Input filter design criteria for basic converters Converter Z N (s) Z D (s) Z e (s) Buck D D s L s LC sc sl D Boost D sl D D s L D LC s D sc sl Buckboost D D sdl D D D s L D LC s D sc sl D The correction factor G vd (s)= Z o(s) Z N (s) Z o(s) Z D (s) G vd (s) Zo (s)= Z o Z N, and Z o(s) Z N (s) Z o(s) Z D (s) shows how the input filter modifies the transfer function G vd (s). The correction factor has a magnitude of approximately unity provided that the following inequalities are satisfied: Z o Z D These provide design criteria, which are relatively easy to apply.

41 Buck converter with input filter Small-signal model V g Input filter L f Converter L i 33 µh µh C C f 3 V 47 µf µf 3 Ω D =.5 v g Input filter L f 33 µh C f 47 µf Z o (s) Z i (s) I Converter model : D V g L µh C µf 3 Ω Z D (s)= D sl sc Z D (s) : D L C 4 dbω f = f o = 3 dbω Z D D =Ω πc π LC ωl 53 Hz.59 khz D dbω Z N ωd C dbω /D Q = C = f o =3 9.5 db L f dbω Hz khz khz f

42 Z N (s)= test(s) test (s) test test Z N (s) I : D V g s L C Solution: test (s)=i (s) test (s)= V g (s) D Hence, Z N (s)= V g (s) D I (s) = D 4 dbω L f 3 dbω Q f C f dbω Z o (s) dbω Z o Z o (s)=sl f sc f dbω dbω dbω f = ωl f f f = π L f C f = 4 Hz Hz khz f L f C f =.84 Ω ωc f No resistance, hence poles are undamped (infinite Q-factor). In practice, losses limit Q-factor; nonetheless, Q f may be very large.

43 Z o Z N, and Z o Z D 4 dbω f Q f = 53 Hz 3 dbω ωl f Z D Ω o =.59 khz D dbω Z N dbω dbω dbω Z o ωd C f ωl f f f = 4 Hz ωc f Q = 3 /D dbω Hz khz khz f Can meet inequalities everywhere except at resonant frequency f f. Need to damp input filter! Z o Z N Z o Z D db db db 8 36 Hz khz khz f Z o Z N Z o Z D

44 4 db G vd 3 db db G vd G vd db G vd db Dashed lines: no input filter Solid lines: including effect of input filter db 8 36 Hz 54 khz khz f Z o, with large C b L f f f f C f C b ωl f f f ωc f

45 4 dbω f = 53 Hz 3 dbω ωl f Z D Ω o =.59 khz D dbω Z N dbω dbω Z o f = Ω ωd C f Q = 3 /D dbω ωl f f f = 4 Hz ωc f dbω Hz khz khz f 4 db G vd 3 db db G vd G vd db G vd db Dashed lines: no input filter Solid lines: including effect of input filter db 9 Hz 8 khz khz f

46 f C b Parallel Damping L f f L b Series Damping L b L f v C f f v f C b v C f v f L b Parallel Damping f L f L b Size of C b or L b can become very large v C f v Need to optimize design v L C C d v Basic results Q opt = = n 43n n 4n Does not degrade HF attenuation No limit on Z mm C d is typically larger than C with Z mm = n = C d C = L C n n Z o mm o.. n = C d C

47 Cascade connection of multiple L-C filter sections can achieve a given high-frequency attenuation with much smaller volume and weight Need to damp each section of the filter One approach: add new filter section to an existing filter, using new design criteria Stagger-tuning of filter sections g Additional Existing filter Z a Z i filter section Z o test test How the additional filter section changes the output impedance of the existing filter: Z a(s) Z N (s) modified Z o (s)= Z o (s) Za (s)= Z a(s) Z D (s) Z N (s)= Z i (s) test (s) Z D (s)= Z i (s) test (s)=

48 g Additional Existing filter Z a Z i filter section Z o test test Z N (s)= Z i (s) test (s) Z D (s)= Z i (s) test (s)= (with filter output port short-circuited) (with filter output port open-circuited) The presence of the additional filter section does not substantially alter the output impedance Z o of the existing filter provided that Z a Z N and Z a Z D equirements: For the same buck converter example, achieve the following: L n L L n L 8 db of attenuation at 5 khz g C C Z o Section to satisfy Z o impedance inequalities as before: Section Section 4 dbω f = f o = 3 dbω Z D D =Ω πc π LC ωl 53 Hz.59 khz D dbω Z N ωd C dbω /D Q = C = f o =3 9.5 db L f dbω Hz khz khz f

49 n L n L g L C Z a L Z i C test test Section Section To avoid disrupting the output impedance Z o of section, section should satisfy the following inequalities: Z a Z N = Z i output shorted = sn L sl Z a Z D = Z i output open-circuited = sc sn L sl dbω Z D dbω Z N Z a dbω 9 45 Z N Z a 45 Z D 9 khz khz khz MHz

50 3 dbω dbω dbω dbω f o Cascaded sections and Z D Section alone Z N - dbω - dbω khz khz khz H db db - db -4 db -6 db -8 db - db 8 db at 5 khz - db khz khz f khz MHz

51 L f g 33 µh C f 47 µf f.67 Ω C b µf n L.65 Ω.9 µh.9 Ω n L 5.6 µh L 5.8 µh L 3. µh g C C 6.9 µf.7 µf Buck converter v g i s Q L D i L C v The peak transistor current replaces the duty cycle as the converter control input. Measure switch current i s f i c f f i s Clock Analog comparator T s S Q Latch m Switch current i s Control signal i c Control input Current-programmed controller dt s T s Transistor status: on off t Compensator v Clock turns transistor on Comparator turns transistor off v ref Conventional output voltage controller

52 i L Ts = i c Neglects switching ripple and artificial ramp (slope compensation) Yields physical insight and simple first-order model Accurate when converter operates well into CCM (so that switching ripple is small) and when the magnitude of the artificial ramp is not too large Well-accepted by practicing engineers esulting small-signal relation: i L (s) i c (s) Buck converter example i i L i L v g v v C v Switch network Averaged terminal waveforms, CCM: The simple approximation: v Ts = d v Ts i Ts i c Ts i Ts = d i Ts

53 CPM averaged switch model i Ts i Ts p Ts L i L Ts v g Ts v Ts i c Ts v Ts C v Ts Averaged switch network Eliminate duty cycle: i Ts = d i c Ts = v Ts v Ts i c Ts i Ts v Ts = i c Ts v Ts = p Ts Output port is a current source Input port is a dependent power sink i i L v v V g i C V I c v c i v V c v V I Switch network small-signal ac model i =i c V V v I c V v I V

54 i g L i L v g C i D D c D sl v i c v G vc (s)= v(s) = i c (s) sc vg = G vg (s)= v(s) = v g (s) ic = i g v g r f (s) i c g v g v g f (s) i c r C v Converter g f r g f r Buck D D sl D Boost D' D' sl D' Buck-boost D D sl D' D' D D D' D' sdl D' D

55 Simulation of Current Mode Controllers Develop a model of the currentprogrammed controller, which can be combined with existing CCM- DCM averaged switch models V g V L 3 i L L 4 35µH.5 Ω 5 4 CCM-DCM 3 d X switch f s = khz L = 35µΗ C µf i LOAD Ω v Controller model outputs a duty cycle, in response to control input i c (or v c ) and the sensed converter voltages and currents v c CPM control current d f i L v()v(3) v(3) E i E E X cpm f = Ω f s = khz L = 35 µη V a =.6 V Averaged controller waveforms i L i L i c i c m a i pk m a i pk m m m m dt s d T s =( d)t s t dt s d T s t v L v Ts v L v Ts v Ts t v Ts t T s T s CCM DCM

56 Equations Need to write large-signal equations of controller, in a form that leads to convergence of simulator and that works for both CCM and DCM Basic equations: d =d m = v Ts L m = Average inductor current: i L Ts = di pk m dt s Artificial ramp amplitude: V a = m a T s f v Ts L i pk = i c m a dt s d i pk m d T s Substitute and solve (partially) for d: i c (d d ) i L Ts m d T s d = m a (d d )T s m dt s i pk d = m T s (CCM) (DCM) i pk d =MIN d, m T s (CCM and DCM) CPM controller subcircuit model Output: duty cycle d.subckt CPM control current d params: L=e-6 fs=e5 Va=.5 f= * generate d for CCM or DCM Inputs: v c Ed d table Ts {MIN(L*fs*(v(control)-va*v(d))/f/(v()),-v(d))} (,)(,) * generate inductor current slopes, see Eqs.(B.4) and (B.6) Em m value={f*v()/l/fs} Em m value={f*v()/l/fs} * compute duty cycle d, see Eq.(B.3) Eduty d table {*(v(control)*(v(d)v(d))-v(current)-v(m)*v(d)*v(d)/) /(v(m)*v(d)*va*(v(d)v(d)))} (.,.) (.99,.99).ends d CPM control current f i L Ts v Ts v Ts

57 CPM buck example CPM buck converter L 3 i L L 4.param Va=.6 35 H.5.param fs=khz V g.param L=35uH X switch C.ac DEC KHz F f V s = khz iout 4 ac L = 35.lib switch.lib Vg V ac Xswitch 5 CCM-DCM PAAMS: L={L} fs={fs} L 3 {L} L d C 4 uf X cpm load 4 d f = Xcpm ctr ni nm nm 5 CPM CPM f s = khz PAAMS: L={L} fs={fs} va={va} f= L = 35 Ei ni value={i(l)} control current V a =.6 V Em nm value={v()-v(3)} Em nm value={v(3)} Vic ctr dc.4v ac f i L v()v(3) v(3).probe v c E i E E.end 5 4 CCM-DCM 3 i LOAD v Control-to-output frequency response Duty cycle control vs current programmed control 4 db G db db db 4 db G vc G vd G vd G In both cases: V = 8. V D =.676 For CPM: V c =.4 V V a =.6 V 6 db G vc 9 8 Hz Hz khz khz khz f

58 Line-to-output frequency response Duty cycle control vs current programmed control db G vg db db 4 db 6 db 8 db Duty cycle control d = constant Current programmed mode v c = constant In both cases: V = 8. V D =.676 For CPM: V c =.4 V V a =.6 V db Hz Hz khz khz khz f Output impedance Duty cycle control vs current programmed control dbω Z out dbω dbω Current programmed mode v c = constant Duty cycle control d = constant In both cases: V = 8. V D =.676 For CPM: V c =.4 V V a =.6 V 4 dbω Hz Hz khz khz khz f

59 Example: comparison of current-mode controlled and duty-cycle controlled regulators L 4 µh s 5 mω C V g V µf v Transistor gate driver f s = 5 khz PWM for duty-cycle controlled regulator or Current-programmed controller Design specs: Output voltage regulated at V = 5 V Output power:.5 W ( = Ω) to 5 W ( =.5 Ω) V ref = 5 V Both current-mode and duty-cycle controlled regulators have the voltageloop compensator designed for the cross-over frequency of 5 khz and the phase margin of 6 o (at the load of =.5 Ω) v c G c (s) Error signal v e Voltage-loop compensator Open-loop responses and compensators Open-loop control-to-output response Duty-cycle controlled regulator Current-mode controlled regulator Duty-cycle controlled regulator PID compensator: G ( s) = G cd G vcd ( s) = G f o md od s s Q ω ω ω I s s ω s ω p o z o = 8 khz, Q =.5 Compensators f z f p f I = khz = 5.6 khz = 8 khz G vcc ( s) = G oc f = 4.3 khz, f = Current-mode controlled regulator PI compensator: ω G s = G Ic cc( ) mc s f Ic s s ω ω = 35 Hz 5kHz

60 Summary of results obtained by simulation Load =. 5 Ω Full load, CCM = Ω educed load, but still CCM = Ω Light load, DCM Duty-cycle controlled regulator f c ϕ m = 5.6 khz o = 69 f c ϕ m = 6 khz o = 63 f c ϕ m =.8 khz o = 73 Current-mode controlled regulator f c ϕ m = 4. khz o = 68 f c ϕ m = 4. khz o = 68 f c ϕ m = 6.6 khz o = 73 Both approaches maintain good phase margins at all loads and approximately the same bandwidth as long as the converter is in CCM Bandwidth is severely reduced at light loads when the converter operates in DCM. This effect is more severe for duty-cycle control than for current-mode control. esources For further reading: Erickson and Maksimovic, Fundamentals of Power Electronics, second edition, Kluwer Academic Publishers,, ISBN Website: Includes downloadable PSPICE libraries