Chapter 3 HARD SWITCHED PUSH-PULL TOPOLOGY

Transcription

1 35 Chapter 3 HARD SWITCHED PUSH-PULL TOPOLOGY S.No. Name of the Sub-Title Page No. 3.1 Introduction Single Output Push Pull Converter Multi-Output Push-Pull Converter Closed Loop Simulation Experimental Implementation Conclusion 60

2 Introduction From table 1.1, it is inferred that the push-pull converter is best suited for low power applications varying from few watts to less than hundred watts, which is particularly suitable for aerospace applications. Therefore, the implementation of multi-output push-pull topology with hard switching is carried out and the results obtained are discussed in this chapter. 3.2 Single Output Push-pull Converter A practical push-pull converter consists of two forward converters operating back to back, magnetizing the core in both the directions and allowing the core to be utilized more effectively. The basic push-pull converter topology is shown in Fig It contains a pair of complementary switches S1 and S2, a center tapped transformer, a full wave rectifier with diodes D1 and D2 in the secondary, an output filter inductor L and an output capacitor C. According to the ON/OFF states of the switches S1 and S2, the converter has the following switching modes: Mode 1 - When S1 is ON and S2 is OFF, diode D1 is forward biased, whereas diode D2 is reverse biased. Mode 2 - When S2 is ON and S1 is OFF, diode D2 is forward biased, whereas diode D1 is reverse biased. Mode 3 - When both S1 and S2 are OFF, diodes D1 and D2 are forward biased.

3 37 The DC voltage acquired from the rectifier output is fed to the load through the filter. Fig: 3.1 Circuit diagram of a push-pull converter. To increase compactness it is proposed to have multiple outputs by modifying the secondary of this converter. The multi-output push-pull converter is discussed in the next section. 3.3 Multi-Output Push-Pull Converter Block diagram of the designed topology is shown in Fig Input voltage is provided to the startup circuit and push-pull transformer. The push-pull transformer is followed by the rectifier and filter circuits. The PWM IC is initiated using the startup circuit. This circuit is designed in such a way that the PWM IC is fed from the third output of the converter, thereby reducing the necessity of an additional power supply. The pulses from the PWM IC are used to drive the switches of the push-pull converter.

4 38 Fig: 3.2 Block diagram of multi-output push-pull topology A 6.875W multi-output push-pull converter topology presented in Fig.3.3 is designed for supplying controlled voltage to Telecommunication systems. Hard switching is employed for the switches. This topology transforms supply voltage (24V - 42V) to three secondary voltages of +5V/0.5A, +12.5V/250mA and +12.5V/100mA respectively. Fig: 3.3 Multi-Output Push-Pull Converter

5 39 Among these secondary outputs +12.5V/250mA (3.125W) is a high power output when compared with the other two outputs +5V/0.5A (2.5W) and +12.5V/100mA (1.25W) respectively. If regulated its impact on the converter system is undesirable, as listed below: It calls for an opto-isolator, making the system much more intricate. Large deviation in this output increases cross regulation on the other outputs (+5V/0.5A and +12.5V/100mA). If operated at no load, other outputs would not be readily available. For these reasons, low power output +12.5V/100mA is sensed and controlled by PWM controller IC UC3825. Once the converter starts working, this regulated output serves as the supply to the PWM IC. This hard switched multi-output push-pull converter topology is chosen as the power supply for Telecommunication systems Design Specifications The converter is designed to operate in continuous and discontinuous modes, and the design specifications are given in this section. Specifications of the multi-output push-pull converter are given in Table 3.1.

6 40 Table 3.1 Specification of multi-output push-pull converter Input Voltage Minimum Input voltage Maximum Input voltage Switching frequency Duty ratio 24V 42V 24V 42V 50kHz 45%(as required by IC UC3825) Efficiency 80% Output power W 6.9W Outputs 5V/0.5A 12.5V/0.25A 12.5V/0.1A The converter design is carried out for both Continuous and Discontinuous Conduction Modes (CCM & DCM) of operation Discontinuous mode (DM) of operation The design formulae for discontinuous operations are listed in this section. Primary current calculation: The Primary inductor, Lpri = = µh The Primary peak current, = 2.16 A The Primary RMS current, = 8.5 A Where, Minimum input voltage (V)

7 41 ON time (micro seconds) Maximum output power (W) T Total time period (micro seconds) Maximum duty cycle Secondary current calculation: The turns ratio, = = 5 for +5V/0.5A output = 2 for +12.5V/0.25A and +12.5V/0.1A outputs. Reset time, Tr = = 7µsec for all outputs Secondary peak current, = = A for +5V/0.5A output = 11.85A for +12.5V/0.25A output = 12.35A for +12.5V/0.1A output Secondary RMS Current, = = 7 A for +5V/0.5A output = 4.04A for +12.5V/0.25A output Where, = 4.21A for +12.5V/0.1A output Primary turns Secondary turns Output voltage (V) Output current (A)

8 Continuous mode(cm) of operation: The design formulae for continuous operations are listed in this section. Primary current calculation: The Primary inductor, Lpri = = µh The Primary peak current, = A The Primary RMS current, = 2.34 A Where, Output power (W) Secondary current calculation: Secondary peak current, = = A for +5V/0.5A output = 0.545A for +12.5V/0.25A output = 0.181A for +12.5V/0.1A output Secondary RMS Current, = * = A for +5V/0.5A output = 0.404A for +12.5V/0.25A output = 0.134A for +12.5V/0.1A output Filter calculation: The output voltage equation of a push-pull converter is given by: Vo = 2*Vin* *D (3.1)

9 43 Ripple current in the filter inductor, il = (3.2) Filter capacitor, C = (3.3) Where, Vo - Output voltage (V) Vin - Input voltage (V) n = - turns ratio D - Duty cycle - Filter inductor (H) - output ripple voltage of the capacitor f - switching frequency(khz) Filter capacitor and inductor are obtained using equations (3.1) (3.3) and are tabulated in Table 3.2 for all three output voltages. Table 3.2 Designed value of filter capacitor and inductor Input voltage (24V-42V) Parameters Output voltage-1 (5V/0.5A) Output voltage-2 (12.5V/0.25A) Output voltage 3 (12.5V/0.1A) Turns ratio Filter inductor 1.8µH 1µH 6.7µH Filter capacitor 270µF 1µF 4.7µF

10 44 From the design it can be implied that both primary and secondary peak currents are higher in discontinuous mode than in continuous conduction mode. Turning OFF the switches at this higher peak current will certainly increase the switching losses and oversize the switches. To limit the current, large inductive filter has to be used which would make the converter bulkier. From the design values obtained in sections and , it is inferred that the currents in primary and secondary are lesser in continuous mode (RMS primary current is 2.34A and secondary currents are 6.7/0.4/0.134A), than in discontinuous mode (RMS primary current is 8.5A and secondary currents are 7/4/4.2A). This results in reduced filter size for continuous mode. It is always desirable to have continuous conduction with lesser current. Therefore, continuous conduction mode is considered for analysis henceforth Transformer and inductor design For the specifications considered in section and , the transformer and inductor needed for the push-pull converter are designed as follows. The following assumptions are made in the transformer design: Reciprocal current density [102], = 500 circular mils /RMS A Where circular mill = 5.067* m 2

11 45 Maximum flux density, = 3200guass Output power, = 6.9W The output power, where is in watts for in gauss, and are in square centimeters, f is in hertz, and is in circular mils per RMS ampere [94]. From the above equation, area product, = 1481mm 4. From Appendix I, core - EE 25/10/5 is selected. Primary number of turns, Np = = 13 The output voltage, =[( - 1) * - 1] * 2 * From the above equation,, From Appendix II the wire gauge selected are: Np = SWG 26, Ns1 = SWG 27, Ns2 = SWG 31 and Ns3 = SWG 35 The following assumptions are made in the inductor design: Flux density, for ferrite Current density, Crest factor, Window utilization factor, The energy stored in the inductor, Joules Area product, Number of turns,

12 46 Where, Im is the peak inductor current (A) = Total iron area (cm 2 ) The design details of the inductor are tabulated in Table 3.3. Table 3.3 Designed values of filter inductor Inductor Value Energy stored Area product Core selected Number of turns SWG selected 1.8µH 51.98µJ 217mm 4 T µH 89µJ mm 4 T µH 1.536µJ 2.133mm 4 T Closed Loop Simulation The designed push-pull converter in section 3.2 is simulated in PSIM and the results obtained are discussed in detail. The design details of the analog controller IC UC3825 is also dealt in this section PWM Controller design The UC3825 family of PWM control IC is optimized for the high frequency switched mode power supply applications. The output of UC3825 oscillator is a saw tooth waveform. The pulse rising edge is governed by Rt and Ct. To generate two complimentary pulses of same frequency from the IC, Rt and Ct are selected to produce saw-tooth waveform at double the desired switching frequency of the converter [refer Appendix III]. = = 3.3kΩ (3.4) = = 4.5nF (3.5)

13 47 The simulation of controller is done with the designed, values in open loop and the simulated circuit diagram is as displayed in Fig.3.4 for an input supply voltage of 12.5V. Fig: 3.4 PWM Controller Startup circuit Startup circuit shown in Fig. 3.5 is utilized to startup the PWM IC (UC3825). The circuit is designed in such a way that, initially PWM IC is powered from the main supply until the converter output reaches steady state, (i.e.) during the transient period of the third output voltage UC3825 IC is powered from the main supply. When output voltage3 reaches steady state, diode D1 in Fig.3.5 is forward biased and the IC is powered directly from the converter regulated third output. Transistor NPN 2N3019 operating in the active region is used to supply adequate startup current. This device has a current gain of β = 50 at Ic = 10mA.

14 48 Two zener diodes are connected in series to provide the required voltage at the emitter of 2N3019. The diodes 1N4626UR of 0.5W are used for providing voltages of 5.6V and 6.2V. Fig: 3.5 Startup circuit The supply voltage and current to UC3825 PWM Controller IC (VpwmIC & IpwmIC) are 12.06V and 50mA respectively. Minimum input supply voltage, Vimin = 24V and β = 50 Collector Current, Ic =50mA Ib = =1 ma The total base current = Ib + zener test current = 1.25mA Zener voltage, Vz =11.8V R8= = 12.2 kω We have chosen 12 kω for R8. Similarly, R5 = = 238 Ω

15 49 Chosen value of R5 is 250Ω. Power dissipation is reduced by a parallel combination of four 1kΩ resistor with 0.25W power rating, resulting in an equivalent resistance of 250Ω. Where PWM voltage, VpwmIC = V Maximum power consumed by switch Q1 = (Vinmax (50mA*250)) x Ic = W, Where, Ic = 50mA Stabilization of feedback loop The main objective of the compensation network is to supply good line, load regulation and also dynamic response. These objectives are most effectively achieved by providing high gain at low frequencies for good DC regulation, and high bandwidth for good transient response. For a stable system, phase margins of 45º to 60º are considered to be safe values that yield well-damped transient load responses. Fig. 3.6(a) shows the open loop response of the converter with a phase margin of and gain margin of db, and it is determined by using state space averaging method. High bandwidth is attained with highest possible crossover frequency fco. The compensation network is designed around the error amplifier to eliminate Right Hand Plane (RHP) zero. Compensation network selected is a type-3 system which can be termed as a combination of three poles and two zeroes (including pole at origin).

16 50 (a) (b) Fig: 3.6 (a) Open loop response (b) Closed loop response of push-pull converter In Fig. 3.6(a), fco is in the -2 slope of the output transfer function. To force fco to the preferred point, the error amplifier should be designed in such a way that the total gain crosses the fco at a -1 slope. i. A pole at origin, at a frequency of 500Hz is calculated as given below. fpo = = 500Hz Because of the pole at origin, the error amplifier gain decreases in the direction of lesser frequencies. To achieve this, the gain at lower frequency is maintained at a low value to degenerate low frequency input ripple completely. The gain curve needs to be turned around to move upwards at a slope of +1 in the direction of lesser frequencies which can be achieved by providing two zeros.

17 51 ii. The frequency at which the second zero occurs is fz2 = = 1000Hz Let C1 = 10kpF, therefore R4 = 13kΩ The gain cannot be allowed to continue upwards at a +1 slope beyond fco. When this happens, gain would be high at higher frequencies and thin noise spikes would get through the output at high amplitudes. For this purpose, two poles are provided. The first pole turns the +1 gain slope horizontal; the second pole turns it to a -1 slope. iii. Frequency of first pole: fp1 = = 3000 khz; C3 = 1kpF iv. Frequency of second pole: fp2 = = 15 khz; Rth = 326Ω, where Rth = R2 R3. The transfer function of the error amplifier is: G = [ ] From the closed loop frequency response of push-pull converter shown in Fig. 3.6(b), it is observed that the phase margin is 47 o, the gain margin is 13.5dB and the cross over frequency is at -1 slope. This cross over frequency is about one fifth of the switching frequency which makes the system stable. Compensation circuit along with the IC and push-pull feedback loop is shown in the Fig. 3.7(a) and (b). Compensation is used

18 52 to achieve constant output voltage for load variation. Push-pull converter with lag-lead compensation is selected for controlling output voltage. (a) (b) Fig: 3.7 (a) Compensation circuit with PWM controller IC (b) Push-pull converter with lag- lead compensator 3.5 Experimental Implementation Hardware Implementation of multi-output push-pull converter in closed loop is carried out with the designed values of components. The results obtained from the hardware implementation are presented and discussed in detail.

19 MOSFET Selection MOSFET is a voltage controlled device and has a positive temperature coefficient, which stops thermal runaway. The ON-state losses can be far lower, as the ON-state-resistance is very low. To particularly deal with limited freewheeling currents, MOSFET also has a body-drain diode. Considering these advantages, the MOSFET has become an unavoidable device for power switch designs. MOSFETs are preferred especially in high frequency applications, wide line or load variations, long duty cycles and low-voltage applications. MOSFET s find application in: Switch mode power supplies (SMPS) Hard switching above 200 khz Soft switching - ZVS below 1000 Watts Battery charging The switching element in a push-pull converter must have a voltage rating high enough to handle the maximum input voltage and the referred secondary voltage. For this push-pull topology, the required minimum voltage rating of the MOSFET is calculated to be 74.49V. Hence an IRF750 N-channel power MOSFET is chosen. This device has a voltage rating of 200V, a continuous DC current rating of 26A and an Rds(on) of 0.1Ω.

20 Diode Selection During the ON time, voltage stress across the diode connected to secondary winding (which is now reverse biased during ON time) is the sum of induced voltage across secondary and output voltage. The reverse voltage across the output-1 diode in Fig 3.3 is calculated to be 35.51V with a peak secondary current of 10A, therefore 16CYQ100C center tap schottky rectifier is selected. This device has a max DC reverse voltage of 100V, maximum average forward current of 16A and a maximum forward voltage drop of 0.82V at 16A. Similarly, for ouput-2 and ouput-3, the reverse voltage across the diode was calculated to be 52.97V and 43.7V, with a peak secondary current of 1A and 0.3A respectively. Therefore for the outputs- 2 and 3, an ultra-fast recovery diode 1N5806 is chosen. This device has a working peak reverse voltage of 150V, average forward current of 2.5A and a maximum forward voltage drop of 0.87V PWM Controller Fig. 3.8(a) illustrates the pulses produced from PWM controller; it is observed that the frequency is 50 khz and duty ratio is 48.4%. Peak voltage of the obtained pulses is found to be 14V. The output of the optocoupler TLP250 is as shown in Fig. 3.8(b), which is used to isolate the two pulses. Peak voltage of the resulting pulses is found to be 14.4V. The duty ratio and frequency remain the same, as obtained from the PWM

21 55 controller IC. The peak to peak output voltage of the PWM controller IC and opto-coupler are 14V and 14.4V respectively. The output of the optocoupler depends only on the Vcc (opto-coupler supply voltage). However the PWM IC outputs duty cycle and frequency have been transmitted through opto-coupler to the MOSFET switches. (a) (b) Fig: 3.8 (a) Pulses from the PWM controller (b) Opto-coupler output Rated outputs Closed loop hardware implementation of multi-output push-pull converter with designed values is carried out at rated load condition. The output voltage and current waveforms obtained are as shown in Fig. 3.9(a) to (c) with the first, second and third output voltage and current values noted as (5V, 0.5A), (12.5V, 0.25A), (12.5V, 0.1A) respectively. (a) (b) (c) Fig: 3.9 (a) First output (b) Second output (c) Third output

22 Line transients For ±15% change in supply voltage, output voltages and currents are obtained. The response of the circuit for decrease in supply voltage from 18V to 16V is as shown in Fig. 3.10(a). From the figure it is observed that the voltage settles at 4.5V from 5V. For the same supply change, the output-2 variation was noted to be 11.5V from 12.5V and 200mA from 210mA, for voltage and current respectively, as shown in Fig. 3.10(b). The decrease in supply results in change from 12.5 to 12V and from 100mA to 90mA for third output voltage and current, in Fig. 3.10(c). The efficiency obtained is about 49% at rated condition. The change in output voltage from the desired value is calculated to be 500mV (5V 4.5V), 1V (12.5V 11.5V) and 500mV (12V 11.38V) for outputs 1, 2, and 3 respectively. (a) (b) (c) Fig: 3.10 For decrease in supply voltage (a) Unregulated output-1 (b) Unregulated output-2 (c) Regulated output Load transients Closed loop implementation of multi-output push-pull converter for load transients are presented and discussed in this section. Load-1 is

23 57 decreased from 10Ω to 5Ω to observe the load regulation and the waveforms obtained for all the loads are presented in Fig. 3.11(a) - (c). In open loop implementation, the output voltage is found to vary when the load resistance is decreased; but for closed loop, as depicted in Fig. 3.11, the output is almost constant for load variations. The change in output voltage from the desired value is calculated to be 890mV (5V 4.11V), 620mV (12.5V 11.88V) and 320mV (12.5V 12.18V) for outputs 1, 2, and 3 respectively. From the results, it is observed that only output-3 (12.5V/100mA) being the supply for controller IC UC3825, is regulated for all load changes applied because of the feedback loop provided from output-3 to UC3825. (a) (b) (c) Fig: 3.11 For decrease in load-1 (a) Unregulated output-1 (b) output-2 & 3 (c) output-1& 3 Fig: 3.12 Hardware prototype

24 58 The cross regulation of the regulated output-3 is within the standard specification (500mV) range as specified in Table 3.4. The cross regulation of output-2 and load regulation of output-1 is above the standard range (100mV & 150mV). This could be overcome by regulating load-2 (12V, 250mA) and output-1 (5V, 0.5A) with individual post regulator IC UC3834 as discussed in the latter section 5.3.4, ringing up the circuits in a printed circuit board, increasing the switching frequency, designing the transformer with less leakage inductance and by using devices of military standards (i.e) by replacing the lab purpose IC UC3825 by UC1825 controller IC which is meant only for military and space applications. The hardware prototype developed is as depicted in Fig Analysis Regulation is a figure of merit for switching power supply. Regulated voltage supply maintains a constant output voltage level against fluctuating input voltage sources and irregular output loads. It is a measure of deviation of voltage over a range of load resistance values. (3.6) VO and VF are the desired output voltage and the actual voltage corresponding to the load. The standard power supply data sheet for avionics, mobile, ground systems and other applications are given in Appendix VI and the important parameters are listed in Table 3.4.

25 59 -VOUT -VOUT Table 3.4 Military avionics power supply specifications Parameter Condition VPT D Units min Typ max Input Voltage Continuous V Transient, 1Sec V Current Inhibited ma No-load ma Ripple Current Full load, 20Hz map-p 10MHz Output Voltage TCASE= 25 0 C V +VOUT TCASE =55 0 C C V +VOUT TCASE= 25 0 C V Power Total VOUT Current VOUT Ripple Voltage VOUT Line Regulation +VOUT -VOUT Load Regulation +VOUT -VOUT Cross Regulation -VOUT TCASE =55 0 C C V Either output W Either output A Full load 20Hz to 10 MHz mvp-p V IN=15 to 50V mv V IN =15 to 50V mv No Load to full load mv No Load to Full Load mv ±Load 70%, ±Load 30% mv Efficiency Full Load % Switching khz frequency Load Step Half Load to Full mvpk Output Transient ±VOUT Load Load Step µsec Recovery Line Step Output VIN = 16V to 40V mvpk Transient ±VOUT Line Step Recovery µsec

26 60 From Table 3.4, it is inferred that the standard for line regulation is 150mV, (i.e) ± 1.23%, load regulation is 100mV, (i.e) ±0.83% and cross regulation is 500mV, (i.e) ±4%. 3.6 Conclusion The multi-output hard switched push-pull converter is designed and implemented experimentally and the results obtained are presented and analysed in this chapter. Hard switching reduces the overall efficiency of the converter and the calculated efficiency is 49%, which is very low. Hence, ZVS multi-output voltage doubler topology is implemented and the same is explained in the next chapter.