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1 Chapter 5 Flyback Converters The flyback converter has long been popular for low-power applications. The major attraction of the flyback topology is its low component count. At higher power levels, the output capacitor ripple current is often too great to deal with using conventional, low-cost capacitors. ynamic response is also limited in continuous conduction mode, because of a right-half-plane (RHP) zero in the transfer function. In the flyback topology, energy is stored in a power inductor (which often has multiple windings, as in a transformer) during the on-time of the switch. uring the off-time of the switch, the energy is delivered to the load. The flyback topology is often used in both discontinuous and continuous conduction modes and can be successfully controlled using current mode or voltage converters. AFlyback Subcircuit A simplified functional schematic diagram of the flyback subcircuit is shown in Fig. 5.. It is included in the Power IC Model Library for PSpice available from AEi Systems. It is a universal subcircuit that is capable of simulating the flyback regulator in both the continuous and discontinuous modes of operation with either voltage mode or current mode control. The derivation of the model is as follows. efined terms P in Converter input power V C Offset error amp output L m Power transformer N P Power transformer ratio magnetizing I min Minimum primary current V out Subcircuit output voltage 5

2 6 Chapter Five :NP V(5) VIN 5 6 V(6) F LP 4 V(3) VC 3 VEE VCC 4 9 ELAY 7 3 CLK Q TS R Q - S 6 :NC 5 45 V(45) VOUT V(9) R RB K* Figure 5. Flyback subcircuit schematic that can be used in both voltage and current modes with discontinuous and continuous inductor currents. I max Peak primary current I out Average output current F sw Switching frequency R b Current transformer burden η Efficiency factor N C Current transformer ratio T s Propagation delay Converter duty cycle T on MOSFET on-time P out Converter output power V in Converter input voltage Governing equations P out = P in η P in = L m ( ) Imax I min F sw I max is defined by the control Voltage V c as I max = V C N C R b The MOSFET on-time is calculated as Since T on = /F sw, + V int s L m T on = L m (I max I min) V in = L mf sw (I max I min) V in N P V out

3 Flyback Converters 7 uring the MOSFET off-time, the primary current falls as I max I min = V ( ) out N P L m F sw while I max I min 0 Substituting equations, ( I min = I max V out N P ) L m F sw V in (I max I min) which can be further simplified as V out I min = I max ( N P L m F sw + V ) while I min 0 out N P V in Substituting equations, I out = L ( ) mf sw I max Imin ( ) + η V out V in N P V out and the duty cycle can be calculated as = L mf sw (I max I min) V in N P V out The circuit shown in Fig. 5. is a simple representation, using the new subcircuit, of a dual-output flyback converter with a separate transformer winding for voltage regulation. The flyback subcircuit essentially replaces the PWM switch model discussed in Chap. 4. The results of the gain-phase measurement of the flyback converter are shown in Figs. 5.3 and 5.4 for a 30-mA load and a -A load on each output, respectively. The circuit has a bandwidth of 7 khz with a phase margin of 75 and a -A load. At a 30-mA load, the performance is quite different because of the discontinuous operation. The 34 khz would likely be a problem for most applications. Either the converter would require a preload or the -A load bandwidth would have to be reduced. This would sacrifice performance. Note that L and C4 are used to break the loop for the open-loop measurement. Voltage source V4 represents the injection signal. This method allows the C path to be closed via L, while the AC information is removed (essentially) by the very low frequency filter created by L and C4. Audio Susceptibility The same SPICE model can be used to evaluate closed-loop performance parameters, such as audio susceptibility. To use the model for these

4 8 Chapter Five VIN X FLYBACK FLYBACK VOUT X3 3 X4 9 N5806 V() +5 V 8 VC RTN UTY C 00U R V4 AC +C4 0 L 0 V(5) V3 5 V(6) FBCK X7 UC843AS C3 N 4 8 REF COMP 6 VC FBK 6 OUT R5 GN.5K R6 47K R4 8K V(3) SENSE 3 X5 R3 MEG 7 N5806 C 00U 8 V(8) -5 R 450 X6 FLY: UAL OUTPUT FLYBACK CONVERTER.TRAN 0U M.AC EC 5 00 MEG.C V OPTIONS RELTOL=.0 ITL=500 ITL=500 ITL4=500 GMIN=n.NOESET V()=5.7.PROBE V()=+5 V(3)=SENSE V(6)=FBCK V(8)=-5 V(5)=.PRINT AC V() VP() V(3) VP(3).PRINT AC V(6) VP(6).PRINT TRAN V(3) V(8).PRINT C V(7) V 08;add AC foraudio Susceptibility Test X3 034 Params: NUM=8 X Params: NUM=8 X Params: NUM=8 X Params: NUM= 9 N N5806 C 0 00U C U R 0 5 ; 5 ohms for A, 450 for 30ma R ; 5 ohms for A, 450 for 30ma R3 4 0 MEG X UC843AS VEA m ; Added for convergence at low currents Figure 5. Schematic design and netlist for a dual-output flyback converter.

5 Flyback Converters 9 R4 38K R5 0.5K C3 8N R6 47K V L ; 0 for open loop Gain/Phase analysis, p for Closed loop analysis (Transient or Audio Susceptibility) C ; 0 for open loop Gain/Phase analysis, p for Closed loop analysis (Transient or Audio Susceptibility) V4 5 0AC X 075FLYBACKParams: L=0U NC=00 NP= F=50K EFF= RB=0 + TS=.5U.EN Figure 5. (Continued). evaluations, the inductor, capacitor, and AC voltage source can be left in the circuit. This is accomplished by changing the value of L to ph, and C4 to pf. To simulate the audio susceptibility performance, an AC source statement must also be added to the input voltage source, V. The results of the audio susceptibility simulation are shown in the graph of Fig Wfm: Phase in eg Wfm: Gain in db (Volts) x < 6.956K M > K 0K 00K Freqency in Hz Figure 5.3 Gain-phase Bode plot of the dual-output flyback converter with a -A load on each output.

6 0 Chapter Five Wfm: Phase in eg Wfm: Gain in db (Volts) K 0K 00K Freqency in Hz Figure 5.4 Gain-phase Bode plot of the dual-output flyback converter with a 30-mA load on each output Attenuation in db (Volts) K 0K 00K Freqency in Hz Figure 5.5 Audio susceptibility simulation results, node.

7 Flyback Converters 460M Control Voltage in Volts 40M 380M 340M 300M Input Voltage in Volts Figure 5.6 Graph showing the nonlinear relationship between the input voltage and the control voltage. Feedforward Improvements The flyback converter has a peak input current that varies with input voltage. This can be seen by sweeping the input voltage and monitoring the control voltage or the output of the error amplifier (see Fig. 5.6). Although this curve is not linear, the audio susceptibility of the flyback converter can still benefit from feedforward compensation. This is most easily added via a simple resistor connected from the input voltage to the current sense pin of the PWM IC. We can add a feedforward signal in series with the control pin of the subcircuit to accomplish the same effect. The schematic showing the incorporation of the feedforward signal is shown in Fig The improvement in audio susceptibility is graphically shown in Fig Note that the feedforward signal improves the audio susceptibility performance by more than 0 db. In several applications, Ihave been able to use this feedforward technique, rather than adding a linear regulator, to obtain the necessary attenuation. There are several benefits. There is no reduction in efficiency performance, as would occur with the addition of a linear regulator. Also, the converter can be made smaller and less expensively without the linear regulator.

8 Chapter Five V 8 Tran 36M 0 359M VIN VC 7.00M time 4.00M X FLYBACK FLYBACK RTN VOUT UTY V(5) 5 Tran M time 4.00M X3 X4 N V() +5 C 00U R 5 V3 5 Tran 537M FBCK 43M.00M time 4.00M V(6) FBCK V(3) X7 UC843AS SENSE C3 N R6 47K 4 8 REF COMP R4 8K 6 3 VC FBK 6 OUT R5 GN.5K X5 7 Tran R3 MEG N5806 C 800U R 5 V(8) -5.00M time 4.00M X6 FLY: FEEFORWAR SIGNAL.OPTION GMIN=0N.NOESET V() = 5.7.TRAN 0U 4M m 0u.PROBE.AC EC 5 00 MEG ALIAS V()=+5 ALIAS V(3)=SENSE ALIAS V(6)=FBCK ALIAS V(8)=-5 ALIAS V(5)=.PRINT AC V(6) VP(6).PRINT AC V() VP() V(3).PRINT TRAN V(3) V(8) V(5) V 08AC X3 034 Params: NUM=8 X Params: NUM=8 X Params: NUM=8 X Params: NUM= 9 N N5806 C 0 00U C U I 0 pulse u.u.u m m ; use for load step analysis R 0 5 R 085 R3 4 0 MEG X UC843AS R4 38K R5 0.5K Figure 5.7 Feedforward signal schematic and netlist.

9 Flyback Converters 3 C3 8N R6 47K V EB 6 7 Value= {.005*V()} X FLYBACK Params: L=0U NC=00 NP= F=50K EFF= RB=0 + TS=.5U.EN Figure 5.7 (Continued). Flyback Transient Response The transient response of the flyback converter is unaffected by the addition of the feedforward signal. The transient response simulation results in Fig. 5.9 show an overlay of a 0.5-A step on the +5-V output with and without the feedforward signal. To calculate the C output resistance, we use the following equations: 5 ( 0.64 ) I l = 5µ ( 50 khz ) =.536 A I pk = I out + I l = =.069 A I rms = I out = =.04 A W:With.005*Vin feedforward in db (Volts) W:Without Feedforward in db (Volts) Figure 5.8 K 0K 00K Frequency in Hz Graph showing improvement in audio susceptibility.

10 4 Chapter Five W: With feedforward +5 in Volts W:Without feedforward +5 in Volts M.6000M M M M Time in Secs Figure 5.9 Transient response simulation results with the unaffected flyback converter. I cap = I out + = =.5 A 0.64 P loss = L l I pk F s + I rms (CR) + I cap (ESR) = ( 350 nh )(.07 ) 50 khz + (.04 ) 0. + (.5 ) 0.03 = W R eff = P loss I out + R d = 0.88 ( ) + 0. = = The resulting 0.6 is a good approximation of the C output resistance. Based on our example, the load regulation from 0% to 00% load would be V = = 0.45 V The actual value that was recorded for the converter was 0.49 V. Obviously, the resistance is nonlinear and dependent upon input voltage, but this is a good estimate. The calculated output resistance was implemented into this SPICE model in order to get the simulation results of Fig. 5..

11 Flyback Converters 5 From the previous simulation, we can obtain the nominal duty cycle of 0.36 with an input voltage of 8 V, or we could calculate it as = V in V out The delta inductor current can be calculated on the basis of the output voltage and : I l = V out L s F s The peak secondary current is calculated as I pk = I out + I l The secondary RMS current can be approximated by I rms = I out The output capacitor RMS ripple current is calculated as I cap = I out + The effects of the diode forward drop can best be approximated by evaluating the difference in forward voltage at two output currents of interest as R d = V f I out The parameters from the power supply design are listed in the following table. L 350 µh I out A L s 5 µh F s 50 khz ESR 0.03 CR N R eff 0. Simulating Regulation One of the more difficult simulations to perform is the C regulation of the flyback converter. The regulation and, more importantly, the crossregulation of a flyback converter is a function of the parasitic leakage

12 6 Chapter Five X FLYBACK FLYBACK VINV V OUT X3 3 X4 9 N5806 V() +5 V 8 VC RTN UTY C 00U R V4 AC +C4 0 L 0 V(5) V3 5 V(6) FBCK X7 UC843AS C3 N 4 8 REF COMP 6 VC FBK 6 OUT R5 GN.5K R6 47K R4 8K V(3) SENSE 3 X5 R3 MEG 7 N5806 C 00U 8 V(8) -5 R 450 Figure 5.0 ual-output 5-V power supply schematic. X6 inductance of the power transformer, the output rectifier characteristics, and the output capacitor equivalent series resistance (ESR). In simple terms, these losses can be viewed as linear power losses. Although this is not entirely true, it will generally provide reasonably accurate results. The one characteristic that will not show up is the large voltage at the output under light-load or no-load conditions. This does not generally pose a problem because there is a protection or limiting device (such as a zener diode) present to make this voltage predictable. The following example is from an actual dual-output 5-V power supply that was designed recently (see Fig. 5.0). Given the following parameters, we will calculate the regulation for incorporation into our SPICE model. efinitions L Power transformer I out Output C current secondary leakage inductance L s Power transformer F s Switching frequency secondary inductance ESR Output capacitor ESR CR Transformer secondary resistance uty cycle uty cycle N power transformer turns ratio I rms RMS secondary current

13 Flyback Converters 7 I pk Peak secondary current I Secondary inductor current delta R d Effective diode resistance R eff Effective average I cap Output capacitor RMS current resistance The total loss of the secondary can be calculated as P loss = L I P F s + I rms CR + I cap ESR FLY3: FEEFORWAR SIGNAL.OPTION RELTOL=.0 ABSTOL=0.u VNTOL=0u GMIN=0N ITL=500 ITL4=500.NOESET V() = 5.7.TRAN 0U 4M M u.probe V()=+5 V(3)=SENSE V(6)=FBCK V(8)=-5 V(5)=.PRINT TRAN V(3) V(8) V(5) V 08 X3 034 Params: NUM=8 X Params: NUM=8 X Params: NUM=8 X Params: NUM= 0 N N5806 C 0 00U C U I 0 pulse u.u.u m m R 0 5 R 085 R3 4 0 MEG X UC843AS R4 38K R5 0.5K C3 8N R6 47K V EB 6 7 Value= {.005*V()} R R X 075FLYBACKParams: L=0U NC=00 NP= F=50K EFF= RB=0 + TS=.5U.EN The simulation results are shown in Fig. 5. along with the previous transient simulation results in order to see the effect of the output resistance.

14 8 Chapter Five Wfm3: +5 in Volts Wfm, Wfm: +5 in Volts Figure M.6000M M M M Time in Secs Transient analysis that shows the effect of the output resistance. Time omain Model The next simulation shows the basic configuration for a transient model of an off-line flyback converter (see Fig. 5.). The transient model allows us to investigate details within the converter, such as peak switch current, harmonic content, output ripple voltage, and many other phenomena that would not be observable using a state space model. Although this model is somewhat simplified, it can easily be upgraded even further. Upgrades could include a nonlinear core model for the power transformer, an input EMI filter, multiple outputs, transformer leakage inductance, etc. In most cases, it is recommended that you start with a basic power supply representation such as this and then add the required details. In fact, each piece can be simulated separately before they are all put together. Using this approach you will have more assurance that the final model will converge, and you can make any necessary changes to the subsections by taking advantage of the superior simulation speed. Obviously, as the model complexity increases, the run time will also increase, thus making investigation of the behavior of each subsection more costly. The simulation results of the transient model are shown in Fig. 5.3.

15 Flyback Converters 9 V3 350V R3 50K R 46K C6 56P Tran 5.88 VERR 385M V(8) VERR R0 3K X7 LT43 0 time CP VREF FB VCC ISENS OUT RT/CT GN 600U X PSW R3 L 4MH Tran 6.6 VOUT -6. X5 XFMR V(9) VPRIM 0 time IOE V() VSECON R 5 600U V(6) VOUT C 68UF R6 45M R4 0K V(5) VSENSE R9 K C4 NF C5 4.7NF V9 PULSE R8.8 LT43: OFF-LINE FLYBACK CONVERTER SPICE NET.TRAN 0.US 0.6MS.MS 0n UIC.PROBE.OPTIONS RELTOL=.005 ITL4=300 V(9)=VPRIM V(6)=VOUT V()=VSECON V(7)=ISENSE V(8)=VERR.PRINT TRAN V(9) V(6) V() V(7) V(8) V V R C UF IC=-4.8V R3 X5 90XFMR Params: RATIO=-0.05 R M 6 IOE OFF.MOEL IOE (TT=NS CJO=PF RS=M) X LT43 R V9 5 0 PULSE U R9 7 4 K C4 7 0 NF C NF R K R 8 46K C6 8 56P Figure 5. Schematic for an off-line flyback converter using a PWM IC model capable of showing all key transient effects. The top-level netlist is also shown.

16 30 Chapter Five R3 6 50K R4 0 0K S9 940SW.MOEL SW VSWITCH RON=. VON=5 VOFF=3 ROFF=E6 L 9 4MH IC=0.EN Figure 5. (Continued ) VOUT in Volts U 50U 350U 450U 550U Time in Secs Wfm: VERR in Volts U 9.3U U 43.08U U Time in Secs Figure 5.3 Transient model results.

17 Flyback Converters 3 V(5) VIN :NP 5 0 V() VOUT V(6) F LP 4 V(3) VC 3 VEE 9 ELAY 7 3 CLK Q 6 5 VCC 4 TS R - Q S :NC 6 V(9) R RB K* Figure 5.4 Schematic of the subcircuit with addition of an external ramp. Adding Slope Compensation The schematic in Fig. 5.4 shows the addition of an external ramp to provide slope compensation to the model. The output of the subcircuit is provided for this purpose. The output is a voltage equivalent of the duty cycle; so a ramp is defined as K*, where K is the peak voltage of the ramp at a duty cycle of. K can also be described as the slope of the ramp divided by the switching frequency. Although we do not have access to the internal nodes required to add the ramp, we can rotate it through the comparator and easily add it externally. A nonlinear dependent source is used to provide the multiplication of K and. The schematic in Fig. 5.5 shows the implementation of the slope compensation ramp that is external to the subcircuit. V(5) VIN :NP 5 0 V() VOUT V(6) V(33) VC 33 F LP 4 44 VEE 9 ELAY 7 3 CLK Q 6 5 VCC 4 TS R Q - S :NC 6 V(9) R RB K* Figure 5.5 Schematic of the subcircuit with the addition of an external ramp using a nonlinear dependent source.

18 3 Chapter Five Voltage Mode Control Using a further extension of the circuit shown in Fig. 5.5, voltage mode control (also called duty cycle control) can be implemented. In this case there is no current sensed, so RB would ideally be set to zero. However, RB cannot be set to zero because it would result in a divide by zero error within the subcircuit. It can, however, be set to a very low value such as m or lower, if necessary. Setting K to will result in a duty cycle that is equal to the control voltage, V C. The modulator gain may also be represented in this subcircuit by setting K equal to /V r, where V r is the peak-to-peak voltage of the ramp. Within the subcircuit, V C is bounded between 0 and V. To use this limiting function, it is recommended that you set K to and add the modulator gain externally.