Practical Feedback-loop Design of Bus Converters Supplying Regulated Voltage to DC-Input-Port Converters

Transcription

1 Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters Dr. Marna Sanz IEEE member (PELS, IES an IE) Assocate Professor Power Electroncs Systems Group (GSEP) Ava. Unversa, Leganés Mar SPAIN Emal: Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 1

2 GSEP s a research group of Carlos III Unversty of Mar Mar Polytechnc School Leganes Campus Leganes Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 2

3 Outlne Lesson 1: Stablty of Dc Power Dstrbuton Systems Lesson 2: Feebackloop esgn conseratons for the BUS converter Lesson 3: Complete characterzaton of the nput mpeance of a DCnputPort Converter Lesson 4: Input mpeance estmaton of commercal DCnputPort Converters Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 3

4 Outlne Trens n Dc Power strbuton systems Arqutectures of man applcatons Man challenges Interacton between cascae converters Constant power loa effect Equvalent smallsgnal crcut Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 4

5 Outlne Trens n Dc Power strbuton systems Arqutectures of man applcatons Man challenges Interacton between cascae converters Constant power loa effect Equvalent smallsgnal crcut Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 5

6 Centralze archtecture Before Snce 2000 Telecom applcaton PROS Power processng technology, thermal management, control, protecton, etc. s ntegrate nto a sngle unt Can be purchase or manufacture as a stanalone system CONS Customze esgn, meanng long tmetomarket an lack of flexblty Falure of the converter means falure of the whole system. Statc an ynamc regulaton of DC voltage s poor. Sngle power converter elvers power to the loas through multple outputs Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 6

7 Dstrbute archtecture Before Snce 2000 Isolate DC/DC 5 V Loa Telecom applcaton AC Input AC/DC converter Bus 48 V Battery Isolate DC/DC Isolate DC/DC. 3.3 V 1.8 V Loa Loa Stanarzaton (commercal offtheself (COTS) converters) Reuce tmetomarket an evelopment cost Reunancy Improve relablty Onlne replacement (hotswappng) Mantenance n nonnterruptng way Decouplng between loa an source ynamcs Loa can be supple wth hgh ynamc response The loas are supple by a number of small power converters whch are strbute throughout the system to perform the power processng close to the loa Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 7

8 Dstrbute archtecture Before Snce 2000 Telecom applcaton Isolaton s prove by the bus converter Nonsolate converters are te to the ntermeate bus an supply each loa (Pontofloa converters) An solate bus converter creates an ntermeate regulate or unregulate (12 V) bus from the man (48 V) bus Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 8

9 SmallScale Power System for Telecommuncaton Applcaton DC/DC Pont of Loa 2.5 V Loa AC nput AC/DC Fronten converter Bus 48 V DC/DC Isolate bus converter Bus 12 V DC/DC Pont of Loa DC/DC Pont of Loa 3.3 V 5 V Loa Loa. Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 9

10 SmallScale Power System for Telecommuncaton Applcaton DC/DC Pont of Loa 2.5 V Loa AC nput AC/DC Fronten converter Bus 48 V DC/DC Isolate bus converter Bus 12 V DC/DC Pont of Loa DC/DC Pont of Loa 3.3 V 5 V Loa Loa Development of behavoral moels that only moel the nput an the output sutable not for converter analyss but for system analyss Voltage (V) Tme (ms) Prect system nstablty Moel smulaton Measure Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters v Current (A) Y o H Tme (ms) Z o v G o o v o Moel smulaton Measure 10

11 Power strbuton n HghPower Energy Harvestng System Canary Islans (SPAIN) Wave Energy Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 11

12 Wave Energy Power Dstrbuton System 1000 V Gr converter Constant power Sea level Upcomng wave DC Bus DC DC or DC AC DC or AC gr Auxlary servces Floatng buoy generator an rve Cbus Brectonal converter DC DC 320 V Auxlary boost converter DC DC Auxlary DC Bus 400 V DC DC Instrumentaton Communcatons Wave power absorber Energy storage (batteres / supercap) DC AC Pump Compressor Wave Energy s use for gr an selfconsumpton snce autonomus system must fe auxlary systems Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 12

13 More Electrc Transport optmze performance ecrease operatng an mantenance costs ncrease spatch relablty Reuce envronmental mpact 270 V DC Engne Starter /Generator AC/DC Brectonal PLMU 3Ø DC/AC converter HghVoltage DC Loas 3Ø AC Loas 115 V AC 400Hz Fuel Cell DC /DC Converter Auxlary Power Unt Hgh Voltage Battery DC /DC 28V DC DC/DC DC/DC Battery DC Loas Multple prmary energy sources types an multple electrc loas Network of power electroncs converter s requre Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 13

14 New challenges n stablty of Power Dstrbuton Systems DC/DC Pont of Loa 2.5 V Loa AC nput AC/DC Fronten converter Bus 48 V DC/DC Isolate bus converter Bus 12 V DC/DC Pont of Loa DC/DC Pont of Loa 3.3 V 5 V Loa Loa. Gr converter generator an rve Cbus DC Bus DC DC or DC AC DC DC Brectonal converter 320 V DC or AC gr Auxlary boost converter DC DC Energy storage (batteres / supercap) 400 V Auxlary DC Bus DC DC DC AC Multple converters nteractng COMPLEX DYNAMIC BEHAVIOR 270 VDC Engne Starter /Generator AC/DC Brectonal PLMU 3Ø DC/AC converter HghVoltage DC Loas 3Ø AC Loas 115 VAC 400Hz Fuel Cell DC /DC Converter AuxlaryPower Unt Hgh Voltage Battery 28VDC DC /DC DC/DC DC/DC Battery DC Loas Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 14

15 New challenges n stablty of Power Dstrbuton Systems DC/DC Pont of Loa 2.5 V Loa AC nput AC/DC Fronten converter Bus 48 V DC/DC Isolate bus converter Bus 12 V DC/DC Pont of Loa DC/DC Pont of Loa 3.3 V 5 V Loa Loa. AC/DC Converter DC/DC Isolate bus converter Use of commercal offtheself (COTS) converters Not enough manufacturer ata to parameterze a moel Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 15

16 Outlne Trens n Dc Power strbuton systems Arqutectures of man applcatons Man challenges Interacton between cascae converters Constant power loa effect Equvalent smallsgnal crcut Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 16

17 Man goal for BUS converter control esgn DC/DC Pont of Loa 2.5 V Loa AC nput AC/DC Fronten converter Bus 48 V DC/DC Isolate BUS converter Bus 12 V DC/DC Pont of Loa DC/DC Pont of Loa 3.3 V 5 V Loa Loa. Loa voltage Loa voltage DC BUS Voltage DC BUS Voltage Loa current Loa current DC bus current DC bus current Feebackloop esgn for Smallsgnal Stablty of DC bus Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 17

18 Behavor at nput port of unregulate DC/DC power converters Swtchng converter (contnuous conucton moe) G V V 0 G C L Flter R 0 rvng sgnal ON OFF ON OFF T ON T OFF T T ON T T ON OFF T T ON V G 1 Flter Gan vo V T D T 0Hz fs khz T D T A DC/DC converter s an electronc crcut that conssts on a chopper an a lowpass flter that supples DC voltage to the loa Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 18

19 Behavor at nput port of unregulate DC/DC power converters Swtchng converter (contnuous conucton moe) G V V 0 G C L Flter R 0 rvng sgnal ON OFF ON OFF T ON T OFF T T ON T T ON OFF T T ON I G 1 : L Low frequency Z 1 : v G C R V 0 At low frequency, un unregulate converter behaves as a postve resstor at ts nput port Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 19

20 Behavor at nput port of regulate DC/DC power converters Swtchng converter G L Sensor V V 0 G C R 0 G I G Moulator V fb β V 0 V ref Compensator V G v G At frequences lower than the banwth of the feebackloop, ue to the acton of the control (perfect trackng of the reference) Vocte Pocte Pcte (power balance) If the nput voltage ncreases, the nput current ecreases an vce versa At low frequency, a regulate DC/DC converter behaves as a constant power loa (CPL) Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 20

21 Other DCnput port converters: Inverter S 1 S 3 S 5 A D 1 A B D 3 B C D 5 C V G S 2 D 2 S 4 D 4 S 6 D 6 Threephase DC/AC converter Swtchng block V G Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 21

22 Behavor as CPL of other DCnput port converters Threephase DC/AC converterwth q control (grte nverter) Swtchng block At frequences lower than the banwth of the feebackloop, ue to the acton of the control (perfect trackng of the reference) Pocte Pcte V G Reference Actve power p ref Reactve power q ref Control Reference generator I _ref I q_ref Compensator Compensator q Moulator a RFT b q c a RFT b q c Sensor Sensor Sensor RFTReference Frame Transformaton At low frequency, a regulate DC/AC converter behaves as a CPL Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 22

23 The smallsgnal moel of a constant power loa I 1 Q1 v n R cpl1 V 1 v I 2 Q2 V 2 v n R cpl 2 v In smallsgnal varatons the constant power loa behavor can be moele as a negatve resstor that epens on the operatng pont The worst case regarng system stablty shoul be consere as operatng pont for the esgn Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 23

24 Effect of negatve loa resstor Resstor voltage Ω Resstor voltage Ω A negatve resstor loa s unstable!!! A smple ynamc system such as LC flter s unstable wth negatve resstor snce the flter ampng s negatve Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 24

25 Expermental valaton of the smallsgnal behavor of DC/DC converter at the nput port Setup for tme oman Osclloscope Vc zo 0.181Ω/40.6 µh C100mF CH1 CH2 CH3 CH4 R2loa R1loa Power supply cc Converter Longwre effects Setup for frequency sweep Vc zo 0.181Ω/40.6 µh C100mF vbus Z Rloa Frequency response analyzer Power supply cc Converter Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 25

26 COTS: Unregulate DC/DC converter IB050E120T32N100 Magntue (Ω) A 2A Postve resstor at low frequency Frequency (Hz) OUTPUT VOLTAGE INPUT VOLTAGE 20 0 OUTPUT CURRENT Phase ( ) A A INPUT CURRENT Frequency (Hz) Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 26

27 COTS: Regulate DC/DC converter HPQ12/25D A Negatve resstor at low frequency Magntue (Ω) A OUTPUT VOLTAGE Frequency (Hz) INPUT VOLTAGE A OUTPUT CURRENT Phase ( ) Frequency (Hz) 7A INPUT CURRENT Play veo Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 27

28 Analyss of power system stablty DC/DC Pont of Loa 2.5 V Loa AC nput AC/DC Fronten converter Bus 48 V DC/DC Isolate BUS converter Bus 12 V DC/DC Pont of Loa DC/DC Pont of Loa 3.3 V 5 V Loa Loa. V Source converter Vbus LOAD converter Vo R LOAD converter Vo R A smple system consstng on cascae converters shoul be analyze Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 28

29 Equvalent moel for smallsgnal stablty analyss CloseLoop output mpeance, Zo(s) CloseLoop nput mpeance, Z(s) V Source converter Vbus LOAD converter Vo R Source Converter Zo(s) Loa Converter V Vbus Z(s) Smallsgnal systemlevel stablty can be well explane by makng use of smallsgnal mpeancebase moels Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 29

30 Stablty of lnear ynamc systems X (s) X e (s) G (s) X O (s) X X O ( s) ( s) 1 G( s) G( s) H ( s) G( s) 1 T ( s) X re (s) H(s) Control to output transfer loop gan or Loop Gan Loop Gan 10 Gan ncrease Loop Gan 200 The stablty of the close loop system s etermne from the control to output transfer functon, T(s) G(s) H(s) or open loop gan or smply loop gan It s suppose to be a negatve feeback structure but there s a ark se Stable Oscllaton Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 30

31 The ark se of the negatve feeback G an H blocks epen on frequency. At the frequency f 180, the phase of loop gan s 180º. Postve feeback!!!! If at ths frequency (f 180 ) the moule of the loop gan s equal to 1, the oscllaton contons are fnally comple: G j2 f ) H( j2 f ) 1 π π ( Close loop transfer functon at f 180 CL vo G G 180 V G H 1 1 f ref f f 180 Infnte gan means that wthout any nput, an output voltage s obtane G(s) H(s) G( jω 180 º ) H( jω 180º ) < 1 Stable Negatve feeback The oscllaton ampltue progressvely ecreases. G(s) H(s) G jω 180 º ) H( jω 180 ) > 1 ( º Postve feeback Exponental growth of the oscllaton Unstable Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 31

32 General Crteron for stablty of lnear ynamc systems X (s) X e (s) X re (s) G (s) H(s) X O (s) X X O Nyqust Crteron ( s) ( s) 1 G( s) G( s) H ( s) G( s) 1 T ( s) Control to output transfer loop gan or Loop Gan T (s) Im T(s) Im T(s) ( 1 0j) ( 1 0j) Re T(s) Re T(s) Stable Unstable The system s stable f T(s) oes not encrcle pont 10j Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 32

33 Nyqust Crteron for smallsgnal stablty of the converter nteracton X (s) X e (s) X re (s) G (s) H(s) X O (s) X X O ( s) ( s) 1 G( s) G( s) H ( s) G( s) 1 T ( s) Control to output transfer loop gan or Loop Gan Nyqust Crteron Source V Zo(s) Vbus Loa Z(s) Vbus( s) V( s) Mnor Loop Gan Z( s) Z( s) Zo( s) 1 T ( s) Zo( s) Z( s) 1 Zo( s) Z( s) Nyqust crteron shoul be satsfe by smallsgnal mpeance rato T(s) Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 33

34 Stablty Crtera for Dc Power Dstrbuton systems Vbus( s) V( s) Loop Gan Z( s) Z( s) Zo( s) 1 T ( s) Zo( s) Z( s) 1 Zo( s) Z( s) Nyqust Crteron Im T(s) ( 1 0j) Re T(s) Stable Stable f Zo( s) T ( s) < 1 Z( s) Mlebrook Crteron s the most conservatve but s the smplest approach snce only t only takes nto account the magntue of both mpeances Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 34

35 Example of system stablty analyss: Man agram block System 1: UNREGULATED SOURCE CONVERTER UNREGULATED LOAD CONVERTER System 2: UNREGULATED SOURCE CONVERTER REGULATED LOAD CONVERTER DC/DC Converter Unregulate (Buck 1) DC/DC Converter Unregulate (Buck 2) DC/DC Converter Unregulate (Buck 1) DC/DC Converter Regulate (Buck 2) VoltageMoe Control Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 35

36 Example of system stablty analyss: The converters s L System 1: UNREGULATED SOURCE CONVERTER UNREGULATED LOAD CONVERTER L v gs V V bus V 0 C C R 0 System 2: UNREGULATED SOURCE CONVERTER REGULATED LOAD CONVERTER s L L v gs V V bus V 0 C C R 0 Moulator V fb β V 0 V ref Compensator Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 36

37 Behavor of an unregulate converter at ts output port Swtchng converter (contnuous conucton moe) L V V 0 C R 0 o Z o I 1 : L v C V 0 R 0 I 1 : L v C V 0 R 0 No varatons of the nput voltage The smallsgnal moel at the output port s the output flter of the converter Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 37

38 Input an output mpeances Output mpeance: source converter Input mpeance: loa converter Unregulate Regulate Buck 1 (Source) Buck 2 (Loa) Buck 2 (Loa) Magntue_Zo Magntue_Z Magntue_Z MagntuZof FaseZof 100 ncreasng 90º ecreasng 90º Frequency (Hz) MagntuZc FaseZc 100 0º cte ecreasng Phase_Zo Phase_Z Phase_Z 90º Frequency (Hz) MagntuZc FaseZc 100 cte 180º ecreasng 90º Frequency (Hz) Z o Z R 2 Z Rcpl Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 38

39 Stablty Crteron System 1: UNREGULATED SOURCE CONVERTER UNREGULATED LOAD CONVERTER System 2: UNREGULATED SOURCE CONVERTER REGULATED LOAD CONVERTER 20 MagntuZof FaseZc_9A MagntuZc_1A Z1 20 MagntuZof MagntuZc_1A MagntuZc_9A Z Z2 Io Zo FaseZof FaseZc_9A FaseZc_1A 0º 90º 90º Frequency (Hz) Z2 Io FaseZof FaseZc_1A FaseZc_9A 0º 180º 90º Zo Frequency (Hz) º ( 1 0j) Io ( 1 0j) STABLE Zo ( s) T ( s) Z ( s) Constant Power Loa Behavour makes possble T encrcles the pont (10j) gvng as a result system nstablty Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters Io UNSTABLE 39

40 Transent response System 1: UNREGULATED SOURCE CONVERTER UNREGULATED LOAD CONVERTER System 2: UNREGULATED SOURCE CONVERTER REGULATED LOAD CONVERTER Io 10 o Current Loa of Buck 2 (Io) Current Loa of Buck 2 (Io) Vo Output Voltage (Vo) Vo Output Voltage (Vo) Vbus Bus Voltage (Vbus) Vbus Bus Voltage (Vbus) Tme (s) STABLE Tme (s) UNSTABLE The system s unstable when the converter loa s regulate, an so behaves as constant power loa Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 40

41 Summary AC nput AC/DC Fronten converter Bus 48 V DC/DC Isolatebus converter Bus 12 V DC/DC PontofLoa DC/DC PontofLoa DC/DC PontofLoa. 2.5 V Loa 3.3 V 5 V Loa Loa DISTRIBUTED ARCHITECTURES USE OF COMMERCIAL CONVERTERS WITH UNKNOWN PARAMETERS The nteracton of two cascae converters shoul be analyze Melbrook Crteron s the smplest approach V Source converter Vbus LOAD converter Vo R Desgn closeloop output mpeance of source converter Calculaton of the closeloop nput mpeance of the loa converter Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 41

42 Outlne Lesson 2: Feebackloop esgn conseratons for the BUS converter Refreshng basc concepts Complete characterzaton of the output port of the BUS converter Output mpeance shapng below the nput mpeance envelope Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 42

43 Outlne Lesson 2: Feebackloop esgn conseratons for the BUS converter Refreshng basc concepts Complete characterzaton of the output port of the BUS converter Output mpeance shapng below the nput mpeance envelope Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 43

44 Feeback loop objectve Output Perturbaton O The output current can change Input Perturbaton v n The nput voltage can change Power converter L O A D control magntue Measure magntue Control Reference Zero error n steay state (perfect trackng of the reference) Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 44

45 Output Voltage Uner Loa Current & Input Voltage Steps Input Perturbaton s L O Output Perturbaton v gs v n v 0 C R 0 The output current can change The nput voltage can change v n Input voltage step (postve ncrement) Duty cycle (control varable) O Output current step (postve ncrement) Auosusceptblty Varaton of the output voltage ue to the nput voltage change v 0 Overshoot V O V O V O Output mpeance Varaton of the output voltage ue to the output current change Unershoot Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 45

46 The nature of DCDC converters an stablty theory NON LINEAR L v G V a NON LINEAR LINEAR LINEAR V REF Swtchng converters are NON LINEAR SYSTEMS. However, 1 Conserng the average value 2 An small varatons aroun the operatng pont Then, the converter can be consere lnear L Q Nyqust stablty crteron to esgn the feeback loop Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 46

47 Equvalent Lnear System Swtchng converter V G V 0 Moulator L C Compensator Sensor V fb β V 0 V ref R 0 Dynamc moellng of the swtchng converter: 1 2 Averagng Block agram of the equvalent lnear system G(s) J. A. Olver, J. A. Cobos, J. Ucea, M. Rascon, C. Qunones Systematc approach for evelopng largesgnal average moels of multoutput PWM converters. IEEE Proc. PESC, vol.2, pp , 2000 Lnearzaton & perturbaton A. Kslovsk, R. Rel, an N. Sokal, Dynamc Analyss of SwtchngMoe DC/DC Converters, New York: Van Nostran Renhol, A lnear moel of the converter s obtane G v vˆ ˆ O vˆ REF vˆ ERR Compensator Moulator ˆ Plant G V vˆ O vˆ FB H(s) Sensor Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 47

48 Nyqust Stablty Crteron G(s) vˆ REF vˆ FB vˆ ERR Compensator R(s) Moulator M(s) ˆ Plant G v (s) vˆ O Close loop transfer functon V CL( s) V O ref ( s) G( s) ( s) 1 G( s) H ( s) Sensor Control to output transfer functon (loop gan): VFB (s) T(s) G( s) H ( s) R(s) M(s) G v (s) H(s) V (s) err H(s) The converter s stable f T(s) oes not encrcle pont 10j Im T(s) ( 1 0j) Stable Re T(s) Desgn the compensator R(s) to T(s) meet Nyqust crteron Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 48

49 Nyqust an Boe Dagrams Nyqust agram Boe agram Im T(s) Re T(s) T ( s) B If the converter s stable, the loop gan T(s) shoul be far enough of pont 10j T (s) Or, the moule of the loop gan T(s) shoul be enough lower than 1 (0B) when the phase of the loop gan T(s) s 180º G jω 180 º ) H( jω 180 ) < 1 ( º Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 49

50 Desgn crtera for Stablty T ( s) B Banwth Crossover frequency, f fc, G(s) H(s) 1 0B f C Boe agram T ( s) B T (s) 180º Phase Margn, PM 0 º 180ºPM T(jωc) PM45º T (s) The phase margn etermnes the stablty of the regulate converter f c 2kHz Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 50

51 Phase Margn an Transent Response PM45º Increasng the PHASE MARGIN provokes a close loop transfer functon wth real poles, whch turns nto a smaller oscllaton n the transent response. f c 2kHz PM45º PM30º PM10º PM1º PM30º PM10º PM1º The phase margn has nfluence on the transent response of the regulate converter Reucng the PHASE MARGIN provokes a close loop transfer functon wth complex poles, whch causes a bgger oscllaton n the transent response. Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 51

52 Complete Block agram of the equvalent lnear system Swtchng converter L V G V 0 C Sensor R 0 loa(s) vˆg Perturbatons î loa Moulator V fb β V 0 V ref Compensator G vg vˆ vˆ O G Z O î vˆ O loa vˆ REF vˆerr Compensator Moulator ˆ Plant G V vˆo vˆfb Sensor Input voltage Auo susceptblty : relatonshp of the nput voltage varatons to the output voltage varatons). Loa Current Output mpeance : relatonshp of the output current varatons to the output voltage varatons). Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 52

53 Outlne Lesson 2: Feebackloop esgn conseratons for the BUS converter Refreshng basc concepts Complete characterzaton of the output port of the BUS converter Output mpeance shapng below the nput mpeance envelope Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 53

54 Output mpeance of the source converter CloseLoop output mpeance, Zo(s) CloseLoop nput mpeance, Z(s) VG DC/DC Converter (SOURCE) Vbus DC/DC converter (LOAD) Vo R Zo (s), termnate Zo (s), termnate The termnate mpeance takes nto account the loa resstor that mposes the steay estate Zo(s), untermnate Zo(s), untermnate VG Source converter Loa Converter The untermnate small sgnal mpeance takes nto account the steay state, but leaves outse the small sgnal effect of the loa resstor because n a cascae connecton t wll not appears. The untermnate mpeance consers the output capactor, because t belongs to the DCDC converter The converter shoul be at the operatng pont (conser c current source at the output) To analyze the system stablty, the untermnate output mpeance must be use Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 54

55 Untermnate versus Termnate output mpeance (OpenLoop) Zo(s), untermnate Zo (s), termnate VG Source converter Loa Converter amp(vo_termnate) amp(vo_termnate)_(open_loop_output_mpeance_source_converter_untermnate) Zo untermnate Zo termnate The untermnate Zo magntue ncreases sgnfcantly phase(vo_termnate) phase(vo_termnate)_(open_loop_output_mpeance_source_converter_untermnate) 0.1K 0.05K 0K 0.05K 0.1K 0.15K Frequency (Hz) Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 55

56 Equvalent lnear crcut for analytcal calculatons Swtchng converter V G V 0 (s) v C rvng sgnal (s) A L C ON OFF ON OFF T ON T OFF T B T ON T T ON OFF T T Dynamc moellng of the swtchng converter: Averagng InjecteAbsorbe Current Equvalent lnear Crcut o(s) (s) Co Ao Bo Lnearzaton & perturbaton Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters ON R 0 Rc C Zc(s) ˆ ( s) 1 2 ˆ ( s) A o v o (s) ZLoa(s) J. A. Olver, J. A. Cobos, J. Ucea, M. Rascon, C. Qunones Systematc approach for evelopng largesgnal average moels of multoutput PWM converters. IEEE Proc. PESC, vol.2, pp , 2000 A. Kslovsk, R. Rel, an N. Sokal, Dynamc Analyss of Swtchng Moe DC/DC Converters, New York: Van Nostran Renhol, A lnear moel of the converter s obtane A ( s) ˆ( s) B ( s) vˆ o loa(s) ( s) ˆ( s) B o 6 coeffcents A an B whch value epens on topology an conucton moe o ( s) vˆ ( s) C o ( s) C ( s) vˆ o G ( s) vˆ ( s) G ( s) 56

57 Applcaton example: Buck converter n CCM (I) L o V n V 0 C R 0 1 Input current an output current as functon of nuctance current 2 Inuctor current as a functon of the rest of specfe values (Vn an vo) 3 Relatonshps Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 57

58 Applcaton example: Buck converter n CCM (II) L o V n V 0 C R 0 (s) o(s) v o (s) (s) v C A B Co Ao Bo Rc C Zc(s) ZLoa(s) loa(s) (s) Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 58

59 Analytcal calculaton of the openloop output mpeance CIRCUIT (s) o(s) v o (s) (s) v C A B Co Ao Bo Rc C Zc(s) ZLoa(s) loa(s) BLOCK DIAGRAM (s) ˆ A O (s) Z L (s) î O î loa B O (s) vˆo 1 î O îloa (s) Z L B O (s) vˆ O Zo, OL( s) Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters vˆ ˆ O loa Z L ( s) 1 B ( s) Z O L ( s) 59

60 Untermnate & Termnate openloop output mpeance Zou,ol Openloop untermnate output mpeance Zot,ol Openloop termnate output mpeance (s) Zo_ol Zou_ol v o (s) (s) v C A B Co Ao Bo Rc C Zc(s) ZLoa(s) loa(s) Output mpeance (s) î loa î ˆ A O (s) O Z L (s) B O (s) vˆo Openloop & termnate Z Openloop & untermnate Z L ( s) Z, Ot OL ( s) ( s) Z, ( s) Zc( s) L Ou OL Zc( s) Z Z ( s) Z c Loa Loa ( s) ( s) The termnate mpeance takes nto account the loa resstor that mposes the steay estate. G v Zo, OL( s) vˆ ˆ O loa Z L( s) 1 B ( s) Z O L The untermnate small sgnal mpeance takes nto account ths steay state, but leaves outse the small sgnal effect of the loa resstor because n a cascae connecton t wll not appears. The untermnate mpeance consers the output capactor, because t belongs to the DCDC converter To analyze the stablty, the untermnate output mpeance must be use Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters ( s) 60

61 Basc calculaton of the closeloop untermnate output mpeance usng sngle control loop: VoltageMoe Control (I) Swtchng converter (buck converter n CCM & Voltage Moe control) loa VG C Co Io vˆ G 0 î loa vˆ REF 0 vˆerr Compensator G(s) Moulator ˆ Plant G V G vg vˆ vˆ O G G Z v O vˆo î vˆ O loa vˆfb H(s) Sensor Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 61

62 Basc calculaton of the closeloop untermnate output mpeance usng sngle control loop: VoltageMoe Control (III) 1 G vˆerr v _ cl Compensator R(s) ( s) Zo _ cl ( s) vˆ ˆ O loa G(s) Moulator M(s) H(s) Sensor ˆ Plant G V (s) î loa Gv( s) Gv( s) 1 Gv( s) M ( s) R( s) H ( s) 1 T ( s) Where Gv s the openloop output mpeance. To calculate the untermnate closeloop output mpeance, Gv must be compute accorngly. G v ( s) Zo _ ol ( s) vˆ ˆ O loa Z L ( s) 1 B ( s) Z O L ( s) G Z v O vˆo î vˆ O loa To etermne the stablty, the untermnate close loop output mpeance (wthout loa resstor) must me use Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 62

63 OpenLoop versus CloseLoop untermnate output Impeance L (Buck converter) V C V 0 R 0 Z o Z ou, OL ( s) 0B T fc Z ou, CL ( s) Z ou, OL ( s) 1 T ( s) Zou,OL Zou,CL f<<f c Zou, CL Zo,OL/T f>>f C Zou, CL Zou,OL The output mpeance of the source converter can be properly esgne by means of the loop gan T(s) Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 63

64 Outlne Lesson 2: Feebackloop esgn conseratons for the BUS converter Refreshng basc concepts Complete characterzaton of the output port of the BUS converter Output mpeance shapng below the nput mpeance envelope Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 64

65 Desgn of the feeback loop of source converter V cc Converter (SOURCE) Vbus cc converter (LOAD) Vo R Source converter Loa Converter Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 65

66 Applcaton esgn example V cc converter (Buck 1) Vbus cc converter (Buck 2) Vo R Magntue Buck 1 (Source) Buck 2 (Loa) Input voltage 12 V 5V Output voltage 5 V 1.5 V Swtchng frequency 20 khz 100 khz Power 20 W 20 W Input capactance 100 µf / 5 mω 100 µf / 5 mω Output capactance 600 µf / 10 mω 150 µf / 5 mω Inuctance 150 µh / 10 mω 30 µh / 1 mω Banwth 100 Hz 20 khz Narrow banwth converter (slow converter) Converter wth fast compensaton (fast converter) Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 66

67 Regulator esgn of source converter Magntue (B) Gv Voltage Regulator Open Loop Phase (egrees) Phase Margn 100 egrees Cross frequency 100Hz R kohm R kohm R kohm C nf C nf C nf Ra 500 Ohm Rb 750 Ohm Vref 3 V Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 67

68 Regulator esgn of loa converter Magntue (B) Voltage Regulator Open Loop Gv Phase (egrees) Phase Margn45 egrees Cross frequency20 khz R11 10 kohm R kohm R kohm C nf C pf C pf Ra Ohm Rb Ohm Vref 1 V Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 68

69 Transent response V cc converter (Buck 1) fsw20 khz V Vo R1 cc converter (Buck 2) fsw100khz Vo R V cc converter (Buck 1) fsw20 khz Vbus cc converter (Buck 2) fsw100khz Vo R Output voltage source converter (fsw20khz) Dc bus voltage Output voltage loa converter (fsw100khz) Output voltage Both converters are nvually stable but the system s unstable Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 69

70 Stablty crteron of the power system V cc converter (Buck 1) Vbus cc converter (Buck 2) Vo R Magntue Buck 1 (Source) Buck 2 (Loa) Input voltage 12 V 5V Output voltage 5 V 1.5 V Swtchng frequency 20 khz 100 khz Power 20 W 20 W Input capactance 100 µf / 5 mω 100 µf / 5 mω Output capactance 600 µf / 10 mω 150 µf / 5 mω Inuctance 150 µh / 10 mω 30 µh / 1 mω Banwth 100 Hz 20 khz closeloop nput mpeance (loa converter) Closeloop nput mpeance of loa converter below crossover frequency Untermnate closeloop output mpeance (source converter) v bus R cpl System s unstable synce Nyqust crteron s not satsfe Zo ( s) > Z( s) Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 70

71 Desgn the Compensator Conserng the Impeance Crteron Source Converter (Buck 1) Zo(s) Loa Converter (Buck 2) Compensator V(s) Vbus(s) Z(s) R V P 2 loa converter loa converter Vbus( s) Vn( s) Z( s) Z( s) Zo( s) 1 Zo ( s) < Z( s) 1 Zo( s) Z( s) Desgn the regulator of the source converter not only to satsfy stablty crteron of the regulator but also to satsfy the mpeance crteron Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 71

72 New compensator esgn of the source converter (Bus converter) Magntue (B) Voltage Regulator Gv Open Loop Phase (egrees) Phase Margn45 egrees Cross frequency 2.5 khz R kohm R kohm R kohm C nf C nf C pf Ra 500 Ohm Rb 750 Ohm Vref 3 V Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 72

73 Stablty crteron of both power systems Compensator esgn 1 Compensator esgn 2 Phase Margn 100 egrees Cross frequency 100Hz Stable stanalone converter Stable stanalone converter Phase Margn 45 egrees Cross frequency 2.5Hz Zo ( s) > Z( s) Unstable system Zo ( s) < Z( s) Stable system Use the nput mpeance of the loa converter as an envelope or mask Set the esgn pont to shape the output mpeance of the source converter below the mask at any frequency Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 73

74 Proper control esgn of the regulator assures system stablty V cc converter (Buck 1) fsw20 khz V Vo R1 cc converter (Buck 2) fsw100khz Vo R V cc converter (Buck 1) fsw20 khz Vbus cc converter (Buck 2) fsw100khz Vo R Output voltage source converter (fsw20khz) Dc bus voltage Output voltage loa converter (fsw100khz) Output voltage Both converters are nvually stable an the system s stable!!! Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 74

75 Usng software tool for automatc esgn of the compensator Bus converter plant (source converter), Gv Bus converter loop gan, T Loa converter Input mpeance, Z Source converter Untermnatte output mpeance, Zo Soluton MAP wth feasble esgns for compensator Analytcal Input an output mpeances of many fferent DC/DC converters Feasble solutons Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 75

76 Summary Lesson 2: Feebackloop esgn conseratons for the BUS converter Calculate openloop untermnate output mpeance (njecteabsorbe current equvalent lnear moel) î î O loa vˆ O Z L ( s) Gv _ OL( s) Zo, OL( s) ˆ A O (s) Z L (s) ˆ vˆo loa 1 BO ( s) Z L( s) Calculate closeloop untermnate output mpeance T (s) 1 Compensator R(s) G(s) B O (s) Moulator Plant G V (s) M(s) H(s) Sensor loa GvZo,OL Calculate compensator to MEET NYQUIST CRITERION IN STAND ALONE OPERATION AND IN THE CONVERTER INTERACTION 180º 0B fc, crossover frequency 180ºPM T(jωc) Z L ( s) Zc( s) Only output capactor as output loa mpeance vo G v _ CL( s) Z Zo o _ cl Gv _ OL( s) ( s) 1 T ( s) Zn Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 76

77 Outlne Lesson 3: Complete characterzaton of the nput mpeance of a DCnputPort Converter Input mpeance of the feebackregulate DC/DC converter Input mpeance of the feebackregulate DC/AC converter The effect of the feeforwar Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 77

78 Outlne Lesson 3: Complete characterzaton of the nput mpeance of a DCnputPort Converter Input mpeance of the feebackregulate DC/DC converter Input mpeance of the feebackregulate DC/AC converter The effect of the feeforwar Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 78

79 Basc concepts of the nput mpeance of regulate DC nput port converters L V V 0 C Sensor R 0 The constant power loa behavor s only val untl crossover frequency of the feebackloop Moulator Compensator V fb β V 0 V ref CPL behavor at low frequency Z v ( s) ( s) negatve resstor I v R cpl V v The smple smallsgnal moel s not val n the whole frequency rangethe feeback loop shoul be stue Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 79

80 Bascs of calculaton of the closeloop nput mpeance: Sngle loop Voltage Moe Control v Z L V V 0 C Sensor R 0 To calculate closeloop nput mpeance Z, t shoul be taken nto account: The openloop uty cycle to output voltage transfer functon (plant) The openloop Auosusceptblty The effect of the output voltage feebackloop that affects the uty cycle an hence the nput current. 0 Moulator V fb β V 0 V ref Compensator G(s) vˆ G vv vˆ vˆ O î loa G Z v O î 0 vˆ O loa vˆ REF vˆfb vˆerr Compensator Rv Moulator Mo ˆ Plant G V X H ( Rv ) Mo vˆo Sensor H Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 80

81 Step 1: Derve the smallsgnal moel of the converter (s) Z 0 (s) v o (s) (s) v C A B Co Ao Bo Rc C Zs(s) (s) ZL(s) The same smallsgnal moel use to erve the analytcal output mpeance can be use Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 81

82 Step 2: Calculate the requre transfer functons (I) 1 Input current expresson v C A B v o (s) Z vˆ C A B vˆo ˆ Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 82

83 Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters Step 2: Calculate the requre transferfunctons (II) ˆ C A B Gv Z (s) Gvv vˆo vˆ ) ( ) ( 1 ) ( ) ( ˆ ˆ ) ( s Z s B s Z s A v s G L O L O O v ) ( ) ( 1 ) ( ) ( ˆ ˆ ) ( s Z s B s Z s C v v s G L O L O O vv Openloop Auosusceptblty Input current expresson Gv v Gvv v o 2 Output voltage expresson Plant o v B A C v 1

84 Step 2: Calculate the requre transferfunctons (III) 1 Input current expresson v C A B vˆ v o Z (s) A C B Gvv Gv vˆo H 3 Duty cycle expresson v ( R ) H Mo o v 1 ˆ Mo Rv 2 v G Output voltage expresson o Plant v Gvv v ( s) vˆ ˆ O Gv AO ( s) Z L( s) 1 B ( s) Z ( s) O L Openloop Auosusceptblty ( s) Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters G vv vˆ vˆ O CO ( s) Z L ( s) 1 B ( s) Z ( s) O L 84 84

85 Analytcal calculaton of the closeloop nput mpeance n Voltage Moe Control (VMC) vˆ VoltageMoe Control (VMC), closeloop C (s) Z A B ˆ T(s) G( s) H ( s) R v Mo Gv (s) Mo(s) G Gvv v Rv vˆo (s) H(s) H 1 (1) (2) (3) (3)(2) (4) (4)(3) (5) v o v Gvv v v v v o o o C A B Gv v ( R ) H Mo v ( X ) v Gvv v Gvv v 1 T v Gvv v ( X ) 1 T Gvv T v Gv 1 T o o ( T ) o Analytcal ervaton of the closeloop nput mpeance s qute complex an teous C v A ( (4)&(5)(1): Gvv Gv T ) 1 T v B Gvv 1 T v Input current expresson Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 85

86 Frequency response of the closeloop nput mpeance n VMC VoltageMoe Control (VMC), closeloop Z fc vˆ C (s) A B Gvv Gv vˆo H Constant 1 Negatve resstor ˆ Mo Rv Z v C A ( 1 Gvv T ) Gv 1 T Gvv B 1 T 180º A regulate converter s not a negatve resstor loa (CPL) n the whole frequency rangethe system can be stable wth a proper esgn of the output mpeance of the source converter Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 86

87 Openloop versus CloseLoop Input Impeance n VMC Low frequency v v n 1 : R cpl Open loop (T0) Postve resstor up to fres close loop Negatve resstor (CPL) up to fc Buck converter (CCM) T Constant Z_CL fres Z_OL fc f res 1 2 π L C Hgh frequency v 1 : 0º Open loop (T0) Output converter flter at f hgher than fres close loop Output converter flter at f hgher than fc 180º Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 87

88 Outlne Lesson 3: Complete characterzaton of the nput mpeance of a DCnputPort Converter Input mpeance of the feebackregulate DC/DC converter Input mpeance of the feebackregulate DC/AC converter The effect of the feeforwar Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 88

89 Basc concepts of the feebackregulate threephase DC/AC converter L_A Voa V L_B Vob Neutral pont L_C Voc Ph A Ph B Ph C PWM Moulator compensator L_A L_B L_C I L ref L measure Sensng an flterng A B C Ph A Ph BL L Ph C L L_A O L_A O C L_C C C C Neutral pont Carga Carga v O_A v O_A v O_C It s not possble to force the currents A, B, C, nepenently snce they are te by the expresson : A B C 0 Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 89

90 Rotatng Space Vector a b c x a x b b abc coornates x c ω X x c x b x a a For 3ph rect sequence magntues, X s a vector that rotates counterclockwse at a rotatng spee ω, that s the frequency gr c The 3ph nstant values of voltage an currents can be represente as projectons of a rotatng space vector over the axes of a 3D space (Park space) Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 90

91 Reference frame transformaton (I) A threephase wre system of sgnals a, b, c fulflls abc 0Map the system nto a bmensonal plane efne by orthogonal coornates αβ b abc β αβ β q ω X ω X ω X a α X Xq α Three statonary axes Two statonary axes Two rotatng axes Rotatng axes Rotatng Space Phasor Statonary Space Phasor c Statonary reference frame Synchronous reference frame (SRF) But the man concept eals wth jont the reference system to the rotatng phasor (q coornates system) Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 91

92 Reference frame transformaton (II) Threephase nstantaneous voltages an currents are seen as two DC quanttes n the Synchronous reference frame Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 92

93 Smple q Control of Threephase GrTe DC/AC converter The control s base on trackng the output actve an reactve power njecte by the DC/AC converter to the gr For a gven 3ph voltage generator, the nstant actve an reactve powers can be expresse on q currents an voltages 3 p 2 ( v v ) q q V p ref 3 q ( v v ) q p v v 2 q v v 2 q q q I _ref Moulatng sgnals n q coornates PI q PWM a b c Moulatng sgnals n abc coornates q ref q 2 3 p v v q 2 q v v 2 q I q_ref PI q q a b c The current references are obtane from the actve an reactve power references Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 93

94 Average Moel of Threephase GrTe DC/AC converter A v V B C Neutral pont A B C V v q q 2 The average moel of the output port of the converter are coupleq components couplng) V q Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 94

95 SmallSgnal Moel of the output port of Threephase GrTe DC/AC converter î L r L ω ˆ q î q L r Lω ˆ V 2 G v mo ˆmo_ Component V 2 G v mo ˆmo_ q Component q ˆ V 2 G mo vˆ mo_ L ω ˆ q 1 L s r ˆ q V 2 G mo vˆ mo_ q L ω ˆ 1 L s r ˆ _ REF εˆ vˆ mo_ V 2 V G mo G 1 L s r î Lω ˆ q _ REF εˆq Compensator (R) vˆ mo_ q Power stage V mo 2 V G G Lω 1 L s r î q Multplenput multpleoutput (MIMO) system s obtane makng ffcult the regulator esgn Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 95

96 q Components Decouplng Concept ˆ V 2 G mo vˆ mo_ L ω ˆ q 1 L s r ˆ _ REF εˆ R vˆ mo_ V V 2 G mo 1 L s r î Lω PLANT î q ˆ _ REF εˆ R vˆ mo_ V V 2 G mo 1 L s r î PLANT ˆ V 2 G mo vˆ mo_ 1 L s r A snglenput sngleoutput (SISO) system s obtane n orer to easy esgn of the compensator Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 96

97 q Components Decouplng by means of FeeForwar Compensaton ˆ V 2 G mo vˆ mo_ L ω ˆ q 1 L s r ˆ _ REF εˆ R FeeForwar Compensaton vˆ mo_ V V 2 G mo 1 L s r î î q Lω Lω PLANT î q ˆ _ REF εˆ R vˆ mo_ V V 2 G mo 1 L s r î PLANT ˆ V 2 G mo vˆ mo_ 1 L s r Compensate the unesre behavor feengforwar the plant wth ts opposte effect Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 97

98 FeeForwar Compensaton of the nput voltage ˆ V 2 G mo vˆ mo_ L ω ˆ q 1 L s r ˆ _ REF εˆ R FeeForwar Compensaton 2 1 V G mo vˆ mo_ V V 2 G mo 1 L s r î î q Lω V Lω î q PLANT ˆ _ REF εˆ R vˆ mo_ 1 L s r î PLANT ( vˆ ) Use feeforwar compensaton to remove the plant varatons uner nput voltage perturbatons ˆ mo_ 1 L s r Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 98

99 SmallSgnal Moel of the output port of Threephase GrTe DC/AC converter wth feeback an feeforwar regulaton ˆ _ REF εˆ R 2 1 V G mo vˆ mo_ V V 2 G mo 1 L s r î î Lω Lω Power stage ˆ q _ REF î q εˆq R q Lω 2 1 V G mo vˆ mo_ q V V G mo 2 G Lω 1 L s r î q Feeback regulaton Feeforwar regulaton Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 99

100 Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 100 Smallsgnal moel of the nput port of Threephase GrTe DC/AC converter q q q q D I D I ˆ 2 3 ˆ 2 3 ˆ 2 3 ˆ 2 3 ˆ Input current expresson v I ˆ 2 3 D ˆ 2 3 q q I ˆ 2 3 q q D ˆ 2 3 Input mpeance expresson v Z

101 Smulaton Example of Threephase GrTe DC/AC converter Power Stage Input voltage perturbaton Z v Reference Frame Transformaton q Current components Reference generaton Compensators Moulator Actve an reactve power calculaton Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 101

102 Smulate Closeloop nput mpeance of threephase nverter As expecte, the nput mpeance s a negatve resstor, snce actve power s tracke, hence constantpower loa (CPL) behavor of the converter s obtane amp(z_promeao) Magntue amp(z_moelo) Constant Z v phase(z_promeao) Phase phase(z_moelo) º Frequency (Hz) Crossover frequency The nput mpeance s a negatve resstor (CPL) even beyon the crossover frequency of the feebackloop Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 102

103 Revew of the control regulaton effects on the nput mpeance Z v V A B v Neutral pont C A B C We have analyze the effect of the feeback but not the feeforwar regulaton effect over nput mpeance p ref q ref q p v v 2 p v v q 2 q v v 2 q q v v 2 q q ˆ _ REF εˆ v R mo_ V 1 V Gmo V G L s r î q Lω 2 G mo Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 2 1 V ˆ FeeForwar Compensaton Lω î q PLANT î 103

104 Outlne Lesson 3: Complete characterzaton of the nput mpeance of a DCnputPort Converter Input mpeance of the feebackregulate DC/DC converter Input mpeance of the feebackregulate DC/AC converter The effect of the feeforwar Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 104

105 Feeforwar objectve O The output current can change Input Perturbaton v The nput voltage can change Power converter L O A D Output Perturbaton control magntue Control Measure magntue Reference FeeForwar technque can be use to ecouple the plant from the external perturbatons Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 105

106 Example Feeforwar of the nput voltage L V I Power s1 C converter R v O (t) Feeforwar Compensaton of nput voltage K V F(v ) G MOD PWM Moulator K V Sensor v mo R(s) v REF The perturbaton mmeately changes the control quantty (most of cases the moulatng sgnal), wthout watng for the response of the compensator Feeforwar s a fast correcton (very hgh banwth) of transent perturbatons n the nput voltage Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 106

107 Feeback an Feeforwar Converter wth feeback regulaton vˆ I O vˆ REF vˆ ERR vˆ Compensator MOD Moulator ˆ Power converter Plant vˆo vˆfb Feeback Sensor v I Converter wth feeback an feeforwar regulaton Vn Feeforwar O vˆ REF vˆfb vˆ ERR Compensator vˆ MOD Moulator O Feeforwar ˆ Power converter Plant vˆo Feeback Sensor Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 107

108 Effect of the nput voltage feeforwar n a DC/DC converter Wthout FF Wth FF Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 108

109 Effect of the feeforwar of the nput voltage L Feeforwar Compensaton of nput voltage K V F(v ) V I Power s1 C converter G MOD PWM Moulator R v O (t) K V Sensor Due to the acton of the feeback regulaton the converter behaves as CPL at frequency lower than the crossover frequency Input voltage v mo R(s) v REF Output voltage Output voltage Wthout FF Wth FF Due to the acton of the feeforwar regulaton the converter behaves as constant power loa n almost whole frequency range The output voltage s almost constant nepenently of the nput voltage Varatons PoctePcte Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 109

110 Effect of the feeforwar of the nput voltage on Inverters Z v V A B v Neutral pont C A B C ˆ vˆ C 1 ( L s r ) p ref q ref q p v v 2 p v v q 2 q v v v 2 q q v 2 q q ˆ _ REF εˆ vˆc v R mo_ V 1 V Gmo V G L s r î q Lω 2 G mo Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 2 1 V Ieal FeeForwar Compensaton ˆ Lω î q PLANT The plant to be controlle oes not epen on the nput voltage, V î 110

111 Threephase nverter has a eal feeforwar of the nput voltage A v V B Neutral pont C A B C V I A (Lne Current) I A (Lne Current) Wthout FF compensaton of V Wth FF compensaton of V Due to the acton of the feeforwar regulaton the converter behaves at constant power loa n the whole frequency range Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 111

112 Summary Lesson 3: Complete characterzaton of the nput mpeance of a DCnputPort Converter vˆ C Z_cl A B Gvv Gv vˆo H The analytcal ervaton of the closeloop nput mpeance s more complex an teous than output mpeance calculatons We nee to know, many fferent transferfunctons. feeforwar ˆ Mo feeback Rv Z _ cl v C A ( Gvv Gv 1 T ) 1 T B Gvv 1 T F(Vn) Closeloop nput mpeance s a negatve resstor only up to crossover frequency of the feebackloop The feeforwar of the nput voltage makes the converter behaves as negatve resstor n the whole frequency range Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 112

113 Outlne Lesson 4: Input mpeance estmaton of commercal DCnputPort of regulate Converters Effects at the DCnputPort of regulate converters Closeloop Input Impeance Estmator Expermental valaton of the estmator wth commercal converters Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 113

114 Outlne Lesson 4: Input mpeance estmaton of commercal DCnputPort of regulate Converters Effects at the DCnputPort of regulate converters Closeloop Input Impeance Estmator Expermental valaton of the estmator wth commercal converters Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 114

115 Problem of nput mpeance analytcal calculaton n case of commercal converters Conser as context, the problem of esgnng the voltage loop of the Source Converter n a typcal strbute supply system for auxlary servces: Auxlary servces Cascae converters DC DC SOURCE CONVERTER DC DC Auxlary DC Bus DC AC LOAD CONVERTERS Unknown loas (nput mpeance) Analytcal technques are not sutable snce nternal parameters are unknown. We nee an Input Impeance Estmator Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 115

116 Effect of Constant Power Loa Behavor v bus P P o V o I o v bus p v bus I v bus R cpl v V A regulate converter behaves at low frequency as a constantpower loa (CPL) n large sgnal. If the nput voltage ncreases, the nput current ecreases an vce versa In smallsgnal, the CPL behavor at low frequency can be moele as a negatve resstor (negatve slope) The negatve resstor value epens on the steaystate operatng contons Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 116

117 Smallsgnal moel of constant power loa v bus P v bus p v bus v bus R cpl V P 2 bus Largesgnal Moel Smallsgnal Moel Large sgnal moel: p v bus Smallsgnal moel: ˆ ˆ F( v v P V bus bus, p ) ˆ V p P vbus 2 bus Vbus v bus 1 bus vˆ pˆ bus F( vbus, p ) p v bus V p P bus pˆ If output power oes not change, nput power oes not change pˆ 0 Small sgnal moel vbus p 2 2 bus Vbus Vbus Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters ˆ P V ˆ ˆ P V 2 bus vˆ 1 bus ˆ P vˆ bus 117

118 Effect of feebackloop T Z Z Negatve low frequency Loop hgh frequency T fc Z The behavour as constant power loa (negatve resstance) s only val untl crossover frequency Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters fc 118

119 Constant power loa & feebackloop effects (fferent control) Magntue (BΩ) Average Current Moe Control Peak Current Moe Control Voltage Moe Control Phase (egrees) Average Current Moe Control Peak Current Moe Control Voltage Moe Control fc Below crossover frequency, the behavor of the converter s the same negatve resstor (CPL) Above crossover frequency, the behavour s not a negatve resstor an epens on the feebackloop Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 119

120 Input capactor of Dc nput port converters CloseLoop nput mpeance, Z(s) Source converter Loa Converter R Vbus C Co Most commercal Dcnputport converters has a capactor connecte at the nput to reuce nput current rpple Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 120

121 Effect of the of the nput capactor Negatve low frequency Loop hgh frequency Z (wthout Cn) Z (wthout Cn) Z (wth Cn) fcpl Z (wth Cn) Negatve low frequency Input hgh frequency 180º 90º f cpl 2 1 π R cpl Cn R cpl V P 2 fc fc The effect of the nput capactor (fcpl) s preomnant over the feeback loop effect Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 121

122 Behavoral moel of the closeloop nput mpeance Z L Constant magntue Z Decreasng magntue V C n R Cn C V o R v R K v v ref Cn100µF 180º 90º G mo Cross frequency Behavoral moel of the closeloop nput mpeance Moelng of the nput port of the converter v Y Z Requre nformaton shoul be obtane from converter measurements or atasheet, no nternal converter parameters are neee Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 122

123 Outlne Lesson 4: Input mpeance estmaton of commercal DCnputPort of regulate Converters Effects at the DCnputPort of regulate converters Closeloop Input Impeance Estmator Expermental valaton of the estmator wth commercal converters Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 123

124 Behavoral moels Gparameters base nputoutput moel o v Y o H Z o v G o v o Input Norton Network Output Thevenn Network Input amttance Y : relatonshp between an v Backcurrent gan H : relatonshp between an o Auosusceptblty G o : relatonshp between v o an v Output mpeance Z o : relatonshp between v o an o Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 124

125 Behavoral moels Gparameters base nputoutput moel Complex measurements plus powerful but complcate entfcaton technques can be use to obtan the complete nformaton of the loa converters nput port EXPERIMENTAL SETUP Power amplfer o DCDC v o Magntue Z o Frequency response analyzer Z o ( s) n an s... a n b s... b n o o Analytcal Ientfcaton technques Phase Z o Frequency Dffcult, expensve an tme consumng to evelop a behavoral moel Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 125

126 Estmator of the closeloop nput mpeance Base on the man effects observe at the nput of the regulate DCnputport converters Z Flter V C n R Cn L C V o R The estmator propose, s the equvalent crcut compose by the nput capactor (Cn) n parallel wth the negatve resstor (Rcpl) K v Z Flter (estmator ) G mo R v v ref Constant magntue Z Flter Decreasng magntue V n R Cn R CPL C n Cn100µF 180º 90º The closeloop nput mpeance can be easly obtane Z Flter Rcpl (1 R ( estmate) 1 ( R R cpl Cn Cn C n ) C s) n s Crossover frequency ONLY THE CONSTANT POWER LOAD RESISTOR VALUE AND THE CAPACITOR VALUE SHOULD BE INDENTIFIED Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 126

127 Closeloop mpeance estmator versus analytcal nput mpeance Magntue (B) Z_estmator (black lne) Z_analytcal (green lne) f cpl 1 V 2 π P 2 Cn Exact calculaton for Buck CCM n Voltage Moe control Z v C A ( 1 Gvv T ) Gv 1 T Gvv B 1 T Estmate calculaton for Buck CCM n Voltage Moe control Z_estmator (black lne) Z Flter Rcpl (1 R ( estmate) 1 ( R R cpl Cn Cn C n ) C s) n s Phase (º) Z_analytcal (green lne) Valaton wth Buck CCM converter n VMC Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 127

128 Valaton wth fferent nput capactor values Buck converter CCM Voltage Moe control Case A Z Flter Z L V C n R Cn C V o R K v G mo R v v ref Case B fc fsw fres Cn RCPL fcpl 20KHz 250KHz 2.2KHz 47uF (A) Hz 20KHz 250KHz 2.2KHz 4.7uF (B) KHz Dfferent nput capactor values The smple estmator s val even when the cuttoff estmator frequency fcpl s close to crossover frequency fc (less than one ecae of the fc) Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 128

129 Same nput capactor esgn but fferent converter an control strategy Buck converter L L Boost converter V C n R Cn C V o R V I C n R Cn s1 C R v O Cn esgne to obtan n any power converter a 5% nput current rpple Dfferent converter topologes (Buck an Boost) Dfferent operatng moes (CCM an DCM) To evaluate f thefferent esgn of nput capactor omnates the hgh frequency effects over feebackloop Dfferent control technques (VMC an ACMC) To evaluate f the fferent control omnates the hgh frequency effects over nput capactor Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 129

130 Analyss of the worstcase for nput mpeance estmator valaton CCM Cn18µF ACMC The nput mpeance estmator has smlar results n VMC an n ACMC CCM Cn18µF VMC The nput mpeance estmator has been valate wth a boost converter n CCM that s the worstcase regarng the effect of nput capactor over the feebackloop effects Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 130

131 Outlne Lesson 4: Input mpeance estmaton of commercal DCnputPort of regulate Converters Effects at the DCnputPort of regulate converters Closeloop Input Impeance Estmator Expermental valaton of the estmator wth commercal converters Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 131

132 Impeance estmator parameters from atasheet v Cn :Input capactor R cpl V P 2 V :Input Voltage P :Input power P Po η V I η o o The atasheet effcency an the operatng contons Vo an Po can be use to calculate the negatve resstor value Only the type of nput flter s specfe Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 132

133 Atonal smple measurements for estmate nput capactor Very smple setup s requre snce the measurement can be one whle the converter s not workng Only a multmeter s requre EXPERIMENTAL SETUP Input mpeance measurement Frequency response analyzer zo R2Ω Z Vc C100mF v Rloa DC power supply DC/DC converter Power amplfer Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 133

134 Accuracy of the estmator n commercal DC/DC converters The nput capactor has been measure, an the nput mpeance estmator has been compare wth the nput mpeance measurement at two fferent output power levels showng goo accuracy Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 134

135 Summary Lesson 4: Input mpeance estmaton of commercal DCnput Port Converters V Z Cn Rcn Mo L C Vo Compensator R Sensor Reference Three effects can be observe at DCnputport converter: Negatve resstance ue to ConstantPower Loa (CPL) behavor Effect of the feeback loop Effect of the nput capactor use to flter nput current rpple The effect of the nput capactor omnates the nput mpeance at hgh frequency. A smple nput mpeance estmator can be consere, whch parameters can be obtane from the atasheet an smple atonal measurements V Z Cn Rcn Rcpl Rcpl (1 R Z ( estmate) 1 ( R R cpl Cn Cn C n ) C s) n s Z magntue Constant magntue (negatve resstance, CPL) Decreasng magntue (capactor) Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 135

136 Outlne Lesson 1: Stablty of Dc Power Dstrbuton Systems Lesson 2: Feebackloop esgn conseratons for the BUS converter Lesson 3: Complete characterzaton of the nput mpeance of a DCnputPort Converter Lesson 4: Input mpeance estmaton of commercal DCnputPort Converters Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 136

137 Fnal Remarks (I) The man stablty problem s ue to the nteracton of cascae converters. The easy way to esgn the feebackloop of the source converter s to apply the Mlebrook s mpeance crteron CloseLoop untermnate output mpeance, Zo(s) CloseLoop nput mpeance, Z(s) V Source converter Vbus LOAD converter Vo R Zn Stable f Zo T Zo ( s ) ( s ) < Z ( s ) 1 Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 137

138 Fnal Remarks (II) Analytcal calculatons of the nput mpeance are qute teous an ffcult n some cases Moreover, analytcal technques are not val n the problem of esgnng the voltage loop of the Source Converter n a typcal strbute supply system for auxlary servces where unknown converter loas an not val for commercal converters. DC DC SOURCE CONVERTER DC DC Auxlary DC Bus DC AC Auxlary servces LOAD CONVERTERS Unknown loas (nput mpeance ) The alternatve s to evelop behavoral moels of the converter. But they are ffcult an tme consumng snce complex measurements plus complcate entfcaton technques shoul be use to obtan the complete nformaton of the loa converters nput port. Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 138

139 Fnal Remarks (III) A smple nput mpeance estmator has been propose base on the smlar effects observe n a converter that has a DC nput port, Negatve resstor at low frequences ue to ConstantPower Loa (CPL) behavor Effect of the compensaton of the feebackloop at hgh frequences Usually, the effect at hgh frequences s omnate by the nput capactor Z magntue Constant magntue (negatve resstor, CPL) Decreasng magntue (capactor) V Z Cn Rcn Rcpl (1 R Z ( estmate) 1 ( R R Rcpl cpl Cn Cn C n ) C s) n s Input Impeance Estmator s a very effectve frstapproach tool to prect cascae converters nstablty. The estmator Is base on: Datasheet nformaton (Rcpl) Smple measurements usng a multmeter (Cn) Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 139

140 Man References an Reangs R. Mftakhutnov, "Power strbuton archtecture for tele an ata communcaton system base on new generaton ntermeate bus converter," INTELEC 2008 M. Blanco, G. Navarro, M. Lafoz, Control of power electroncs rvng a swtche reluctance lnear generator n wave energy applcatons. Proc. European Conference on Power Electroncs an Applcatons, EPE '09, pp. 1 9, 2009 A. Ema et al, "Power electroncs ntensve solutons for avance electrc, hybr electrc, an fuel cell vehcular power systems," IEEE Trans. Power Electron., Y. Xe, et. al "A PCcluster base realtme smulator for all electrc shp ntegrate power systems analyss an optmzaton", IEEE ESTS 2007 M. Sanz, M. Bermejo, A. Lázaro, D. López el Moral, C. Fernánez, P. Zumel, A. Barrao, Smple Input Impeance Converter Moel to Desgn Regulators for DcDstrbute System, 2016 Seventeenth IEEE Workshop on Control an Moelng for Power Electroncs (COMPEL), pp. 16, June 2016 A. Rccobono an Enrco Sant Comprenhesve Revew of Stablty Crtera for DC Power Dstrbuton System, IEEE Trans. On Inustry Applcatons, vol.50, no.5, págs , November 2014 J.Sun, SmallSgnal Methos for AC Dstrbute Power Systems: A revew, IEEE Trans. Power Electron., vol.24, no.11, págs.2547, November 2009 M. Sanz, V. Valva, P. Zumel, D. López el Moral, C. Fernánez, A. Lázaro, A. Barrao, Analyss of the Stablty of Power Electroncs Systems: a Practcal Approach, 29 th IEEE Proc. Apple Power Electroncs Conference (APEC), pp , 2014 A. Kslovsk, R. Rel, an N. Sokal, Dynamc Analyss of SwtchngMoe DC/DC Converters, New York: Van Nostran Renhol, 1991 L. Arneo, D. Boroyevch, R. Burgos, F. Wang, BlackBox Termnal Characterzaton Moels for the Analyss an Smulaton of Dstrbute Power Electronc Systems, IEEE Proc. Power Electroncs Specalsts Conference (PESC), pp , 2007 V. Valva Behavoral Moelng an Ientfcaton of Power Electroncs Converters an Subsystems Base on Transent Response Ph Dssertaton, Carlos III Unversty of Mar, January, Y. Panov, M. Jovanovc, Practcal ssues of nput/output mpeance measurements n swtchng power supples an applcaton of measure ata to stablty analyss, Proc. IEEE Apple Power Electroncs Conference an Exposton (APEC), pp: , 2005 M. Sanz, A. Lázaro, C. Fernánez, P. Zumel, D. López el Moral, I. Quesaa, A. Barrao, Practcng Desgn Metho of Regulators for Cascae Converters, IEEE Proc. 14th Workshop on Control an Moelng for Power Electroncs (COMPEL), pp. 15, 2014 M. Sanz; A. Lazaro; M. Bermejo; D. Lopez el Moral; P. Zumel;C. Fernanez; A. Barrao, Lowcost nput mpeance estmator of DctoDc converters for esgnng the control loop n cascae converters, 2016 IEEE Apple Power Electroncs Conference an Exposton (APEC), pp , March 2016 Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 140

141 Contact: Emal: Practcal Feebackloop Desgn of Bus Converters Supplyng Regulate Voltage to DCInputPort Converters 141