Linear Building Block Low-Power Voltage Reference with Dual Op Amp, Dual Comparator, and Shutdown Mode

Transcription

1 Linear Building Block Low-Power Voltage Reference with Dual Op Amp, FEATURES Combines Two Op Amps, Two s and a Voltage Reference into a Single Package Optimized for Single-Supply Operation Small Package Pin QSOP Ultra Low Input Bias Current... Less than 1pA Low Quiescent Current... Operating 16µA (Typ.) Shutdown 6µA (Typ.) Rail-to-Rail Inputs and Outputs Operates Down to = 1.8V Reference and One Remain Active in Shutdown to Provide Supervisory Functions APPLICATIONS Power Management Circuits Battery Operated Equipment Consumer Products Replacements for Discrete Components FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION The is a mixed-function device combining two general purpose op amps, two general purpose comparators, and a voltage reference in a single 16-Pin package. This increased integration allows the user to replace two or three packages, saving space, lowering supply current, and increasing system performance. A Shutdown input, SHDN, disables the op amps and one of the comparators, placing their outputs in a high-impedance state. The reference and one comparator stay active in Shutdown mode. Standby power consumption is typically 6µA.Both the Op Amps and comparators have rail-to-rail inputs and outputs which allows operation from low supply voltages with large input and output signal swings. Packaged in a 16-Pin QSOP, the is ideal for applications requiring high integration, small size, and low power. PIN CONFIGURATION (QSOP) A1 IN A1 IN AMP 1 A1 OUT A1 IN 1 16 A1 IN A IN A1 OUT A OUT A IN 4 _EQR 1 C1 IN A IN A OUT C1 OUT 5 1 C1 IN A IN C1 OUT AMP CMPTR 1 C1 IN C1 IN C OUT SHDN V SS C IN C IN V REF C OUT SHDN CMPTR C IN C IN ORDERING INFORMATION Temperature Part No. Package Range V SS Voltage Reference V REF CEQR 16-Pin QSOP 4 C to 85 C 1-1/1/

2 Linear Building Block Low-power ABSOLUTE MAXIMUM RATINGS* Supply Voltage...6.V Voltage on Any Pin: (With Respect to Supplies).. (V SS.V) to (.V) Operating Temperature Range:... 4 C to 85 C Storage Temperature Range C to 15 C Lead Temperature (Soldering, 1 sec)... 6 C * Static-sensitive device. Unused devices must be stored in conductive material. Protect devices from static discharge and static fields. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to Absolute Maximum Rating Conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS: Typical values apply at 5 C and =.V. Minimum and maximum values apply for T A = 4 to 85 C and = 1.8V to 5.5V, unless otherwise specified. Symbol Parameter Test Conditions Min Typ Max Unit Supply Voltage V I Q Supply Current, Operating All outputs unloaded, SHDN = 16 µa I SHDN Supply Current, Shutdown CMPTR and V REF Outputs 6 1 µa unloaded, SHDN = V SS Shutdown Input V IH Input High Threshold 8% V V IL Input Low Threshold % V I SI Shutdown Input Current ±1 na Op Amps T SEL Select Time (V OUT from SHDN = V IH ) R L =1KΩ to V SS 15 µsec T DESEL Deselect Time (V OUT from SHDN = V IL ) R L =1KΩ to V SS 1 nsec R OUT (SD) Output Resistance in Shutdown SHDN = V SS MΩ C OUT (SD) Output Capacitance in Shutdown SHDN = V SS 5 pf A VOL Large Signal Voltage Gain R L = 1 KΩ, = 5V 1 V/mV V ICMR Common Mode Input Voltage Range V SS.. V V OS Input Offset Voltage = V, V CM = 1.5V, T A = 5 C, ±1 ±5 µv T A = 4 C to 85 C ±. ±1.5 mv I B Input Bias Current T A = 5 C, V CM = to V SS pa V OS (DRIFT) Average Izut Offset Voltage Drift = V, V CM = 1.5V 4 µv/ C GBWP Gain-Bandwidth Product = 1.8V to 5.5V; V O = to V SS 9 KHz SR Slew Rate C L = 1pF R L = 1MΩ to GND Gain = 1 V IN = V SS to 5 mv/µsec V OUT Output Signal Swing R L = 1 KΩ V SS V.5.5 CMRR Common Mode Rejection Ratio T A = 5 C, = 5V 7 db V CM = to V SS PSRR Power Supply Rejection Ratio T A = 5 C,V CM = V SS 8 db = 1.8 to 5V I SRC Output Source Current V IN =, V IN = V SS, ma Output Shorted to V SS = 1.8V, Gain = 1 I SINK Output Sink Current V IN = V SS, V IN =, 4 ma Output Shorted to = 1.8V, Gain = 1-1/1/

3 Linear Building Block Low-power ELECTRICAL CHARACTERISTICS: (Cont.) Typical values apply at 5 C and =.V. Minimum and maximum values apply for T A = 4 to 85 C and = 1.8V to 5.5V, unless otherwise specified. Symbol Parameter Test Conditions Min Typ Max Unit Op Amps (Cont.) en Input Noise Voltage.1 Hz to 1 Hz 1 µv pp s Input Noise Density 1KHz 15 nv/ Hz R OUT (SD) Output Resistance in Shutdown SHDN = V SS MΩ C OUT (SD) Output Capacitance in Shutdown SHDN = V SS 5 pf T SEL Select Time (For Valid Output) V OUT from SHDN = V IH µsec R L =1KΩ to V SS T DESEL Deselect Time V OUT from SHDN = V IL 5 nsec R L =1KΩ to V SS V ICMR Common Mode Input Voltage Range V SS.. V V OS Input Offset Voltage = V, V CM =1.5V, T A = 5 C 5 5 mv T A = 4 C to 85 C 5 5 mv I B Input Bias Current T A = 5 C, IN, IN = to V SS ±1 pa V OH Output High Voltage R L = 1KΩ to V SS. V V OL Output Low Voltage R L = 1KΩ to. V CMRR Common Mode Rejection Ratio T A = 5 C, = 5V 66 db V CM = to V SS PSRR Power Supply Rejection Ratio T A = 5 C, V CM =1.V 6 db = 1.8V to 5V I SRC Output Source Current IN =, IN = V SS 1 ma Output Shorted to V SS = 1.8V I SINK Output Sink Current IN = V SS, IN =, ma Output Shorted to = 1.8V t PD1 Response Time 1 mv Overdrive,C L = 1pF 4 µsec t PD Response Time 1mV Overdrive, C L = 1pF 6 µsec Voltage Reference V REF Reference Voltage V I REF(SOURCE) Source Current 5 µa I REF(SINK) Sink Current 5 µa C L(REF) Load Capacitance 1 pf N VREF Voltage Noise 1 Hz to 1 KHz µv RMS Noise Density 1 KHz 1. µv/ Hz - 1/1/

4 Linear Building Block Low-power DETAILED DESCRIPTION The is one of a series of very low power, linear building block products targeted at low voltage, single supply applications. The minimum operating voltage is 1.8V and typical supply current is only µa (fully enabled). It combines two comparators, two op amps, and a voltage reference in a single package. A shutdown mode is incorporated for easy adaptation to system power management schemes. During shutdown, all but one comparator and the voltage reference are disabled (i.e. powered down and with their respective outputs at high impedance). The still awake comparator and voltage reference can be used as a wakeup timer, power supply monitor, LDO controller, or other continuous duty circuit function. s The contains two comparators. The comparators input range extends beyond both supply voltages by mv and the outputs will swing to within several millivolts of the supplies depending on the load current being driven. The comparators exhibit a propagation delay and supply current which are largely independent of supply voltage. The low input bias current and offset voltage make them suitable for high impedance precision applications. CMPTR1 is disabled during shutdown and has a high impedance output. CMPTR remains active. Operational Amplifiers The contains two rail-to-rail op amps. The amplifiers input range extends beyond both supplies by mv and the outputs will swing to within several millivolts of the supplies depending on the load current being driven. The amplifier design is such that large signal gain, slew rate and bandwidth are largely independent of supply voltage. The low input bias current and offset voltage of the make it suitable for precision applications. Both op amps are disabled during shutdown and have high output impedance. Voltage Reference A. percent tolerance, internally biased, 1.V bandgap voltage reference is included in the. It has a push-pull output capable of sourcing and sinking at least 5 µa. The voltage reference remains fully enabled during shutdown. Shutdown Input SHDN at V IL disables both op amps and one compara- tor. The SHDN input cannot be allowed to float; when not used, connect it to. The disabled comparator s output and the two disabled op amps outputs are in a high impedance state when shutdown is active. The disabled comparator s inputs and the two disabled op amps inputs can be driven from rail-to-rail by an external voltage when the is in shutdown. No latchup will occur when the device is driven to its enabled state when SHDN is set to V IH. TYPICAL APPLICATIONS The lends itself to a wide variety of applications, particularly in battery-powered systems. It typically finds application in power management, processor supervisory, and interface circuitry. Wake-Up Timer Many microcontrollers have a low power sleep mode that significantly reduces their supply current. Typically, the microcontroller is placed in this mode via a software instruction, and returns to a fully enabled state upon reception of an external signal ( wake-up ). The wake-up signal is usually supplied by a hardware timer. Most system applications demand that this timer have a long duration (typically seconds or minutes), and consume as little supply current as possible. The circuit shown in Figure 1 is a wake-up timer made from comparator CMPTR. (CMPTR is used because the wake-up timer must operate when SHDN is active.) Capacitor C1 charges through R1 until a voltage equal to V R is reached, at which point the WAKE-UP is driven active. Upon wake-up, the microcontroller resets the timer by forcing a logic low on a dedicated, open drain I/O port pin. This discharges C1 through R4 (the value of R4 is chosen to limit the maximum current sunk by the I/O port pin). With a V supply, the circuit as shown consumes typically 6 µa and furnishes a nominal timer duration of 5 seconds. Precision Battery Monitor Figure is a precision battery low/battery dead monitoring circuit. Typically, the battery low output warns the user that a battery dead condition is imminent. Battery dead typically initiates a forced shutdown to prevent operation at low internal supply voltages (which can cause unstable system operation). The circuit of Figure uses a single (one op amp is unused) and only six external resistors. AMP 1 is a simple buffer while CMPTR1 and CMPTR provide precision voltage detection using V R as a reference. Resistors R and R4 set the detection threshold for BATTLOW while resistors R1 and R set the detection threshold for BATTFAIL. The component values shown assert - 1/1/ 4

5 Linear Building Block Low-power BATT LOW at.v (typical) and BATT FAIL at.v (typical). Total current consumed by this circuit is typically µa at V. Resistors R5 and R6 provide hysteresis for comparators CMPTR1 and CMPTR, respectively. Dual LDO with Shutdown Figure shows a portion of a configured as a dual low dropout regulator with shutdown. AMP1 and AMP are independent error amplifiers that use V R as a reference. Resistors RA 1, RB 1, RA, and RB set the feedback around the amplifiers and therefore determine the output voltage settings (please see equation in the figure). RA 1, RB 1, RA, and RB can have large ohmic values (i.e. 1 s of KΩ) to minimize supply current. Using the N output transistors as shown, these regulators exhibit low dropout operation. For example, with V OUT =.V, the typical dropout voltage is only 5 mv at an output current of 5 ma. The unused comparators can be used in conjunction with this circuit as power-on reset or low voltage detectors for a complete LDO solution at a very low installed cost. External Hysteresis Hysteresis can be set externally with two resistors using positive feedback techniques (see Figure 4). The design procedure for setting external comparator hysteresis is as follows: 1. Choose the feedback resistor R C. Since the input bias current of the comparator is at most 1 pa, the current through R C can be set to 1 na (i.e. 1 times the input bias current) and retain excellent accuracy. The current through R C at the comparator s trip point is V R / R C where V R is a stable reference voltage. C1 1µF R1 5M V R R4 CMPTR Figure 1. Wake-Up Timer MICROCONTROLLER I/O* WAKE-UP *OPEN DRAIN PORT PIN 5. Determine the hysteresis voltage (V HY ) between the upper and lower thresholds.. Calculate R A as follows. R A = R C ( V HY ) 4. Choose the rising threshold voltage for V SRC (V THR ). 5. Calculate R B as follows: R B = [ ( V THR (V R * R A )) RA R C ] 6. Verify the threshold voltages with these formulas: V SRC rising: V THR = (V R ) (R A ) [( R A ) ( R B ) ( R C ) ] V SRC falling: Equation 1. Equation. Equation. V THF = V THR [ (R A * ) R C ] Equation KHz Time Of Day Clock Crystal Controlled Oscillator A very stable oscillator driver can be designed by using a crystal resonator as the feedback element. Figure 5 shows a typical application circuit using this technique to develop a clock driver for a Time Of Day (TOD) clock chip. The value of R A and R B determine the DC voltage level at which the comparator trips in this case one-half of. The RC time constant of R C and C A should be set several times greater than the crystal oscillator s period, which will ensure a 5% duty cycle by maintaining a DC voltage at the inverting comparator input equal to the absolute average of the output signal. Non-Retriggerable One Shot Multivibrator Using two comparators, a non-retriggerable one shot multivibrator can be designed using the circuit configuration of Figure 6. A key feature of this design is that the pulse width is independent of the magnitude of the supply voltage because the charging voltage and the intercept voltage are - 1/1/

6 Linear Building Block Low-power a fixed percentage of. In addition, this one shot is capable of pulse width with as much as a 99% duty cycle and exhibits input lockout to ensure that the circuit will not retrigger before the output pulse has completely timed out. The trigger level is the voltage required at the input to raise the voltage at node A higher than the voltage at node B, and is set by the resistive divider R4 and R1 and the impedance network composed of R1, R, and R. When the one shot has been triggered, the output of CMPTR is high, causing the reference voltage at the non-inverting input of CMPTR1 to go to. This prevents any additional input pulses from disturbing the circuit until the output pulse has timed out. The value of the timing capacitor C1 must be small enough to allow CMPTR1 to discharge C1 to a diode voltage before the feedback signal from CMPTR (through R1) switches CMPTR1 to its high state and allows C1 to start an exponential charge through R5. Proper circuit action depends upon rapidly discharging C1 through the voltage set by R6, R9, and D to a final voltage of a small diode drop. Two propagation delays after the voltage on C1 drops below the level on the non-inverting input of CMPTR, the output of CMPTR1 switches to the positive rail and begins to charge C1 through R5. The time delay which sets the output pulse width results from C1 charging to the reference voltage set by R6, R9, and D, plus four comparator propagation delays. When the voltage across C1 charges beyond the reference, the output pulse returns to ground and the input is again ready to accept a trigger signal. Oscillators and Pulse Width Modulators Microchip s linear building block comparators adapt well to oscillator applications for low frequencies (less than 1 KHz). Figure 7 shows a symmetrical square wave generator using a minimum number of components. The output is set by the RC time constant of R4 and C1, and the total hysteresis of the loop is set by R1, R, and R. The maximum frequency of the oscillator is limited only by the large signal propagation delay of the comparator in addition to any capacitive loading at the output which degrades the slew rate. To analyze this circuit, assume that the output is initially high. For this to occur, the voltage at the inverting input must be less than the voltage at the non-inverting input. Therefore, capacitor C1 is discharged. The voltage at the noninverting input (V H ) is: V H = R( ) [R (R1 R)] Equation 5. where, if R1 = R = R, then: V H = () Equation 6. Capacitor C1 will charge up through R4. When the voltage at the comparator s inverting input is equal to V H, the comparator output will switch. With the output at ground potential, the value at the non-inverting input terminal (V L ) is reduced by the hysteresis network to a value given by: V L = Equation 7. Using the same resistors as before, capacitor C1 must now discharge through R4 toward ground. The output will return to a high state when the voltage across the capacitor has discharged to a value equal to V L. The period of oscillation will be twice the time it takes for the RC circuit to charge up to one half its final value. The period can be calculated from: 1 FREQ = (.694) (R4) (C1) Equation 8. The frequency stability of this circuit should only be a function of the external component tolerances. Figure 8 shows the circuit for a pulse width modulator circuit. It is essentially the same as in Figure 7 with the addition of an input control voltage. When the input control voltage is equal to one-half, operation is basically the same as described for the free-running oscillator. If the input control voltage is moved above or below one-half, the duty cycle of the output square wave will be altered. This is because the addition of the control voltage at the input has now altered the trip points. The equations for these trip points are shown in Figure 8 (see V H and V L ). Pulse width sensitivity to the input voltage variations can be increased by reducing the value of R6 from 1 KΩ and conversely, sensitivity will be reduced by increasing the value of R6. The values of R1 and C1 can be varied to produce the desired center frequency. Voice Band Receive Filter The majority of spectral energy for human voices is found to be in a.7 KHz frequency band from Hz to KHz. To properly recover a voice signal in applications such - 1/1/ 6

7 Linear Building Block Low-power as radios, cellular phones, and voice pagers a low-power bandpass filter that is matched to the human voice spectrum can be implemented using Microchip s CMOS op amps. Figure 9 shows a unity gain multi-pole Butterworth filter with ripple less than.15 db in the human voice band. The lower db cut-off frequency is 7 Hz (single order response) while the upper cut-off frequency is.5 KHz (fourth order response). Figure 1 shows a high Q () second order SAT detection bandpass filter using Microchip s CMOS op amp architecture. This circuit nulls all frequencies except the three SAT tones of interest. Supervisory Audio Tone (SAT) Filter for Cellular Supervisory Audio Tones (SAT) provide a reliable transmission path between cellular subscriber units and base stations. The SAT tone functions much like the current/ voltage used in land line telephone systems to indicate that a phone is off the hook. The SAT tone may be one of three frequencies: 597, 6, or 6 Hz. A loss of SAT implies that channel conditions are impaired and if SAT is interrupted for more than 5 seconds a cellular call is terminated. TO SYSTEM DC/DC CONVERTER R4, 47k, 1% VDD R5, 7.5M AMP1 R, k, 1% CMPTR1 VDD BATTLOW V ALKALINE R1, 7k, 1% V R CMPTR BATTFAIL R6, 7.5M R, 47k, 1% Figure. Precision Battery Monitor 7-1/1/

8 Linear Building Block Low-power V IN SHDN AMP1 N V OUT1 AMP N V OUT V R RA 1 C1, 1µF RA C, 1µF RB 1 RB V OUT = V R x (R A R B )/R B Figure. Dual Low Dropout Regulator V SRC R A R B R C V OUT R A 15K R B 15K.768 KHz VDD R C V OUT V R C A 1 pf 1M Tper =.5 µsec Figure 4. External Hysteresis Configuration Figure KHz Time of Day Clock Oscillator IN t IN R1 R 1M 1K R 1K GND A R4 1M B CMPTR1 R1 61.9K R5 1M D1 R6 56K C C1 1 pf R9 4K TC15 CMPTR R8 1M R7 1M OUT OUT C GND GND D Figure 6. Non-Retriggerable Multivibrator - 1/1/ 8

9 Linear Building Block Low-power C1 R1 1K R 1K R 1K R4 V H = R ( ) R (R1 R) V L = ( ) (R R) R1 (R R) FREQ = 1 (.694)(R4)(C1) V C C1 R6 1K R1 1K R 1K R4 R 1K V H = (R R R 6 ) V V C (R 1 R R ) L = R 1 R R 6 R 1 R R 6 R R R 6 R 1 R R 1 FREQ = (.694) (R4) (C1) For Square Wave Generation, Select R1 = R = R V C = (R 1 R R 6 R R R 6 ) V C (R 1 R R ) R 1 R R 6 R 1 R R 6 R R R 6 R 1 R R Figure 7. Square Wave Generator Figure 8. Pulse Width Modulator Gain = db Fch =.5 KHz 4 db/octave Fcl = 7 Hz 6 db/octave Passband Ripple <.15 db V IN.1 µf 68 pf 1.K 1.K 1.K.6K /.6K 75 pf V OUT Gain = db Q = Q = FC BW ( db) FC = 6 KHz VIN 4.K µf.6 µf 48.7K V OUT 4 pf 47 pf / / Op Amp Two () Op Amps Figure 9. Multi-Pole Butterworth Voice Band Receive Filter Figure 1. Second Order SAT Bandpass Filter 9-1/1/

10 Linear Building Block Low-power DEMO CARD The Demo Card is a 1.5 x 1. card containing a and all of the necessary external components required to develop a Dual Adjustable Low Dropout Voltage Regulator with Power Good Flags and Master Shutdown Mode. This application utilizes all five internal cells (i.e. both op-amps, both comparators and the reference) of the which allows the user to evaluate the device performance in a system level application. The demo card is fully assembled with the required external resistors, capacitors, transistors, and potentiometers that allow the user to adjust the two regulated output voltages (V OUT1, V OUT ) and the two Power Good Flag (V OUT1_GOOD, V OUT_GOOD ) threshold levels. For convenience, several test points and jumpers are available for measuring various voltages and currents on the circuit board. Figure 11 is a schematic of the Demo Card, and Figure 1 shows the assembly drawing and artwork for the board. Table 1 lists the voltages that are monitored by the test points and Table lists the currents that can be measured as well as the various operating modes of the demo card using the jumpers on the board. NOTE: Never operate the Demo Card with both J and J connected simultaneously! Table lists the adjustments the user can make with the four potentiometers (VR1 through VR4). Figure 11. Demo Card Schematic - 1/1/ 1

11 Linear Building Block Low-power Figure 1. Demo Card Assembly Drawing and Artwork Table 1. Demo Card Test Points Test Font TP1 TP TP TP4 TP5 TP6 TP7 TP8 Voltage Measurement Demo Card Power Supply Input [4.5V to 5.5V] Ground Ground /SHDN Input (Active Low) Adjustable LDO Regulator Output Voltage #1 (V OUT1 ) Adjustable LDO Regulator Output Voltage # (V OUT ) Power Good Flag for LDO Regulator #1 (V OUT1_GOOD ) Power Good Flag for LDO Regulator # (V OUT_GOOD ) Table. Demo Card Adjustments Potentiometer Adjustments VR1 LDO Regulator Voltage #1 (V OUT1 ) VR LDO Regulator Voltage # (V OUT ) VR Power Good Flag Threshold for LDO Regulator #1 (V OUT1_GOOD ) VR4 Power Good Flag Thresh old for LDO Regulator # (V OUT_GOOD ) Table. Demo Card Test Points Current Measurement / Jumper Jumper Function J1 Demo Card Supply Current J Demo Cad Shutdown (See Notes 1,) J Demo Card Enable (See Notes 1, ) NOTES: 1. Never connect both J and J Jumpers simultaneously.. If jumpers J and J are OPEN, the Demo Card will default to the ENABLE mode. 11-1/1/

12 Linear Building Block Low-power TYPICAL CHARACTERISTICS DELAY TO RISING EDGE (µsec) DELAY TO FALLING EDGE (µsec) Propagation Delay vs. Supply Voltage TA = 5 C CL = 1pF Overdrive = 1mV Overdrive 5mV SUPPLY VOLTAGE (V) Propagation Delay vs. Temperature 7 Overdrive = 1mV = 5V = 4V = V = V TEMPERATURE ( C) VDD VOUT (V) DELAY TO FALLING EDGE (µsec) Propagation Delay vs. Supply Voltage SUPPLY VOLTAGE (V) Output Swing vs. Output Source Current.5 T A = 5 C Output Short-Circuit Current vs. Supply Voltage TA = 4 C 5 TA = 5 C 1. OUTPUT SHORT -CIRCUIT CURRENT (ma) 4 TA = 85 C TA = 4 C Sinking TA = 5 C 1 Sourcing TA = 85 C SUPPLY VOLTAGE (V) REFERENCE VOLTAGE (V).5 TA = 5 C CL = 1pF = 1.8V Overdrive = 1mV Overdrive = 5mV Overdrive 1mV I SOURCE (ma) = V = 5.5V Reference Voltage vs. Load Current = 1.8V = 1.8V = V Sinking Sourcing = 5.5V = 5V = V LOAD CURRENT (ma) V OUT V SS (V) DELAY TO RISING EDGE (µsec) Propagation Delay vs. Temperature Overdrive = 1mV VDD = 5V VDD = 4V VDD = V = V 4 5 TEMPERATURE ( C) 85.5 Output Swing vs. Output Sink Current T A = 5 C = 1.8V SUPPLY AND REFERENCE VOLTAGES (V) 4 1 I SINK (ma) = V = 5.5V Line Transient Response of V REF V REF 1 4 TIME (µsec) - 1/1/ 1

13 Linear Building Block Low-power TYPICAL CHARACTERISTICS DC Open-Loop Gain (db) Op Amp DC Open-Loop Gain vs. Temperature Supply Voltage (V) DC Open-Loop Gain (V/mV) Op Amp DC Open-Loop Gain vs. Temperature C 5 C 85 C Temperature ( C) Output Current (ma) Op Amp Short-Circuit Current vs. Supply Voltage I SINK Supply Voltage (V) Output Current (ma) Op Amp Short-Circuit Current vs. Supply Voltage I SRC Supply Voltage (V) R LAOD (KΩ) Op Amp Load Resistance vs. Load Capacitance 1% Overshoot = V, V CM = 1.5V Region of Marginal Stability Region of Stable Operation Capacitive Load (pf) Output Voltage (mv) Input Voltage (mv) Op-Amp Small-Signal Transient Response TIME µsec Output Voltage (V) Input Voltage (V) Op-Amp Large-Signal Transient Response PSRR (db) Op Amp Power Supply Rejection Ratio (PSRR) vs. Frequency = V, V CM = 1.5V, V IN = 1mVpp TIME µsec 7 1 1K 1K Frequency (Hz) 1K 1-1/1/

14 Linear Building Block Low-power TYPICAL CHARACTERISTICS Reference Voltage vs. Supply Voltage 1.5 Supply Current vs. Supply Voltage SHDN = REFERENCE VOLTAGE (V) SUPPLY CURRENT (µa) T A = 5 C T A = 85 C T A = 4 C SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) PACKAGE DIMENSIONS 16-Pin QSOP PIN (.99).15 (.81).44 (6.).8 (5.8).196 (4.98).189 (4.8).1 (.5).4 (.1).5 (.65) TYP..1 (.1).8 (.1).69 (1.75) 8.5 (1.5) MAX..1 (.5).7 (.19).5 (1.7).16 (.41) Dimensions: inches (mm) - 1/1/ 14

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