An Integrated 900 MHz Spread-Spectrum Wireless Receiver in 1-µm CMOS and a Suspended Inductor Technique

Transcription

1 An Integrated 900 MHz Spread-Spectrum Wireless Receiver in 1-µm CMOS and a Suspended Inductor Technique FINAL REPOR EPORT James Chang Integrated Circuits & Systems Laboratory Electrical Engineering Department University of California Los Angeles, CA March 1998 Supported by DARPA, Rockwell International, Harris Semiconductor, Texas Instruments, AMD, and the State of California MICRO Program.

2 Table of Contents Chapter 1 System Architecture and Fundamentals Introduction Transceiver Architecture Direct-Conversion Receiver Receiver Fundamentals Sensitivity, MDS, and NF Linearity Dynamic Range CMOS Fundamentals Large-Signal Performance of MOS and Bipolar Devices Noise Sources in MOS and Bipolar Devices Chapter 2 Suspended Spiral Inductors Inductor Requirements Inductance Calculation Substrate Comparison Silicon Etching iv

3 2.4.1 EDP and TMAH Xenon Difluoride (XeF 2 ) XeF 2 Etching Chamber and Procedure XeF 2 Etching Procedure Suspended Inductor Performance Chapter 3 CMOS RF Front-End Circuits Front-End Circuit Requirements LNA Design LNA Development History Matched Common-Source LNA Common Gate Amplifier Downconversion Mixer Front-End Prototype Evaluation Chapter 4 Baseband Circuits and Receiver Integration Channel-Select Filter Limiting Amplifier and RSSI Correlating FSK Detector Stand-alone Receiver Prototype v

4 4.5 Final Receiver on Integrated Transceiver Modifications in the Baseband Circuits Modifications in the RF Circuits Dynamic Range Planning Chapter 5 Receiver Experimental Results Prototype Assembly Device Package and Evaluation Board Test Equipment Receiver Front-End Performance Receiver Noise Figure and MDS IIP2 and IIP Receiver Performance Summary Chapter 6 Conclusions Bibliography vi

5 ABSTRACT OF THE DISSERTATION An Integrated 900 MHz Spread-Spectrum Wireless Receiver in 1-µm CMOS and a Suspended Inductor Technique by James Yung-Chieh Chang Doctor of Philosophy in Electrical Engineering University of California, Los Angeles, 1998 Professor Asad A. Abidi, Chair Portable wireless personal communication systems such as cellular phones, message pagers, and wireless modems traditionally have been built from a mixture of IC technologies: GaAs or silicon bipolar for the RF front-end, CMOS for the baseband DSP circuits. This approach increases system complexity, cost, and power consumption. In addition, the typical transceiver architecture mandates the use of off-chip bandpass filters which increase system size. xxv

6 This dissertation describes the first single-chip 900 MHz frequency-hopped spread-spectrum wireless receiver in 1-µm CMOS. This receiver is part of a singlechip transceiver which operates in the MHz ISM band. A frequencyhopped carrier with FSK modulation transmits digital data at 160 kb/s. The receiver combines a balanced low-noise amplifier, quadrature downconversion mixers, lowpass channel-select filters, and limiting amplifiers all in one single CMOS IC. Using direct conversion architecture, CMOS RF circuits, and on-chip filtering, the receiver is fully self-contained and eliminates off-chip SAW filters often seen in superheterodyne receivers. The patented suspended inductors used in both the receiver and transmitter enable low-power RF circuits to be integrated with baseband circuits in CMOS technology. Device properties unique to CMOS are exploited to obtain highly linear RF circuits. This receiver achieves 62 db of SFDR with -104 dbm MDS at 10-3 BER, and -8.3 dbm IIP3. It drains 40 ma from 3.3 V, 120 ma if on-chip frequency synthesizer is included. The technical methods and knowledge accumulated in this project pave the way for imminent low-cost, low-power, single-chip wireless digital communication systems. xxvi

7 Chapter 1 System Architecture and Fundamentals 1.1 Introduction Portable wireless personal communication devices such as cellular phones, message pagers, and wireless modems, are fast becoming a part of our daily lives. The advances in integrated circuit (IC) technology, digital communication methods and digital signal processing (DSP) are making them easier to use and packed with user friendly features. These devices must provide high data rate to allow multimedia compatibility in the future, and low power consumption for longer lasting battery life. The cost and size of such devices are also critical for their success in the consumer market. 1

8 Analog RF Transceiver Digital waveform Control Digital Baseband DSP Typically: GaAs or Si Bipolar CMOS Figure 1.1 Two-way wireless digital communication system. Conceptually, a two-way wireless digital communication system is divided into two major sections, the transceiver analog front-end and the baseband digital back-end as shown in Figure 1.1. In transmit mode, the transceiver front-end modulates a radio frequency (RF) carrier signal according to the baseband digital data which represent either speech or data. In receive mode, the process is reversed. The baseband digital back-end contains synchronization, power control, coding, and error correction circuitries as well as the user interface, which turns the system into a cellular telephone, cordless telephone, or computer modem. In the case of one-way broadcast communication such as message paging or global positioning system (GPS), the transceiver is reduced to a receiver. Fueled by developments in high density DRAM research, the digital backend is being improved rapidly by advances in complimentary metal-oxide semiconductor (CMOS) IC technology, which now offers higher integration level and processing speed. However, the analog front-end which has to operate at RF are traditionally built from more expensive technologies like GaAs or silicon bipolar 2

9 which are optimized to provide signal amplification at radio frequencies. This mixture of device technologies prevents the single-chip integration of a wireless system. Present transceiver architecture also requires several external discrete filters which increase system size and complexity. Over the years, radio communication across any significant distance was strictly regulated by issue of a license to transmit on precisely defined frequencies, with prescribed upper limits on the bandwidth of the transmitted signal and on its power level. More recently, the FCC has opened up three frequency bands for unlicensed use in Industrial, Scientific, and Medical (ISM) applications. Instead of assigning fixed frequencies to certain users by license, these bands grant multiple access by requiring users only to spread the transmitted spectrum according to some pseuodonoise (PN) code [1]. Users of one band do not interfere with one another if the correlation between their codes is small. The FCC rules (47 CFR ) allow spreading by direct-sequence modulation or frequency hopping of the carrier, as long as the user spreads the signal by a prescribed minimum. The maximum transmitted power is limited to 1W, and the out-of-ism band emission must be 50 db lower than the in-band transmitted power. There is free choice of modulation scheme. The ISM band gives great flexibility for the design of wireless equipment. From the researcher's perspective, it is now possible to explore the multidimensional design space comprising modulation scheme, spreading method, transceiver architecture, and circuit building blocks, for the most compact 3

10 transceiver, or one that consumes the least power for a given performance. This is the approach underlying the receiver design described in this dissertation, part of a single-chip transceiver intended to operate in a microcellbased environment at a data rate of up to 160 kb/s, and implemented entirely in the MOSIS 1-µm CMOS technology, HPCMOS34, available at the inception of this project. The prototype is to use as few or no external components as possible to reduce overall system complexity and size. Single-chip solution has the additional advantage of keeping RF signals on-chip, thus power consumption is reduced by eliminating RF buffers which drive off-chip 50 Ω transmission lines or filters. The knowledge accumulated in this project allows the development of a complete wireless digital communication system on a single chip in the near future. It is assumed from here on that the reader is already well-versed in existing RF transceiver architectures and circuitries. An excellent reference [2] which surveys the current RF IC designs is helpful to those who are new to this field. 1.2 Transceiver Architecture The transceiver shown in Figure 1.2 implements a customized frequencyhopped spread-spectrum (FH-SS) radio system [3][4]. All spread-spectrum provides an inherent immunity to multipath fading, but with frequency hopping the signal processing takes place at the hopping rate, which may be much lower than 4

11 Baseband 915 MHz Local Osc RF Baseband Data In Baseband Data Out Frequency Control Logic Freq. & Timing Acquisition FSK Detector DDFS DDFS 10b 10b I Q Limiter Limiter I Q f LO /64 RC Polyphase Filter LPF LPF f LO /16 Q I I Q Combine PA Power Control LNA Receiver Balun Balun DRF RSSI Digital Analog Figure 1.2 Transceiver architecture. the chip-rate in direct-sequence (DS) SS [1] to spread the spectrum over some wide bandwidth. Thus, if a compact agile frequency synthesizer is available, a frequencyhopped transceiver potentially offers the lower power implementation. Further details on system design rationale and definitions of FH vs. DS are found in [5]. With FH-SS, there is also wider choice of modulation. The modest data rate in this system is conveyed by frequency-shift keying (FSK) the carrier. Among the various types of multi-level FSK, quaternary FSK (4-FSK) makes most efficient use of bandwidth at low error probability [6][7]. It maps a pair of binary data bits to one of four equally-spaced offsets of the carrier frequency (f c ), that is f c ± f and f c ± 3 f, or even, as here, f c ± 2 f. 4-FSK symbols are at half the basic data rate. A noncoherent receiver detects data by sensing the outputs of four bandpass filters 5

12 centered at the offset frequencies. This is much simpler than a receiver for directsequence SS communication systems, whose operation at least requires phase recovery, and whose front-end clocks at some high chip rate. On the other hand, a direct-conversion, or zero-if, architecture is well-suited to receive FSK [8], and is well-recognized as the best candidate for monolithic integration. This system divides the ISM band into 54 channels each with 480 khz of bandwidth. The carrier frequency hops at 20 khops/s among these 54 channels according to a pseudo-random sequence. The digital data is carried by symbol tones at an offset of either ±80 khz or ±160 khz from the carrier frequency. This is illustrated in Figure 1.3. Since there are four possible symbols at each carrier frequency, each symbol represents 2 bits of digital data. This system can achieve a maximum data rate of 160 kb/s by sending four symbols per hop. The transceiver operates as follows. A baseband direct-digital frequency synthesizer (DDFS) is used as an agile frequency synthesizer and data modulator [9][10]. The DDFS creates digital samples of a baseband sinusoidal waveform by addressing a sine ROM at a frequency set by a 24-bit control word. Two 10-bit D/A converters (DAC s) map the 10-bit words at the DDFS outputs into discrete analog samples. The quadrature outputs synthesize a complex (in the sense of magnitude and phase) FH-SS at baseband. A fixed-frequency oscillator upconverts these outputs to the ISM band in a single-sideband mixer. With an oscillator at 915 MHz in the center of the ISM band, either the upper or the lower sideband is selected to 6

13 Noise-Like Spectrum Carrier Hop Pseudo- Random Sequence 902 Frequency, MHz 928 Channel 1 Channel 54 f c -13MHz 0 480KHz +13MHz guard band 80kHz 80kHz guard band 480kHz Figure 1.3 Frequency-hopped spread-spectrum system (FHSS). place the instantaneous carrier frequency anywhere in the band. The DDFS/DAC output frequency need only span 0 to 13 MHz to cover the ISM range of 915 ± 13 MHz. After upconversion, a power amplifier (PA) drives the antenna with the modulated hopped carrier. The maximum PA output is 20 mw into 50 Ω (+13 dbm), sufficient for operation in microcells with 100 m diameter or for communication over 1 km over an unobstructed line-of-sight link. A key feature is 7

14 that a 5-bit digital word controls the output power over a 30 db range, to a minimum value of 20 µw. Accurate power control by the base-station over this dynamic range is essential to achieve the potential user capacity of a FH-CDMA system [11]. An off-chip passive dielectric resonator filter (DRF) between the PA and antenna suppresses out-of-band signals at the transmitter output. These out-of-band signals are images around the clock frequency of the discrete-time waveforms in the transmitter. Internally, the dielectric filter comprises three coupled resonators tailored to a passband spanning MHz, with a transition band 50 MHz wide on either side, and an eventual stopband loss of 40 db ([12] shows this filter's response). Its insertion loss in the passband is about 1.5 db. In a Code Division Multiple Access (CDMA) wireless system, users transmit and receive in the same frequency band, distinguishing themselves by a unique spreading code. The receiver is tuned to the MHz band and the same dielectric filter, used reciprocally, acts as the RF preselect filter. The received FH-FSK is concurrently de-spread and downconverted in quadrature to zero-if in the receiver front-end. The DDFS-based agile frequency synthesizer, after upconversion but without modulation, is used as the local oscillator (LO) in the downconversion mixers (Figure 1.2 and Figure 1.4). A baseband circuit [13] synchronizes the LO to the spreading code, that is, the hopping pattern, of the user of interest, always downconverting that user's carrier frequency to DC, but also downconverting all other users of the ISM band to frequencies positioned away 8

15 Hopping I-LO from transmitter 902~928 MHz Dielectric Resonator Filter LNA 230 khz LPF Limiter RSSI Hopping Q-LO FSK Detector Figure 1.4 Direct-conversion receiver for this system. from DC. The receiver discriminates positive FSK offsets (+ f and +2 f) from negative offsets (- f and -2 f) in quadrature downconversion paths. I/Q (Inphase/Quadrature-phase) phasing scheme keeps the negative-frequency halfchannel from folding over and superpose on to the positive-frequency half-channel [8]. A lowpass channel-select filter in each path passes only the selected user's received signal and suppresses adjacent channels. This is implemented as a switched-capacitor filter which is discussed later in Chapter 4. The specifications of the required channel-select filter are illustrated in Figure 1.5. The filter passband encompasses the spectrum of four FSK tones at ±80 khz and ±160 khz, modulated in continuous-phase by pseudorandom data. The filter must suppress all the other signals populating the downconverted ISM band, particularly the adjacent user whose carrier frequency is 480 khz above and below the desired user. The sidelobes of each quaternary tone at a baud rate of 80 khz occupy a 6-dB signal bandwidth of ±40 khz around the tone frequency, which means that the spectrum of the tones at 160 khz extends to ±200 khz. The filter passband is 230 khz wide. 9

16 0 db f pass = 230kHz 0 to -1dB 280kHz -24dB 320kHz dB f (khz) User 1 User 2 As in any FM receiver, instead of a complicated linear AGC, a simple limiting amplifier boosts the received signal to binary levels whose zero crossings contain the modulation. The limiter also produces a logarithmic signal-strength measurement, Received Signal Strength Indicator (RSSI), to an accuracy of 1 db over a 80 db dynamic range, which allows a slow 7-bit A/D converter digitizes for uplink to the base-station. A digital detector correlates the limited signals in the quadrature channels with the four expected frequency offsets, and a decision based on the strongest correlation over each symbol is mapped to a pair of data bits [13][14]. The correlation detector also creates early-late data words for a digital PLL to align the LO hopping pattern and the symbol timing clock in the detector [15]. Figure 1.5 Channel-select filter specification. Frequency spectrum of 4- FSK pseudorandom modulation shown in passband. The transmitter and receiver operate in time-division duplex. The PA output 10

17 may be connected to the low-noise amplifier (LNA) input, and one matching network, in principle, may transform the impedance this common node to the antenna impedance. However, we did not find a unique network to match the shorted-together PA and LNA ports to 50 Ω in both transmit and receive modes. A circulator or a low-loss RF switch should be used to combine the two ports. 1.3 Direct-Conversion Receiver In a superheterodyne receiver architecture commonly found in TV receiver or analog cellular telephones, the input signal is first amplified at RF in a tuned stage, then converted by an offset-frequency local oscillator to a lower intermediate frequency (IF) anywhere from 10 to 100 MHz, where it is substantially amplified and filtered by highly-selective passive bandpass filters [8]. Figure 1.6 shows a typical superheterodyne receiver. Although this approach is generally thought to provide high selectivity and sensitivity, it requires several off-chip passive filters which make single-chip implementation difficult. An image-reject filter between On-Chip LNA Image Rejection Filter Channel Select Filter Channel Select Filter Demod F1 F2 Figure 1.6 Typical superheterodyne receiver. 11

18 the LNA and the mixer to filter the image channel, and bandpass filters for channel selection between the IF stages using LC-tuned circuits or SAW filters are commonly found in these receivers. Amplifying signals at IF also increases power consumption because transistors must be biased at large currents to drive the parasitics and the low characteristic impedance of the passive IF filters. Though suitable for tabletop receivers, superheterodyne architecture has many limitations for single-chip, low-power receiver designs. Direct-conversion architecture has been well-recognized for monolithic integration, and it is often used in single-chip paging receivers [16]. It is also known as a zero-if receiver because the LO is centered at the signal carrier frequency and thus the first IF, in the context of a superheterodyne receiver, is zero. It eliminates the off-chip passive IF filters in a superheterodyne receiver, and it is potentially less power consuming. Only a lowpass filter, which is in effect a bandpass filter centered at DC when the negative frequency axis is included, is used to select the desired channel and to reject all adjacent channels. RF preselection may in principle be removed because there is no image channel. In practice, it is still required to suppress strong out-of-band signals that may create large intermodulation distortion in the front-end prior to baseband channel selection and to avoid harmonic downconversion. If a high-order active filter is used for channel selection, it will dissipate lower power and occupy a smaller chip area at a given dynamic range than an active bandpass filter with the same selectivity centered at a high IF [17]. All 12

19 amplification past the front-end is also at baseband, and therefore consumes a small power. Despite its simplicity and potential for single-chip implementation, directconversion architecture has some well-known problems which prevented its widespread use in cellular phones. Among the problems, spurious LO leakage is probably best known. Since the LO is tuned exactly to the center of the LNA and antenna passbands, a small fraction of the LO energy may leak into the antenna through the mixer and LNA because of their finite reverse isolation. The LO energy can also be coupled to the antenna through external leads [18]. This becomes an inband interferer to other nearby receivers tuned to the same band, for the leakage may even be stronger than the desired signal. The problem is less severe in a superheterodyne whose LO frequency is usually outside the antenna passband. However, experimental studies [19] suggest that standard shielding in the receiver may control LO leakage to the point that it does not seriously handicap the use of direct-conversion. Distortion produced by strong signals in the downconversion mixer will cause the sensitivity of a direct-conversion receiver to degrade more rapidly than the superheterodyne. Second-order distortion in a single-ended mixer will rectify the envelope of an amplitude-modulated RF input such as QPSK data to produce spurious baseband spectral energy centered at DC, which adds to the desired downconverted signal [18][20]. This is particularly serious if the envelope is that of 13

20 Interferer Self-mixing LNA Dynamic DC Offset LO Self-mixing LO Figure 1.7 Sources of dynamic offsets in direct-conversion receivers. a large unwanted signal lying in the preselect filter passband, which has not yet been rejected by the baseband channel-select filter. The most effective solution is to use balanced or differential circuits in the RF front-end, particularly in the mixer. Chapter 3 covers the highly linear RF front-end circuits implemented for this receiver in more detail. The DC offset in the baseband section following the mixer is perhaps the most serious problem. Offsets mainly come from three sources: transistor mismatch in the signal path between the mixer I and Q inputs to the detector; LO leaking from the antenna and reflecting off an external object and self-downconvert to DC in the mixer; or a large undesired near-channel interferer leaking into the LO port of the mixer and self-downconvert to DC (Figure 1.7). The last two types of offsets have varying amplitudes with receiver location, orientation, and the instantaneous LO frequency in a frequency-hopping receiver. These offsets appears in the middle of the downconverted signal spectrum, and may be larger than the signal itself, and much larger than thermal and flicker noise. Unless the offset is removed, the Signal 14

21 to Noise Ratio (SNR) at the detector input will be very low. Chapter 4 shows our solution used to remove static offsets: a global feedback loop around the limiting amplifier which effectively removes offsets up to 1 V. In addition to solving previously mentioned problems, we have also for the first time created highly linear CMOS RF circuits and passive components in order to achieve a single-chip transceiver. Chapter 2 covers a critical passive component, suspended spiral inductor, used in the RF portions of the transceiver: LNA, voltage controlled oscillator (VCO), power amplifier (PA), and local oscillator (LO) buffers. This patented technology [21] allows large inductors to be built in standard CMOS process enabling on-chip LC tuned circuits. In addition to baseband circuits, Chapter 4 also covers the system dynamic range planning. Finally, Chapter 5 presents the experimental results of the receiver portion of the transceiver prototype. 1.4 Receiver Fundamentals Some commonly used figures of merit for receiver design are defined in this section: sensitivity, noise figure, linearity, IIP3, 1-dB compression and dynamic range. Frequently used design equations are also summarized in this section Sensitivity, MDS, and NF The sensitivity of a receiver is a measure of its ability to amplify and 15

22 demodulate weak signals. Sensitivity is often expressed in terms of the minimum detectable signal (MDS) level at the antenna which produces some acceptable level of signal-to-noise ratio (SNR) at the demodulator output. MDS is calculated by: MDS = 174 dbm/hz + NF + 10logBW + SNR min, (1.1) where -174 dbm/hz is the thermal noise at 290 K, NF is the cascaded noise figure of receiver in db before the demodulator, BW is the effective noise bandwidth used in SNR calculation of the demodulator, and SNR min is the minimum signal-to-noise ratio required by the demodulator to maintain a certain level of fidelity, typically represented by Bit-Error-Rate (BER). Since the input impedance of most RF and microwave systems is 50 Ω, MDS is measured in dbm referred to 50 Ω. dbm is a power unit defined as: Power (Watts) dbm = 10log mW. (1.2) For example, -100 dbm of MDS represents dissipating 0.1 pw of power into 50 Ω, which is 2.23 µv rms. Signal level can also be expressed in terms of voltage, dbv is the number of decibels above 1 V rms, V rms dbv = 20log (1.3) 1V rms Thus the relationship between dbm and dbv in a 50 Ω system is, 16

23 V2 RMS 1000 mw dbm = 10log W. (1.4) = dbv + 13 Noise Figure The IEEE definition of noise factor is the ratio of available output noise power to available output noise due to the source. When noise factor (F) is expressed in decibels, it is called noise figure (NF). Noise factor is typically defined in 1 Hz noise bandwidth and it is called spot noise factor. In this dissertation, all NF is quoted as spot NF. NF can also be expressed as the amount of SNR degradation through a circuit block due to the added noise from the circuit block. That is, NF S i N = i = S o N o SNR in, (1.5) SNR out where S and N represent signal and noise powers and the subscripts i and o represent the input and output of the block. For radio receivers, these locations are typically defined as the antenna port and the demodulator input respectively. We can see that these two definitions are equivalent since F = S ---- i ( N i G + N ao, ) G N i S i = N ao, N i G (1.6) N ai, N i = where G is the power gain of the circuit block, N a,o is the output noise, N a,i is the 17

24 v n,s 4KTR s 2 Amplifier Input-Referred Noise 2 v n R in Noiseless 2 i n R s (= 50 Ω) Figure 1.8 Noise figure calculation for an amplifier. input-referred noise power, and N i is the source noise power. Thus, for an amplifier with input-referred noise voltage v n, and current i n as shown in Figure 1.8, NF is represented as: ( v NF 10 1 n + i n R s ) 2 = log (1.7) 4KTR S For CMOS amplifiers at low frequencies where i2 n 0, NF is simplified to: v2 NF = 10log n. (1.8) 4KTR S Note that the noise figure is not dependent on the input impedance, i.e. matching, of the amplifier when v n and i n of the amplifier have been determined, and it is only dependent on R S. NF is minimum when R 2 S, opt = v n, (1.9) i2 n 18

25 assuming negligible correlation between v2 n and i2 n [22]. However, v2 n and i2 n are often interrelated to the amplifier input impedance in LNA design, and they can vary as LNA bias is varied, thus there is an indirect relationship between NF and input matching. Cascaded NF Calculation of the cascaded noise figure must take into account the different impedance levels in a receiver. In general, the cascaded noise factor is derived as (Figure 1.9), R 2 4kTR F s + ( V n1 + i n1 R s ) 2 ( V n2 + i n2 R o1 ) in2 R tot o1 + R in2 = kTR 2 s A 1 ( 4kTRs ) R in1 + R s R in1 (1.10) Circuit building blocks on-chip operate at a high input impedance relative to 50 Ω, while the receiver input impedance is 50 Ω and the cascade noise figure is always referred to the noise in a 50 Ω source resistance. If 2 0, R o,i << R in,i+1, i ni, A 1 v ns R s 50 Ω v n1 noiseless v n2 v n3 i n2 A 2 i n1 i n3 R L A 3 R in1 Figure 1.9 R o1 R in2 R o2 R in3 NF of cascaded circuit blocks. 19

26 and R in1 is matched to R S, the equivalent input noise voltage, v n,i, of block i following the first block, the LNA, contributes v n,i /(0.5 x A 1 x... x A i-1 ) to the noise figure calculation, where A i is the loaded voltage gain of block i measured between its input and output ports. The NF is then ṽ2 n1 ṽ2 n ( 0.5 A Cascaded NF ) 2 + = log KT50. (1.11) When R S R in1, the noise contribution from the blocks following the first block would change according to the ratio R in1 R s R in From equation (3.3), this ratio is + equal to R in1 R s + R in1 = S , where S 11 is the complex reflection coefficient Linearity As the receiver is detecting a weak radio signal, there may exist strong signals emitted by another user nearby. The strong signal can drive the receiver into its nonlinear region and generate new frequencies which may swamp out the desired weak signal. Thus, the linearity of a receiver determines the maximum allowable signal level to its input. All real-life linear systems exhibit some degree of nonlinearity (Figure 1.10). Assume that the output-to-input characteristic of a system can be modeled by 20

27 v i Practical Linear Amplifier v o v o = a 0 + a 1 v i + a 2 v2 i + a 3 v3 i + Figure 1.10 Linear system modeled by a Taylor s series. a Taylor s series expansion about v i = 0 (i.e., a Maclaurin series): where v o = a 0 + a 1 v i + a 2 v2 i + a 3 v3 i + = a n vn i, (1.12) n = 0 n 1 dv a n = n! dvn i v i = 0. (1.13) The coefficients a n are assumed to be frequency independent. The output DC offset level is represented by a 0, a 1 v i is the first-order (linear) term, i.e. the gain, a 2 v2 i is the second-order (square-law) term, and so on. Coefficient a 1 will be larger than a 2, a 3,... if the system is linear. In differential circuits or balanced circuits whose transfer characteristic has only odd symmetry, the coefficients of all even powers of v i are zero. For analytical simplicity, terms higher than the third power are often neglected in hand calculations. Many linearity related problems can be analyzed by substituting v i = A 1 cosω 1 t + A 2 cosω 2 t (1.14) 21

28 into After collecting terms, at the fundamental frequencies we have: Second-order terms:. (1.15) At ω 1 : 3 a 1 --a (1.16) 2 3 A a 4 3 A2 1 A1 cosω 1 t At ω 2 : 3 a 1 --a (1.17) 2 3 A a 4 3 A2 2 A2 cosω 2 t At 2ω 1 : 1 --a (1.18) 2 2 A2 1 cos2ω 1 t At 2ω 2 : 1 --a (1.19) 2 2 A2 2 cos2ω 2 t At ω 1 ± ω 2 : ( a 2 A 1 A 2 ) [ cos ( ω 1 + ω 2 )t + cos ( ω 1 ω 2 )t] (1.20) Third-order terms: v o = a 1 v i + a 2 v2 i + a 3 v3 i At 3ω 1 : 1 --a (1.21) 4 3 A3 1 cos3ω 1 t At 3ω 2 : 1 --a (1.22) 4 3 A3 2 cos3ω 2 t At 2ω 1 ± ω 2 : 3 --a (1.23) 4 3 A 2 1 A 2 [ cos ( 2ω 1 + ω 2 )t + cos ( 2ω 1 ω 2 )t] At ω 1 ± 2ω 2 : 3 --a (1.24) 4 3 A 1 A2 2 [ cos ( ω 1 + 2ω 2 )t + cos ( ω 1 2ω 2 )t] For most linear systems, the transfer curve saturates at the extreme ends, thus the gain decreases as the input level is increased (Figure 1.11). This compressive 22

29 v o v i Output waveform Input waveform Figure 1.11 A Linear system with saturating characteristics, large inputs produce clipped outputs. transfer curve implies that the first order term and third order terms of equation (1.15) have opposite signs, that is a 1 = -a 3. From equation (1.16), we see that the third-order distortion reduces gain as input amplitude is increased. 1-dB Compression point The input level at which the small-signal gain is reduced by 1 db is called the 1-dB compression point (Figure 1.16). Setting A 2 =0 in equation (1.16), and equating the coefficient of equation (1.16) to 1 db less than the small-signal gain, a 1, 20loga db = 20log a a 4 3 A2 1dB (1.25) 23

30 0.145 a 1 = A 1dB a 3 (1.26) The 1-dB compression is typically measured in dbm, and equation (1.4) is used to convert dbv into dbm. IP3 The third-order intercept point (IP3) is found by a two-tone test. As the amplitude of two equal sinusoidal test tones at f 1 and f 2 in equation (1.14) is increased, the third-order intermodulation distortion (IMD) products will be increased at the rate of A cubed as shown in equation (1.23) and (1.24). IP3 is the point at which the amplitude of the third-order IMD would become equal to that of the fundamental. The input level at which this occurs is called the input third-order intercept point, IIP3 (Figure 1.12). The fundamental amplitude is a linear extrapolation of the small signal fundamental output curve without the effect of gain compression. Setting the coefficient of equation (1.23) equal to the small signal gain a 1 A: 3 a 1 A IIP3 = --a 4 3 A3 IIP3 (1.27) Comparing equation (1.26) with (1.28), we see that 4 A IIP3 -- a 1 = (1.28) 3 a 3 1-dB Comp. Point IIP3 10 db, (1.29) 24

31 Input Level Output Level fundamental A out A in fundamental Linear System A IM3 IM3 f 1 f 2 f 2f 1 -f 2 2f 2 -f 1 f Output Level (dbv) 20logA out Fundamental IM3 Slope=1 Slope=3 20logA IM3 20logA in IIP 3 Input Level (dbv) Figure 1.12 Finding IIP3 from a two-tone test. where IIP3 is typically measured in dbm referred to 50 Ω, it could equally well be dbv. Blocking and Desensitization When the receiver is detecting a weak signal in the presence of a strong interfering signal, the small signal gain of the receiver is reduced by the interferer. The receiver is said to be desensitized by the interferer. The interferer can desensitize the receiver to an extent that it blocks out the desired weak signal completely. To see this effect, set A 1 << A 2 in equation (1.16): 25

32 3 a a. (1.30) 2 3 A2 2 A1 cosω 1 t 3 Since a 1 =-a 3, the small signal gain is reduced by --a. When, 2 3 A2 3 2 a a 2 3 A2 2 = 0 the weak signal is said to be blocked by the interferer. A common way to quantify desensitization is by finding the interferer input level required to reduce the gain for the desired tone by 3-dB [23]: a 3 log A = 3 a 1 (1.31) A 2 = a (1.32) a 3 Comparing equation (1.32) with (1.26) and (1.28), we see that the 3-dB desensitization point is about 8.3 db less than IP3, and about 1.2 db above the 1- db compression point. Cascaded IIP3 From the above analysis, we see that once the IIP3 of a linear system is determined, many third-order related nonlinearities are quantified. When a system contains a cascade of circuit blocks, the overall input-referred third-order intercept IIP3 tot A 1 A 2 A 3... IIP3 1 IIP3 2 Figure 1.13 IIP3 3 Cascaded IIP3. 26

33 A y Asinθ 2π π x π - π x θ Figure 1.14 Estimating 1-dB compression point if the nonlinearity is only caused by clipping. point is calculated by using a well-known formula [24]: IIP3 tot (db) = 10log IIP3 1 IIP3 2 A2 1 IIP A 2 + ( 1 A2 2 ). (1.33) where IIP3 n is the amplitude of input-referred third-order intercept point of the n- th stage. A n is the loaded voltage gain of the n-th stage. Unlike cascaded NF, different impedance levels do not affect the calculation. Estimating 1-dB Compression Point Due to Clipping If the nonlinearity is only caused by clipping or saturation effect on the ends of the transfer curve, the 1-dB compression point can be estimated by straightforward calculus. The mean-square value of a sinusoid without clipping is: 1 2π ( Asinθ) 2π 2 dθ = 0 A (1.34) 2 If the sinusoid is clipped at θ = π/x as shown in Figure 1.14, the mean-square value 27

34 of the gray area is π -- 1 x ( Asinθ) 2π 2 dθ = A x π π -- x 1 2π y2 d π θ to solve for 1-dB compression point, set equation (1.35) to -- x A y -- y y x x A 2, (1.35) A , and let x = π , then asin ( y A) y 2 2 y 1 -- asin--. (1.36) π A A2 y Ay y asin π A π 0.1A = 0 2 A 2 Y is easily solved for numerically. If A=1, y=0.788 will cause a 1-dB drop in mean square value. Offset Induced IP2 The even-order nonlinearities would be cancelled out in a perfectly balanced circuit. However, in the presence of an input offset, the third-order nonlinearity of a system would induce a second-order distortion. Consider the system shown in Figure 1.15, ignoring terms higher than the third-order term, the output is which is simplified to, Y o = a 1 ( x + x 0 ) + a 2 ( x + x 0 ) 2 + a 3 ( x+ x 0 ) 3, (1.37) + a 1 x a 2 x 2 + a 3 x 3 28

35 X 1 =x+x 0 Y 1 Y o X 2 = -x Y 2 Y 1 = a 0 + a 1 X 1 + a 2 X2 1 + a 3 X3 1 + Y 2 = a 0 + a 1 X 2 + a 2 X2 2 + a 3 X3 2 + Figure 1.15 A fully differential circuit represented by 2 identical non-linear systems. An offset x 0 is applied to the input inducing second order distortion. 2 3 Y o = a 1 x 0 + a 2 x 0 +a 3 x a 1 + 2a 2 x 0 + 3a 3 x 0 x + ( 3a 3 x 0 )x 2 (1.38) When two tones of equal amplitude and different frequencies are applied to the system, + ( 2a 3 )x 3 x = Acosω 1 + Acosω 2 (1.39) the second-order term in equation (1.38) introduces a tone at the difference frequency: Y o = + 3a 3 A 2 x 0 cos ( ω 1 ω 2 ) + (1.40) Similar to IIP3, IIP2 is the input amplitude at which the second-order intermodulation distortion (IM2) level equals to that of the fundamental, 29

36 2a 1 A IIP2 A IIP2 = = 3a 3 x 0 A 2 IIP2. (1.41) 2 -- a a 3 x 0 From equation (1.28), 1 A IIP2 = A 2 IIP3. (1.42) 2x 0 If the mismatch in the a 2 or a 3 is known, similar analysis can be applied to find the IIP2. In the case of a mismatch, δ, present in a 2, i.e. 2 3 Y 1 = a 0 + a 1 X 1 + ( a 2 + δ)x 1 +a 3 X Y 2 = a 0 + a 1 X 2 + a 2 X 2 + a 3 X 2 (1.43) and, X 1 = x + x 0 = x X 2 (1.44) where, x = Acosω 1 + Acosω 2. (1.45) IIP2 is found as, 1 A IIP2 = (1.46) δ 2x a 1 A 2 IIP3 For a mismatch in a 3, 30

37 2 Y 1 = a 0 + a 1 X 1 + a 2 X Y 2 = a 0 + a 1 X 2 + a 2 X 2 + a 3 X 2 3 ( a 3 + δ)x 1, (1.47) IIP2 is, A IIP2 = A 2 IIP , (1.48) 2x ε where, Dynamic Range ε = δ (1.49) a 3 In a wireless environment, radio signal strength can vary greatly depending on the distance between the transmitter and receiver, and the medium in between. A receiver s ability to accommodate both large and small signals is indicated by its dynamic range. The higher the dynamic range is, the more tolerant the receiver is towards signals that vary greatly in magnitude. Two definitions of dynamic range are used (Figure 1.16): spurious-free dynamic range (SFDR), and blocking dynamic range (BDR). The lower bounds of both dynamic range definitions are set by the receiver noise floor, which is MDS in equation (1.1) with SNR min set to zero. Namely, P NsFlr (Noise Floor) = 174 dbm/hz + NF + 10logBW, (1.50) and the upper bounds are either related to IIP3 or the 1-dB compression point. 31

38 Output 1 db Fundamental SFDR IM3 SNR min P NsFlr MDS SFDR BDR P -1dB IIP 3 Input Figure 1.16 Graphical representation of IIP3, 1-dB compression point, BDR and SFDR. SFDR The upper bound of SFDR is defined as the two-tone in-band signal level at which third-order intermodulation distortion products rise to the noise floor level (Figure 1.17). If the third-order intercept point of the receiver is known, SFDR is found as follows: assuming that all quantities are in db or dbm, and since IM3 Noise Floor Figure 1.17 f Upper bound of SFDR. 32

39 IIP3 = P out P IM3,out + P, (1.51) 2 in and referring output level to equivalent input level by subtracting gain, P out -G = P in, (1.52) P IM3,out - G = P IM3,in = P NsFlr, (1.53) IIP3 = P in,max P NsFlr + P. (1.54) 2 in,max Maximum input level for SFDR is then P P NsFlr + 2IIP3 in,max = , (1.55) SFDR = P in,max ( P NsFlr + SNR min ) 2 = -- ( IIP3 P 3 NsFlr ) SNR min. (1.56) SFDR is a very stringent measure, and is not often specified explicitly. The SNR min is often assumed to be zero in the literature and in [25]. In order to facilitate comparison to the published receiver performance in the literature, the SNR min is assumed to be zero in following discussions. BDR The upper bound of BDR is the 1-dB compression point. BDR is a measure of resilience to a large out-of-band blocking signal which, by driving the receiver into compression, de-sensitizes it to a small desired signal [23][26]. SFDR and BDR are related as follows (Figure 1.16): 33

40 P -1dB IIP3 10 db P NsFlr SFDR BDR = 174 dbm/hz + NF + 10logBW = = 2 -- ( IIP3 P 3 NsFlr ) SNR min P NsFlr SNR min P 1dB (1.57) SFDR ( BDR SNR min ) SNR min where P -1dB is the input power (referred to 50Ω) of 1-dB compression point. SNR min is the signal to noise ratio required at the detector for the smallest acceptable bit-error rate, BW is the net receiver noise bandwidth, usually set by the detector; and NF is its input noise figure. It is important to note that the first relation usually holds for single-point nonlinearity, that is, when the dominant nonlinearity arises at one point in a strongly nonlinear circuit. CMOS circuits are weakly nonlinear, and it is quite possible that distortion in one part of the circuit sets the (extrapolated) IIP3, while clipping in another the P -1dB. 1.5 CMOS Fundamentals CMOS design equations are briefly summarized in this section along with a comparison between CMOS devices and bipolar devices for their use in RF applications. Starting with the level 1 current equation for a NFET in its saturation region (V ds V gs -V t ) and ignoring V ds effect, 34

41 I d = µ n C ox W ( L V gs V t ) 2 (1.58) and the transconductance g m is g m = I d V gs = W µ n C ox ---- ( V L gs V t ) (1.59) 2I = d = V gs V t 2I d V eff The unity current gain frequency, ω T, of a MOSFET is ω T = = g m C gs V GS µ n ( V t ) θ ( V GS V t ) L 2 (1.60) where θ captures how the inversion-layer mobility, µ n, degrades with gate electric field [27]. While equation (1.59) is readily verified by measurement, there is little data in the literature on CMOS ω T to validate equation (1.60). Therefore, the S- parameters of a single 2000/1 µm NMOSFET in the HPCMOS34 process were characterized on a Cascade probe station, from which ω T was deduced. An interdigitated NFET was laid out with ground-signal-ground pad configuration which is suitable for Cascade Microtech probes. Before measurement, the probes are first calibrated by using Cascade Microtech supplied calibration standards and twelve measurements were made by HP8510 Network Analyzer for its internal 35

42 error model. Exact electrical delay of the cable was then dialed into HP8510 to move the reference plane to the probe tips. The DC bias of the device is supplied through the internal bias-t of the network analyzer. In order to remove the effects of the pads from the device under test (DUT), S-parameters of the DUT-plus-pads and stand-alone pads must be measured separately. The S-parameters are converted into Y-parameters and the pad Y-parameters are subtracted from the DUT-plus-pad Y-parameters. The remaining Y-parameters describe the transistor alone. The twoport S-parameters are converted to Y-parameters by, 1 + s 22 s 11 s 1 2s y = y 1 + s 22 + s 11 + s Z 12 = s 22 + s 11 + s Z 0 2s s y s 11 s 1 = y 1 + s 22 + s 11 + s Z 22 = s 22 + s 11 + s Z 0 (1.61) where s = s 11 s 22 s 12 s 21, and Z 0 is the characteristic impedance of the S- parameters. This procedure is outlined in [28]. Figure 1.18 shows the layout of the test device on the left and the dummy pad on the right. The rectangular ring around the device is the metal-2 which is grounded by the probe. The signal pad is shielded from the substrate by grounded metal-1 underneath. The current gain, I o /I i, versus frequency is plotted in Figure 1.19 at four different V eff s. The f T is extracted and plotted against V eff in Figure 1.20 at four points, and equation (1.60) is fit through these points using the parameters shown in the figure. The measured data shows that ω T = 2πf T conforms closely to equation 36

43 Figure 1.18 An interdigitated 2000/1 µm NMOSFET for f T measurement using Cascade probes. A set of dummy pads are also measured to deembed transistor data. (1.60) in the V gs -V t range of interest. This curve serves as an important design aid. We can conclude from this experiment that 1-µm MOS transistors are certainly fast 100 y 21 / y 11 = I out / I in 10 1 V gs -V t Frequency (GHz) Figure 1.19 Measured current gain of a 2000/1 µm NMOSFET at four different V eff 's. 37

44 f T (GHz) µ n = 550 cm 2 /V s θ = 1.6 V -1 L eff =0.7 µm V gs - V t (V) 0.6 Figure 1.20 Measured unity current gain frequency f T vs. V eff. enough for RF applications in the 1-GHz range, and recent submicron CMOS research has produced MOSFETS with f T as high as 18 GHz [29] Large-Signal Performance of MOS and Bipolar Devices Consider a bipolar differential pair which is degenerated by a resistor for increased linearity as shown in Figure 1.21(a). The effective g m is 2/R. Comparing this to a MOS differential pair with the same maximum large-signal swing, the MOS differential pair has an effective g m of 2 2/R, which is 41% higher than the bipolar differential pair. Whereas a grounded MOS differential pair with the same swing would have an effective g m of 4/R, which is twice that of the bipolar pair. 38

45 +1/2v i R -1/2v +1/2v i -1/2v +1/2v i -1/2v I I 2I 2I 2I 4I IR 2(V gs -V t ) 2(V gs -V t ) g m,eff = 2/R g m = 2 2/R g m = 4/R (a) (b) (c) Figure 1.21 Bipolar and MOS circuits comparison. Thus, CMOS devices can offer higher gain for the same swing and power dissipation than bipolar devices. Note that by setting IR = 2 ( V gs V t ) =, (1.62) the V eff of case (c) is smaller than that of case (b). From equation (1.59), the same DC bias currents would make g m of case (c) higher than that of case (b). ( b) 2 ( V gs V t ) ( c) 39

46 1.5.2 Noise Sources in MOS and Bipolar Devices The main noise sources in MOSFET s are the channel thermal noise and flicker noise, whereas the bipolar transistor has thermal noise, base and collector shot noise. Their expressions are shown in Figure The γ is often taken as 2/3 for long channel devices, and it can be as high as two or three for short channel devices [30], depending on the bias point. Since flicker noise is insignificant at RF, MOSFET s actually have less white noise sources than bipolar transistors at radio frequencies. From the above comparisons, CMOS devices indeed are suitable, and perhaps better than bipolar devices for RF applications. CMOS devices can offer high linearity and low noise at RF when they are carefully designed and laid out. v2 n = 4kT γ K ( WL f 0.8 ) g m v2 n = 4kT r b g m v n v n i n 2 = I C β 2 2q I B i n Figure 1.22 Noise sources in MOS and bipolar transistors. 40

47 Chapter 2 Suspended Spiral Inductors The inductor is a fundamental component in RF applications. It is often needed for LNA matching and in LC tank circuits for oscillators. However, it has been a challenge to integrate high-inductance inductors on silicon substrate for RF circuits operating at 1-2 GHz [31][32]. Integrated inductors which self-resonate at 2.45 GHz are limited in their size to approximately 10 nh [33]. Two major obstacles to building large inductors with high self-resonant frequency on a silicon substrate are high substrate capacitance and high substrate loss. The high parasitic capacitance to the substrate makes the self-resonant frequency of inductors larger than 10 nh too low to be used in circuits operating at 900 MHz, and resistive loss in the substrate lowers the inductor Q. In applications where high impedance, thus high inductance, is required, the parasitic capacitance of integrated inductors must 41

48 be lowered to raise the self-resonant frequency. Recent efforts have concentrated on increasing the dielectric thickness and substrate resistivity [34][35]. This approach only marginally increases inductor self-resonant frequency. Some inductor designs also make use of multi-layer metals or even gold [34] to reduce the series resistance in the metal windings and obtain higher Q, but this has little effect on the selfresonant frequency of the inductors. This chapter describes an alternative method which removes the substrate altogether, thus simultaneously increasing inductor self-resonant frequency and Q. It is a CMOS-compatible, post-fabrication maskless etching procedure which selectively removes the silicon substrate and suspends inductors in air. This technique can integrate large inductors with CMOS RF circuits operating in the 1 GHz band. A 12-fold increase in inductance value has been demonstrated. The high inductive impedance provided by suspended inductors can reduce the power consumption in RF tuned amplifiers. This method has also been applied to long onchip signal lines whose capacitance is otherwise too large, and therefore require buffer amplifiers. If only small inductors in 3-5 nh range are needed, the unused inductance could be used to trade for higher Q with this process. In the following sections, the rationale of using large inductors in RF circuit design is first presented. The etching procedure, and improvement in inductor performance are then covered. The potential problems of this technique are also discussed. 42

49 2.1 Inductor Requirements A practical inductor is specified by its inductance, quality factor Q, and selfresonant frequency. The impedance of a real inductor increases with frequency until it reaches self-resonance, when the parasitic capacitance resonates with the inductor. Beyond the self-resonant frequency, the inductor behaves like a capacitor and the impedance decreases with frequency. A qualitative plot of the impedance versus frequency curve is shown in Figure 2.1. The self-resonant frequency is denoted by ω 0. The quality factor Q describes how sharp the resonance is and it is defined by the center frequency to 3-dB bandwidth ratio, ω Q = (2.1) ω The simplest model to describe a practical inductor is a three-element RLC Z in Z max log (Ω) Z max ω R s ω 0 log f Figure 2.1 Qualitative plot of impedance versus frequency of a practical inductor. 43

50 Z in L R C Figure 2.2 Three-element inductor model. model as shown in Figure 2.2. R models the resistance of the inductor winding and the C represents the intrinsic parasitic capacitance. With this model, the selfresonant impedance Z max, self-resonant frequency and the Q at self-resonance are: Z max = L RC (2.2) 1 ω R = LC L LC (2.3) Q 0 ω = = ω ω 0 L R (2.4) Note that this Q 0 is only defined at self-resonance. It is both intuitive and obvious from the above equations that as the parasitic capacitance and resistance diminish, the inductor approaches an ideal inductor and both Z max and ω 0 approach infinity. Inductors are mostly used with extrinsic capacitors to make resonant circuits. Using the model in Figure 2.2, any additional capacitance from the circuit will be in parallel with the intrinsic capacitance of the inductor (Figure 2.3). Therefore, equations (2.2) through (2.4) still apply to the final circuit resonance, except that C is now modified to 44

51 L Z in Inductor Model L Z in V out C par C intrinsic Transconductor C par R Figure 2.3 Parasitic capacitance from the circuit Is in parallel with the intrinsic inductor capacitance. C tot = C par + C intrinsic. (2.5) To obtain the chosen circuit resonant frequency, ω c = ω2 c = Constant LC tot (2.6) L 2 ω2 Z c max = R (2.7) and since Z max L/C tot, (2.8) it follows that with a larger inductance, the L/C tot ratio and thus Z max would increase. For a planar spiral inductor, the inductance is approximately proportional to the number of turns squared, and the resistance is proportional to the number of turns. In Figure 2.8 for example, L is proportional to n 2.2 and R is proportional to n 1.4, where n is number of turns. Therefore, as the number of turns increase in a 45

52 planar inductor, Z max increases. Since higher resonant impedance in a tuned amplifier circuit translates to lower power dissipation for a given voltage gain, the largest allowable inductor must be used in low-power designs. Higher Q in a resonant circuit means better frequency selectivity, and in the context of an LC oscillator, higher Q means lower phase noise [36]. The Q at the circuit resonance is, ω Q c ω c L = = = ω R 1 -- R L (2.9) C tot Again, since L*C tot must remain a constant to maintain the chosen ω c, and L increases at a higher rate than resistance does as the number of turns increase in a planar spiral as mentioned previously, it implies that Q is largest when the largest possible inductance and the smallest C tot are concurrently used. Therefore, as the spiral inductor increase in size, both the Z max and Q increase at a chosen frequency ω c. However, as is shown later in Figure 2.9 and Figure 2.10, the parasitic substrate capacitance lowers the self-resonance of a 20 nh integrated inductor to 1 GHz, which is unusable for circuits intended for 1 GHz operation. This leads to the development of monolithic suspended inductors which are almost free of any substrate capacitance regardless of the spiral size. 46

53 2.2 Inductance Calculation The inductance of a rectangular planar inductor can be accurately calculated by the procedures described in Greenhouse s paper [37]. It is the sum of self inductances of each segment, plus the sum of all positive mutual inductances between adjacent segments, minus the sum of all negative inductances between segments on opposite sides of the spiral. This is shown schematically in Figure 2.4. For metal lines with a rectangular cross section, which is the case for IC s, and relative magnetic permeability of one, the self inductance of a line segment is 1 Positive Mutual Inductance 5 z 4 8 Negative Mutual Inductance Figure 2.4 Positive and negative components of mutual inductances in a rectangular planar inductor.. The relative permeability of aluminum is

54 computed using equation (2.10), L self = 2l 0.002l ln w t w+ t l nh (2.10) where l is the length, w is the line width, and t is the thickness of the metal line. All length dimensions are in centimeters. The mutual inductance between any two segments are computed by using the following equations, M( l, d, w ) = 2 l Q( ldw,, ) nh (2.11) where l is the length of the segments, d is the center to center separation between lines, and w is the width of the lines. The function Q is defined as, l Q( ldw,, ) ln GMD ( dw), 1+ l 2 GMD = + 2 ( dw), (2.12) GMD 1 2 ( dw), GMD ( dw), l l 2 and the geometric mean distance GMD of two lines is, lngmd ( dw), = lnd d w d w d w d w d w (2.13) For metal lines of unequal length as shown Figure 2.5, the mutual inductance is, 2 Mm, j = [ M( m+ pdw,, ) + M( m+ qdw,, )] [ M( pdw,, ) + M( qdw,, )]. (2.14) 48

55 j w j d s m p m q Figure 2.5 Mutual inductance between two metal segments, m, j. The mutual inductance is positive if the currents are flowing in the same direction, negative if currents are in the opposite direction. Thus, the total inductance for a rectangular planar inductor with n complete turns, and z segments is, L tot = z n z 4 L selfi + 2 M ii, + 4j i = 1 j = 1 i = 1 z 2 i = 1 M ii, + 2j. (2.15) A MATLAB script which implements these equations was written to compute and compare the inductance of various inductor geometries [38]. This program takes the line width w, line thickness t, edge to edge distance s, first and second segment lengths l1, l2, and total number of segments z as inputs. It then computes the total inductance, inductance contribution from each segment, and area covered by the metal lines. This program was used to study the winding geometry trade-off s in inductor design [38]. Generally speaking, to improve inductor Q: Inner turns should be left out. Metal width should be as wide as possible. Recent study has shown that in current CMOS processes where aluminum is used, metal width should be limited 49

56 to about 15 µm wide before skin-effect degrades performance severely [35][39]. Metal spacing should be as close as the process allows. The inter-winding capacitance may dominate if metal thickness is much larger than 3 µm. 2.3 Substrate Comparison The silicon substrate affects integrated inductor performance in two ways. It adds parasitic capacitance and introduces resistive or magnetic losses to the inductor. Many silicon bipolar or BiCMOS technologies use a lightly doped substrate, and the substrate resistivity is on the order of 150 Ω-cm [34]. When modeling this type of substrate, a spreading resistance must be included (Figure 2.6). This resistance reduces the Q of the inductor and lowers its self-resonant frequency. If the substrate was simply undoped silicon, its influence on the inductor is only capacitive, thus it only affects the self-resonant frequency. Q is lowered as Aluminum Lossy Si 10~14 Ω-cm SiO 2 Ground Plane ε r 4 Lossless Si ε r 12 Figure 2.6 silicon. Substrate comparison: lowly doped vs. undoped 50

57 a consequence of this change in self-resonant frequency. For highly conductive silicon substrates used in modern CMOS technology, eddy currents can be magnetically induced in the substrate and adversely affect the inductor performance [39]. Inductor performance will dramatically improve when the silicon substrate is removed since the substrate capacitance is substantially lower, and the resistive or magnetic losses are eliminated. Inductor performances on three types of substrates were analyzed in a 3-D electromagnetic simulator, SONNET EM. A 430 x 430 µm, 130 nh inductor was simulated on 14 Ω-cm lossy substrate, purely capacitive substrate, and on air substrate. The thickness of the substrate is 500 µm in all three cases. The S-parameters were converted to Y-parameters and the magnitude of their impedances versus frequency are plotted in Figure 2.7. It clearly shows that the inductor with air substrate would have more than 10-fold improvement in resonant impedance compared to the same size inductor on lightly doped substrate. Due to the increase in self-resonant frequency, the resonant Q of the inductor over an air gap is also increased. The parasitic substrate capacitance is proportional to the physical size of the inductor. However, high inductance can only be achieved with physically large inductors. Figure 2.8 shows that as an inductor spirals outwards from an inner dimension of 146 x 138 µm to 450 x 450 µm at 20 turns, the inductance increases 51

58 10 5 Over Air Impedance 1/Y 11 (Ω) Over Lossless Si Over Lossy Si Frequency (GHz) Figure D EM simulation of inductors on 3 types of substrates. to approximately 140 nh. However, the substrate capacitance also increases proportionally as shown in Figure 2.9. Using equation (2.3), the self-resonant frequency is computed and plotted in Figure Assuming that the minimum selfresonant frequency required for an inductor in a 1 GHz circuit is 2 GHz, Figure 2.10 shows that the largest usable inductor is limited to 5 turns, which is only 10 nh. A 10 nh inductor, being tuned to 1 GHz, offers only 300 to 400 Ω of resonant impedance even if the design guidelines of previous section are followed to maximize Q. More of this will be discussed in Section

59 2.4 Silicon Etching An active area of research in the field of Micro-Electrical-Mechanical- Systems (MEMS) is integrating suspended structures with electronic circuits on IC s. Suspended structures are often employed in integrated sensors and actuators. For instance, integrated accelerometers found in automobiles for air-bag control contains suspended g-force sensing proof-mass which are manufactured by micromachining techniques. However, most MEMS require specially designed IC technology which is not widely available to circuit designers. A CMOS compatible, post-fabrication etching technique was developed a few years ago to fabricate Inductance(nH) Resistance(Ω) Resistance Inductance No. of turns in Spiral Figure 2.8 Inductance increases as inductor gets bigger physically. Inner dimension: 146x138 µm, metal width: 6 µm, separation: 2 µm. 53

60 Substrate Capacitance (ff) No. of turns in Spiral Figure 2.9 Substrate capacitance increases as inductor grow in size. Self-Resonant Frequency (GHz) No. of turns in Spiral Figure 2.10 Calculated self-resonant frequency by using Figure 2.8 and Figure

61 SiO 2 or Si 3 N 4 Aluminum Stacked vias specified during layout Silicon Substrate Figure 2.11 Stacked vias expose substrate after chip fabrication. infrared-point-source pixels [40]. This paved the way for combining low-loss passive components with state-of-the-art CMOS technology. An air substrate can now be inexpensively obtained for monolithic inductors. After modification of the technology file of the layout software, vias can be stacked one upon another during the layout design [38]. These stacked vias leave openings in the passivation down to the substrate after chip fabrication and they become the etchant entry points. The remaining passivation acts as the mask for the etchant. Since the pads are also exposed to the etchant along with the substrate openings, the success of this procedure relies on finding a suitable silicon etchant which is not corrosive to aluminum. The etchant must also have a high selectivity between silicon and the passivation, SiO 2 or Si 3 N 4, which is used as the mask and shields transistors from the etchant. Since stacked vias will be filled by planarization tungsten in planarized IC processes, this method of exposing substrate can only work on non-planarized IC processes. The 1-µm process was the last generation of this process. For planarized processes, the substrate openings can be 55

62 opened by reactive-ion-etch (RIE) using an inexpensive low-resolution mask EDP and TMAH EthyleneDiamine-Pyrocatechol (EDP) has been used in the past as the CMOS-compatible silicon etchant since it has a low etch-rate for aluminum and silicon dioxide [40][41]. However, it is unsuitable for the 1-µm HPCMOS34 process used by this project for three reasons. First, the P+ substrate used in modern short-channel, digital CMOS processes reduces the etch-rate considerably. The typical etch-time of 4 hours for a 800x800 µm pit on P- substrate is increased to 8 hours on P+ substrate. This increased etch-time leads to the second problem: aluminum etch. EDP has a low but non-zero aluminum etch-rate. As the total etchtime is prolonged by the P+ substrate, the majority of the pads are also etched away. Lastly, EDP must be stirred and heated during the etching process. Stirring applies an undesirable pressure on the suspended membranes. Since the passivation of a typical commercial CMOS process is under compressive force to prevent electron migration, the membrane once released from its substrate will easily be shattered when any additional force is applied. As a result, the suspended inductors are shattered by the swirling etchant as soon as they are released from the substrate. Another liquid silicon etchant, tetramethyl ammonium hydroxide (TMAH) [42], was also experimented with but the 15-hour etch results in similar problems. Both EDP and TMAH are anisotropic etchants, and exhibit preferential 56

63 EDP or TMAH Etchant Entry opening specified during layout SiO 2 P+ Silicon Substrate Slows Etch-Rate 800 µm Figure 2.12 Anisotropic pits formed by EDP and TMAH. etching characteristics for <100> crystal planes. With an arbitrarily shaped opening, anisotropic etchants form an inverted-pyramid pit whose base is the smallest enclosing rectangle of the opening. If a few adjacent pits intersect, they would coalesce into one large rectangular pit enclosing all the openings. Figure 2.12 is an example of such a pit, the four trapezoidal openings surrounding an inductor form intersecting pits which eventually merge into one large rectangular pit. The inductor on the right has been manually removed by pressing it down with a probe tip until it breaks to reveal the remaining silicon underneath. Given enough time, the bottom would be etched away forming a wedge. Boomerang-shaped openings shown in Figure 2.13 have been tried in EDP 57

64 with some success. The curved supports release the compressive force in the passivation thus giving high yield for the suspended structure. However, the pads were not able to withstand the long etch time. More of this will be discussed in Chapter Xenon Difluoride (XeF 2 ) Xenon difluoride (XeF 2 ) is an isotropic silicon etchant which exhibits high selectivity to many metals, dielectrics, and polymers used in traditional IC processing. It has no measurable etch-rate on aluminum, silicon dioxide, LPCVD silicon nitride, and photoresist [43]. Unlike EDP or TMAH, the etch-rate is not lowered in the P+ substrate. Most importantly, XeF 2 etching is a gas-phase procedure which is free of the additional contact pressure that liquid etchants put on 800 µm Figure 2.13 Curved supports formed by boomerangshaped openings release compressive force in membrane. 58

65 XeF 2 Entrance Al Stacked vias SiO 2 P+ Silicon Substrate After Fabrication Air P+ Silicon Substrate SiO2 After Etching Figure 2.14 XeF 2 isotropic silicon etchant. the released membranes. This property significantly increases yield compared to liquid-phase etching. XeF 2 is a rocksalt-sized crystal at room temperature and pressure, and it has a sublimation pressure of 4 Torr at room temperature. A vacuum chamber is thus necessary for this procedure. The overall reaction equation for the Si/XeF 2 is 2 XeF 2(g) + Si (s) SiF 4(g) + 2 Xe (g) (2.16) The etching products of XeF 2 etching are all gaseous, thus they can all be effectively removed by the vacuum system. Figure 2.14 shows the cross-sectional view of this process. XeF 2 etches out hemispherical pits underneath the stacked vias. As etching progresses, these pits coalesce into a large cavity over which the inductor is suspended. In the presence of water vapor, XeF 2 forms HF which can etch away both 59

66 400µm 150µm Figure 2.15 Stacked via arrangement for XeF 2 entry. The pit surface resembles an egg carton. passivation and aluminum. Thus, ensuring that the vacuum chamber free of moisture becomes the most crucial precaution for successful XeF 2 etching. Figure 2.15 shows the scanning-electron microscope (SEM) photographs of a suspended inductor and the substrate underneath after etching. The via openings are 60 µm in diameter, each hemispherical pit is about 300 µm in diameter, and the overall pit size is approximately 900x900 µm. The maximum depth of the pit is the radius of each hemispherical pit, which is determined by half the distance between the furthest two via openings. In this case, it is the distance from the edge of the center via, to the edge of the corner via. The eight vias surrounding the inductor are meant to reduce total etch time at the expense of a four-fold increase in area usage. These vias are not necessary if physically small inductors were used. For small inductors, say 100x100 µm, only the center via is necessary and the transistors can also be placed within µm 60

67 to the inductors. Whenever possible, circular vias should to be used instead of rectangular vias, which concentrate the compressive stress on the corners. 2.5 XeF 2 Etching Chamber and Procedure A custom-designed stainless steel vacuum chamber was built from MDC Vacuum Products. One-and-a-half inch wide tubing and vacuum valves with Kwik Flange were used for quick assembly. The vacuum setup is shown schematically in Figure The XeF 2 crystals are placed in a 90 elbow tubing which is sealed off by valve 3, a butterfly valve (KBFV-150). When the elbow tubing is disconnected and moved to a fume hood for loading in new crystals, valve 3 keeps Pump Vacuum Gauge Valve 1 Etching Chamber Valve 2 threaded Expansion Chamber Figure 2.16 N 2 XeF 2 etching system. Valve 3 butterfly XeF2 Crystals. Designed and constructed by Dr. Shahla Khorram. 61

68 XeF 2 from leaking into the air. A quartz viewport tubing was initially used as the source chamber to monitor the amount of XeF 2 remaining, but it turned hazy within a week, probably due to HF etching. Valve 2 is a threaded throttle valve (KAV-150), which regulates the flow of XeF 2 into the etching chamber. The expansion chamber is simply the interconnect tubing of valve 2. It allows XeF 2 crystals to sublimate into a fixed volume of gas, which is later released into the etching chamber. Having two valves between the etching chamber and the source can shield the source from the reaction products during etching. The etching chamber is covered by an acrylic lid sealed with a Viton O-ring. The Viton O-rings around the source show severe degradation after more than one year of continuous exposure to XeF 2. Again, it is suspected that the HF generated from XeF 2 and moisture in the air caused the damage. The acrylic lid did not show any degradation after a few months of continuous usage. Nitrogen is used to purge the chamber. Since this procedure does not require high vacuum, a standard mechanical vacuum pump is adequate and it is connected to the chamber via a threaded throttle valve, valve 1. Figure 2.17 and Figure 2.18 show the front and top view of the vacuum system respectively. A low-power viewing microscope is placed on top of the acrylic lid to monitor the progress and etch-depth. An aluminum block is placed in the etching chamber as the sample platform on which the sample resides at the focal point of the microscope. Before the chips are placed in the chamber for etching, the 62

69 Valve 2 Valve 1 Valve 3 Figure 2.17 Vacuum Chamber front view. A viewing microscope is placed on top to observe the etching process. exposed silicon on the backside and the edges must be protected from etching. Photoresist is painted on manually by using cotton swab sticks. For easy handling, the chips are attached to a piece of microscope slide by baked-dry photoresist. A quick dip in 5% HF just before etching is needed to remove any native oxide which can slow the onset of etching. Experiments show that the etch-rate is increased to about 2 µm per minute when XeF 2 is allowed to remain in the chamber for a few minutes instead of flowing constantly over the chips. This is what we call pulse-mode etching. After a few minutes of etching by a fixed amount of XeF 2, the chamber is purged with N 2 to remove reaction products and a new pulse of XeF 2 is released into the chamber. 63

70 Valve 1 Valve 3 Valve 2 Figure 2.18 Vacuum chamber top view. The chamber is covered by plexiglas for viewing. The following etching procedure ensures that both the XeF 2 source and main chamber stay dry throughout the process. It also incorporates pulse-mode etching XeF 2 Etching Procedure 1. Turn the pump on and open V1(valve 1), V2, the night before etching to dry the chamber. Open V2 and V3, purge the chamber and XeF 2 source with N 2 to dry them before loading the chips. Close V3. 64

71 2. Clean chips with acetone, isopropyl alcohol, and water. Blow dry. 3. Apply AZ5214 photo-resist to the edges of the chips, soft-bake at 90 C for 20 minutes, followed by hard-bake at 120 C for 20 minutes. 4. Dip chips in 5% HF for 5 seconds, rinse in water for 5 minutes. Blow dry and dehydrate samples on a 100 C hot plate for 5 minutes. 5. Close V1, V2 and open N 2 valve to open chamber. Load chips into chamber and open V1 to pump chamber down. Open V2 and purge chamber with N 2 for at least 5 times. The chamber should reach 10 mtorr. Let the chamber stay at this pressure for at least 30 minutes to remove moisture. 6. Check for outgassing and leakage: close V1, make sure that the pressure does not rise from 100 mtorr to 200 mtorr within 50 seconds. Pulse-Mode Etching 7. Close V1, V2 to isolate chamber. 8. Open V3 for about 30 seconds to let XeF 2 out, then close V3. 9. Open V2 slowly to let XeF 2 into the chamber. Chamber pressure rises to 2-3 Torr. Let XeF 2 stay in the chamber for 5 minutes. 10. Open V1 and pump out reaction products. When pressure drops to 200 mtorr, go to step 7 until done. 11. Soak samples in acetone to dissolve photo-resist. 65

72 Clean up 12. Purge XeF 2 source with N 2 after the samples have been removed from chamber. Pump down chamber with V1, V2 open. Close V2 at 5 Torr to keep pressure in the buffer tube equal to XeF 2 chamber. 13. Open N 2 valve slightly and leave the pump on to purge the chamber continuously. 2.6 Suspended Inductor Performance This post-fabrication etching technique allows large inductors to be integrated with CMOS circuits to provide a high impedance resonator. The removal of silicon substrate eliminates resistive or eddy current loss in the substrate, and decouples the substrate capacitance of an integrated inductor from its inductance. The intrinsic parasitic capacitance is now set by the pit size. The pit capacitance can be estimated by the parallel plate capacitance formula when d<<l and fringing fields are ignored, C = εa d (2.17) where ε is the permittivity of air, A is the area of the plates, and d is the distance between plates. However, when d is comparable to l (Figure 2.19), fringing effect must be included, and the capacitance can only be computed numerically. The capacitance of a 400x400 µm 2 parallel plate capacitor is both calculated by equation 66

73 (2.17) and integrated numerically for comparison, the results are summarized in Table 2.1. The capacitance limits to 8 ff as distance approaches infinity. The d (µm) Equation (2.17) (ff) Include fringing (ff) Table x400 µm parallel plate capacitance. limiting capacitance can be estimated by the capacitance of a half-sphere in free space, C limit = 2πεr = 11.1 ff. (2.18) The intrinsic capacitance of a suspended inductor is measured to be 50 ff using the test chip shown in Figure 3.15 and procedures outlined in Section 1.5. Since the calculated wiring capacitance of the 10x100 µm metal-2 interconnect from the probe pad to the edge of the pit is 26 ff using HPCMOS34 design parameters, the 200µm 400x400µm 150µm Air P+ Silicon Substrate d A l Figure 2.19 Estimating pit capacitance using parallel plate capacitance including fringing field.. Program supplied by Jaesup Lee of UCLA. 67

74 pit capacitance is approximately 24 ff. This is result is very close to the parallel plate capacitance separated by 100 µm, which suggests the average depth of the pit. Inductors as large as 120 nh with a self-resonant frequency of 2.4 GHz has been fabricated and used in a CMOS RF amplifier [38][44]. When high inductance is not needed, this technique allows the designer to trade inductance for higher Q by using wider metal windings. Table 2.2 demonstrates three suspended inductor design examples using HPCMOS34 parameters, two metal layers with 36 mω/sqr, 0.75 µm thick aluminum as metal-2. The L s are calculated by the algorithm outlined in Section 2.2, R s are the DC resistances, self-resonant frequencies and Q are calculated by using equation (2.3) and (2.4) respectively. The parasitic substrate capacitances for all three cases are fixed at 50 ff. In the first example, the 128 nh Geometry (µm) 20T, W=5, s=2, 400x400 10T, W=15, s=2, 400x400 4T, w=55, s=2, 400x400 L (nh) R (Ω) ω 0 (GHz) Q 1 GHz Z 1 GHz 4,300 Ω C p = 0.15 pf 1,093 Ω C p = 1 pf 178 Ω C p = 8.4 pf Table 2.2 Different inductor designs for high Z max or high Q. inductor is optimized for high inductance and impedance within the 400x400 µm 2 suspended membrane area (Figure 2.15). When a medium-sized inductor is adequate, the second design shows that the same area can be used to fit wider metal 68

75 windings and improve resonant Q at 1 GHz. If obtaining high Q is the sole objective, the third example shows that a small inductor with a Q of 10 can be designed at the cost of low resonant impedance. Although skin effect may slightly lower the Q in case 3, these examples nonetheless demonstrate the flexibility in inductor design offered by this suspension technique. Since inductor Q at a chosen frequency is only dependent on inductance to series resistance ratio, L/R, when the substrate loss is eliminated, suspended inductors can provide the highest possible Q of all planar inductors, and Q can only be further improved by changing the planar structure or metallization material to obtain better L/R ratio [39]. It is important to note that when comparing inductor performances in the literature, inductor Q must be normalized by the frequency at which it is measured. For example, [45][46][47] claim to have produced suspended inductors with Q s ranging from 6 through 28. Closer examination will reveal that these amazingly high Q s are the result of high frequencies at which these Q s are quoted. The L/R ratio is actually as low as 0.3 to 0.5 nh/ω. Since the inductance values range from 1.1 to 1.7 nh for inductors in [45] and [47], and 7.6 nh in [46], these small inductors are only useful at high frequencies. An inductor with a Q of 20 at 10 GHz would only have a Q of 2 when it is tuned to 1 GHz by an external capacitor. Also, many publications define inductor Q as: Q = IM(Z ind ) , (2.19) RE(Z ind ) 69

76 which goes to zero at resonance. Although Q' is useful in analyzing the intrinsic behavior of the inductor, it can not be applied casually to predict the final circuit resonant Q. This etching technique is also used to suspend long on-chip interconnect wires. As shown later in Figure 5.3, the 3,000 µm long interconnects between the transmitter local oscillator and the receiver downconversion mixer are also suspended along with the 12 on-chip inductors. This dramatically reduces capacitive loading on the local oscillator buffer [48]. This patented suspended inductor [21] enables RF components to be wholly-integrated in CMOS. In addition to the LNA discussed in the next chapter, it is also used in the VCO for LO generation, LO buffer, and power amplifier [4]. As a survey in a recent publication shows [49], no simpler method has yet been found to realize large-value integrated inductors. 70

77 Chapter 3 CMOS RF Front-End Circuits 3.1 Front-End Circuit Requirements The RF front-end of a wireless receiver must meet several exacting specifications. First is sensitivity. The input noise of the front-end must be sufficiently low in order to detect weak input signals. The front-end gain must be high enough to overcome the noise contributions of later circuits, which might otherwise degrade the receiver sensitivity. Second, a front-end with a wide input dynamic range can tolerate large undesired signals nearby in frequency to a weak desired signal, which might otherwise create energy at frequencies overlapping the desired channel, through intermodulation distortion as discussed in Chapter 1. Third, the RF input impedance of the front-end must be a good match to the 71

78 characteristic impedance of the transmission line leading to the front-end. In this system, the dielectric-resonator filter preceding the LNA only conforms to its designed specifications if it is terminated in 50 Ω. Thus, the input impedance of the LNA must be designed to be 50 Ω. These requirements are often interdependent in a simple circuit, and require iterative design for all to be fulfilled. The Low-Noise Amplifier (LNA) and mixer together determine the performance of the front-end. For instance, although a large LNA gain is desirable to overcome noise from later stages, too large a gain can overload the mixer and compromise dynamic range. On the other hand, the gain must be large enough to overcome the fundamentally higher mixer noise. It is also desirable to connect the LNA to the mixer directly, without power-hungry RF buffers. This chapter discusses the design of the front-end circuits used in this receiver. 3.2 LNA Design The LNA used in the transceiver evolved to its final form over many revisions. The initial LNA design was hindered by the co-development of suspended inductor technology. Many of the circuit related problems could not be confidently diagnosed until the etching technique has matured enough to produce repeatable results. This section highlights the CMOS LNA development history, detailing some of the problems encountered along the way, and finally the LNA adopted in this project. 72

79 3.2.1 LNA Development History Following the initial success of a 2-µm CMOS 770 MHz RF amplifier [38][44] in 1992, a 1-µm version of common-source cascode amplifier was similarly designed and fabricated. The schematic diagram and S 21 measurement set-up of the first 1-µm version is shown in Figure 3.1. Since the outcome of fabricating suspended inductor in the 1-µm process was unknown at this early stage, the initial design goal was to achieve a respectable voltage gain at 1-GHz with very low power consumption. Low-noise matching circuit was intended to be provided by off-chip low-loss passive matching network. The 2000/1 input device was chosen to provide 20 ms of g m at 2.5 ma. The 150/1 cascode device was chosen to obtain a small parasitic capacitance which resonates with the 123 nh onchip suspended inductor. In order to facilitate testing in the 50 Ω environment, a 50/1 attenuating buffer was placed on-chip along with a stand-alone version of this buffer for loss calibration [38]. The post-layout simulation (Figure 3.2) using HP s worst-case BSIM model (Level 28 in HSPICE) shows an on-chip voltage gain of 32 db. The dashed-line is the overall S 21 of this amplifier including a 20 db loss due to the attenuating buffer loaded by the 50 Ω load presented by port-2 of the network analyzer, this curve is used to compare with the measured results shown later. The S 21 is simulated in HSPICE as follows. Since the losses in the 73

80 Out+ 50µm 3 V 123 nh 172Ω 35fF In- Out- 150µm In+ 2000µm 5 ma L=1µm Mini-Circuits ZFSCJ-2-4 HP11612A Bias-T 45 MHz~26.5 GHz In+ Out+ Balun 100 Ω LNA 100 Ω Balun Out- In- HP 8720 Network Analyzer Figure 3.1 Schematic diagram of early versions of LNA and S 21 measurement setup. 74

81 On-chip Voltage Gain S 21 including on-chip attenuating buffer Figure MHz HSPICE AC simulation of the first version of 1-µm LNA. transmission line between the network analyzer ports and the 2-port network under test can be calibrated out before measurement, they become ideal transmission lines introducing only a delay, and this delay can also be compensated for during measurement by moving the reference plane of the network analyzer to the input of the 2-port network. This is effectively setting l = 0 in Figure 3.3, and the expression for S 21 is simplified to, b S 2 21 = ---- = a 1 a 2 = 0 V out V s 2 (3.1) wherea i is the incident voltage to port i, b i is the reflected voltage from port i. It is 75

82 Port 1 of Network Analyzer Port 2 of Network Analyzer 50Ω V in l V out V s a 1 b 1 2-Port Network Under Test b 2 a 2 50Ω 50Ω 50Ω 50Ω l=0 V s + V in - 2-Port Network Under Test + V out - 50Ω Figure 3.3 Simulating S 11 and S 21 in SPICE. important not to replace V s /2 by V in when circuit input impedance is matched to 50 Ω because the typical matching response is not flat, and the input matching resonances would distort S 21. That is, V out V in = S S S (3.2) Similarly, S 11 is simplified to, b S 1 V in a = = = a 1 a 2 = 0 a 1 V in V s 2 (3.3) Note that S 11 is a complex number and it is crucial to maintain the complex 76

83 + 1V - 400nH k= V 200nH - Common Mode Bias + 200nH 0.707V M k = L 1 L 2 Figure 3.4 Ideal balun model used in simulations, lossless above 100MHz. relationship in the conversion, i.e. S 11 = V in Re V s 2 1 i Im V in V s 2. (3.4) Losses in the baluns are also calibrated out before measurement, thus an ideal balun model shown in Figure 3.4 is used in simulations. This amplifier was however not tested until one and half years later due to the difficulties encountered in producing suspended inductors in HPCMOS34 process. The spiral inductors in the first 1-µm LNA were supported by diagonally opposing cantilever beams similar to those used in the 2-µm version shown in Figure However, the compressive stress in the oxynitride passivation of the HPCMOS34 process caused the supports to buckle and shatter as soon as the inductors were released from the substrate. An experimental chip (Figure 3.5) containing various support designs was subsequently fabricated to see if curled supports could re-direct the stress. The amplifier circuit remained the same. The. Discussion with Prof. Kristofer Pister, now at U.C. Berkeley, is crucial to the success. 77

84 Stress Relief Curled Supports Figure 3.5 Experimental chip with stress-release support structures. curled supports proved to be successful, however, due to the long 8-hour etching time as discussed in Section 2.4.1, most of the pads were damaged by EDP (Figure 3.6). Photoresist can not be used to shield the pads since it is also soluble in EDP. Electroless nickel plating on the pads has also been experimented with but without success. Although suspended inductor yield was improved, wirebonding or probing were impossible on these chips. The same circuit was again fabricated (LNA3 in Figure 3.7) with the best inductor support structure learned from the previous experimental chip, while a way of protecting the pads from the etchant was sought for. Liquid etchant TMAH with 78

85 Figure 3.6 Aluminum pads were damaged by 8-hour EDP etch. Stress Relief Curled Supports Figure 3.7 LNA3 with stress-relief suspension technique. 79

86 dissolved silicon has been shown to have low aluminum etch-rate [42], and it was experimented with LNA3. However, the pads were still etched away due to the 15- hour etch-time. In addition, the undissolved silicon powder bombarded and shattered the suspended membrane as the solution was stirred. XeF 2 was first experimented with LNA3. Photoresist was manually painted on the four boomerang-shaped openings and baked dry leaving only the center via opening as the XeF 2 entry point. Due poor moisture control, the passivation and pads were etched away on most runs, and the edges of the chips were also severely etched making these chips extremely difficult to handle. Improper choice of photoresist also allowed some etchant to leak through the photoresist covering the boomerang-shaped openings and formed irregularly shaped pits. Few chips survived the etch when all the conditions happened to be right, and the survivors had only partially suspended inductors. Those chips were packaged and tested. To alleviate the effort of building separate test boards for each chip with the die-on-board method outlined in [38], the etched chips were bonded into 40-lead Leaded Chip Carriers (LCC) from GigaBit Logic (GBL) shown in Figure 3.8. This package has signal feed-throughs and a ground plane (V TT ) on the top surface for microwave decoupling capacitors or termination resistors. This package is then pressed cavity-down into a 40-contact socket by a spring-loaded plunger on the socket lid (Figure 3.9). Cin-apse wire button contacts in this socket adds 0.63 nh 80

87 V TT : Package-top ground plane V TT Cavity 0.25 in 0.5 in Impressions of Socket Contacts Signal Feed-throughs Figure 3.8 LNA bonded in a 40-lead package which is inserted cavity-down into a socket for testing. of inductance to the package leads according to the data sheet. The socket mates with the gold plated 50 Ω microstrip lines on the top layer of test board (Figure 3.10). Decoupling capacitors are placed on the bottom side (Figure 3.11) of the test board, they are located directly underneath the socket contact points. This set-up greatly simplifies RF circuit testing. Figure 3.9 Cinch Connector Company socket. Spring-loaded heat-sink presses the package down on gold contacts. 81

88 Socket Location Figure 3.10 Top view of Gigabit Logic glass-epoxy test board, GBL 90GT40. Semi-rigid mini-coax connect the SMA connectors to the gold-plated microstrip lines. 82

89 Figure 3.11 Bottom view of test board showing decoupling chip-capacitors. 83

90 The measured S 21 of LNA3 were quite inconsistent across samples, and they were generally tuned to MHz. Two sample measurements are shown in Figure 3.12 and Figure The 20-dB loss due to the attenuating buffer were included in these measurements. The frequency shift was suspected to be caused by the extremely unstable etching process and partially suspended inductors. In order to pin-point the cause, two new chips were fabricated simultaneously. Figure 3.14 shows the amplifier db Figure 3.12 Measured S 21 of a partially etched LNA3. Loss in the attenuating buffer is included. This is plotted with the same scale as Figure 3.2 for comparison. 84

91 db Figure 3.13 S 21 of a different LNA3 sample. (LNA4) with a new etchant via design suitable for the isotropic etchant XeF 2, and Figure 3.15 shows the test chip, which will be referred to as cascade in the following text, intended for RF characterization of the MOSFET s and inductors in LNA4 using Cascade probes. An enlarged view of the transistor layout and measurement methods are found in Section 1.5. The metal-2 RF pads of these two chips were all shielded by metal-1 underneath to eliminate the substrate spreading resistance which is discussed later in this chapter. The circular vias were 60 µm in diameter, they prevented stress from concentrating at corners of a rectangular via. 85

92 Figure 3.14 LNA4 with etchant vias designed for XeF 2. RF pads are shielded from the substrate spreading resistance. Dummy pads were used to determine pad capacitance. With proper control of moisture in the XeF 2 vacuum chamber this time, the yield of this new etchant vias design was 100%. LNA4 was tested using the same package-and-socket system as LNA3. However, LNA4 samples were consistently tuned to approximately 700MHz (Figure 3.16) even with fully suspended inductors and a much more stable etching process. 86

93 Dummy Pads Figure 3.15 A test chip, cascade, designed for Cascade probes to verify transistor and inductor models. Dummy pads are used to determine pad capacitance Figure 3.16 Measured S 21 of LNA4 including the attenuating buffer loss. 87

94 The test chip cascade in Figure 3.15 was then etched by XeF 2 and probed by Cascade probes. The S-parameters of the transistors at various bias points and inductor S-parameters were measured from 45 MHz to 10 GHz by HP8510 Network Analyzer. The S-parameters of the transistors at their respective bias points in the circuit were then converted to Y-parameters using equation (1.61), and the Y-parameter of the measured pad capacitance (80fF for a 40x40 µm pad) were subtracted from the Y-parameters. The amplifier transfer function was determined from the Y-parameters at each frequency point. Figure 3.17 schematically shows this computation. It is derived that, y 22 + y' 11 + y' 12 + y' 21 + y' 22 ( y' 12 + y' 22 ) y' 21 + y' 22 ( y' 22 + Y load ) V x V out V in V in = y 21 0, (3.5) and V out /V in can be solved for by using Cramer s rule, V out Y load V out Y V in y 11 Y load y 12 y 22 V x y 21 V in Y y 11 y 21 y 22 y 12 Figure 3.17 Finding V out /V in using measured Y-parameters. 88

95 V out V in = y 22 + y' 11 + y' 12 + y' 21 + y' 22 y 21 y' 21 + y' (3.6) y 22 + y' 11 + y' 12 + y' 21 + y' 22 ( y' 12 + y' 22 ) y' 21 + y' 22 ( y' 22 + Y load ) The measured results matched with worst-case model HSPICE simulation extremely well (Figure 3.18). A DC measurement of the transistor shows that the g m indeed lined up with the worst case g m at the same bias conditions. This test shows that the HSPICE Level-28 BSIM model supplied by HP works well to at least 2 GHz, and the suspended inductor model is also quite accurate at the frequencies of interest V out /V in (not S 21 ) (db) Nominal Model Measured S-parameters Figure 3.18 Worst Case Model 1 2 GHz Vo/Vin from simulation and measured S-parameters. 89

96 The next potential culprit for causing the frequency shift was package parasitics. The package lead-frame model is shown in Figure 3.19 [50], and the cavity model is shown Figure Along with the bonding diagram shown in Figure 3.21, the post-layout circuit containing the parasitic wiring capacitances was enclosed in the 40-pin model and simulated. The floating leads of the package were To next pin 85fF 85fF 1.08nH 1.08nH Bondwire Pad 235fF 235fF 85fF 235fF Ω 670fF To Socket Contact 85fF 1.08nH 235fF 235fF 85fF 235fF 85fF 85fF fF nH 660Ω Bondwire Pad 670fF 1.08nH 1.08nH Bondwire Pad 235fF 235fF 85fF 235fF 85fF To next pin 85fF Node1: Cavity Paddle Node2: V TT 2 660Ω Lead Model 670fF Figure 3.19 GBL 40-lead LCC model. 90

97 Left Side of Cavity Right Side of Cavity 1.5pF 0.32nH 0.64nH 0.32nH 1.5pF 16.5pF 16.5pF 4.9pF 4.9pF 23Ω 10pF 10pF 23Ω 0.32nH 0.64nH 0.32nH Left V TT 2nH 2nH Right V TT Figure 3.20 Circuit model of the cavity paddle and the ground plane on top of the package, V TT. Vdd Stand-alone Buffer for Gain Calibration Out+ Cascode Bias In+ In- Out- Cascode Bias Gnd Bias for I-src Figure 3.21 Bonding diagram of LNA3 and LNA4. 91

98 simulated by connecting them to grounded 1 GΩ resistors. The HSPICE microstrip line model was also included in this simulation to model the effect of the test board, and the simulated S 21 is shown in Figure There is a 2-dB gain attenuation, the center frequency, however, remained at 900 MHz. The next likely cause for the frequency shift is the parasitics present on the gate bias of the cascode transistor. It was a mistake to bring out the cascode bias separately since this would cause a differential current to flow in the parasitic inductances of the bondwire and package. More of this will be discussed later in equation (3.20). However, sweeping inductance on the cascode bias node from 5 nh S21 (db) 900 MHz Figure 3.22 Simulated S 21 of post-layout LNA4 with 40-lead package model and HSPICE microstrip line model. The loss in the attenuating buffer is included to facilitate comparison with measured S 21 in Figure

99 to 50 nh in SPICE showed that this would cause an extra resonance to form with a much higher gain, but the resonance due to the on-chip inductor would still remain at 900 MHz (Figure 3.23). A 35 nh inductor was needed to create a resonance at 700 MHz, by sweeping the Q from 1 to 10 of a 35 nh inductor at 700MHz (Figure 3.24), it showed little effect on the designed resonance at 900MHz. Thus, it was concluded the parasitic inductance on the cascode gate bias was not the cause for the off-tuning problem. This parasitic resonance is however a potential cause for oscillation, so a spectrum analyzer shared the LNA output with port-2 of the network analyzer via a power splitter to check for oscillation, but none was found. Another suspicion was that the mutual inductance between the two on-chip S 21 (db) Figure 3.23 Sweeping cascode gate bias parasitic Inductance value from 5nH to 50nH in 5 nh steps, the Q of the inductor is set to 4. 93

100 Figure 3.24 Sweeping Q of the 35nH parasitic inductance from 1 to 10, resonance at 900MHz remains unaffected. inductors de-tuned the circuit. This is quite unlikely for two reasons. First, the two spirals were spaced approximately 500 µm apart, so the mutual inductance, M, between the two closest segments was 0.03 nh according to equation (2.11). This corresponds to a coupling coefficient K of 0.068, where K = M L 1 L 2 (3.7) L 1 and L 2 are self inductance of these segments, and M is the mutual inductance between them. All other segments would have smaller values since they were farther apart and progressively shorter. The upper limit of the aggregate mutual inductance of the spirals can be computed by assuming that all 20 turns were 94

101 K = M L 1 L K 0 Mutual Inductance (nh) Distance (µm) Figure 3.25 Mutual inductance and K factor between two parallel 400x4 µm wire segments vs. 10 to 500µm of separation. located at the outermost edge of the inductors, i.e. all 20 turns were 500 µm apart, and that they were all equally long, then 20 x 20 x 0.03 nh = 12 nh. Since each spiral has 120 nh of self inductance, the coupling coefficient K is less than 0.1. Second, the spirals are wound in opposite directions, resulting in a positive mutual inductance. The effect of mutual inductance on the tuning can be easily simulated in SPICE and it is shown in Figure It shows that positive mutual inductance can only increase the resonant frequency, not lower it. 95

102 k= k=0.8 k=1 Figure 3.26 Mutual inductance between suspended inductors, coupling coefficient k swept from -1 to 1 in steps of 0.2. Another experiment was performed in an effort to understand what was causing the resonance shift. The cascade test chip was bonded into a 40-lead LCC and tested in the same socket and board as LNA4. Figure 3.27 is the bonding diagram of a packaged cascade, the gate and drain of the stand-alone transistors shared the same mini-coax and microstrip line traces on the board as the LNA input and outputs (Figure 3.21). The S 21 of the single transistor measured in the packagesocket-board combination is plotted along with the S 21 measured by Cascade probes in Figure The packaged transistor showed high-q resonances between 700 to 900 MHz, which was not explained by the package model. 96

103 V TT Bond to Paddle D D 2000/1 150/1 G G S V TT Figure 3.27 Bonding diagram of a single MOSFET in a 40-lead LCC. Figure 3.29 shows the simulated S 21 with the complete 40-lead package model shown previously. It shows that the package parasitics only affects the S 21 at frequencies above 2 GHz. The additional resonance should come from the boardto-socket and socket-to-package interface which was the only part left out in this simulation. Although no definitive answer was found to explain the off-tuning problem, several lessons were learned to prevent similar problems in the future: The gate bias of the cascode device must be carefully decoupled on-chip to 97

104 S21 (db) Probed Packaged GHz Figure 3.28 Measured S 21 of a packaged 2000/1 NMOSFET vs. Cascade probed data at identical bias conditions, V gs -V t =500 mv, Vds=2V, Id=22.78 ma. prevent oscillation. Adjacent pins of RF signals should be grounded to reduce package coupling. Package parasitics should be considered during LNA design phase since it is a vital part of the circuit. All off-chip parasitics are part of the LNA, thus exact models of the parasitics are necessary to predict LNA performance. 98

105 20 10 HSPICE S21 (db) 0-10 Measured GHz Figure 3.29 Simulated S 21 of a 2000/1 NMOSFET in the 40-lead package model (Figure 3.19) vs. the measured results Matched Common-Source LNA The previous design (LNA4) did not consider the low-noise requirement. The design focus was merely on the amplifier gain at 1 GHz. In order to fulfill further requirements on matching and noise, the common-source amplifier with inductive de-generation is examined. The gate of a MOSFET fabricated in 1-µm technology is capacitive to frequencies beyond 1 GHz, assuming that the gate has been laid out in an interdigitated fashion (Figure 1.18). However, a lossless matching network, 99

106 consisting only of inductors and capacitors, can transform the FET input into a pure resistance over some frequency band of interest. The most common matching network for FETs consists of a series feedback inductor, L s, in the FET source, and another inductor, L g, in series with the gate to tune out the capacitance C gs, resulting in an input resistance g m L s C gs where g m is the FET transconductance shown in Figure 3.30 [51][52][53][54][55]. This method is preferred over resistor feedback because the matching network introduces no noise of its own. However, losses in practical inductors L g and L s will tend to degrade noise figure. With sufficiently good inductors, though, a noise figure well below 3 db may be obtained with this technique, ultimately limited by such transistor imperfections as non-zero gate resistance as we shall see shortly. The input impedance of the CS amplifier is Z in L g Z in L g C gs + V gs C gs - L s g m V gs L s g m L s C gs Figure 3.30 The input equivalent circuit of a common source amplifier degenerated by an inductor in the source. 100

107 Z in = = g m L s + s( L g L ) C gs + s sc gs ω T ω T L s + s( L g + L s ) sg m. (3.8) The first term is a frequency independent resistive term whose value is set by ω T and L s. It can be set to R s, or 50 Ω for LNA. L g plus L s and C gs must be chosen to resonate at frequency of operation, ω 0 1 ω 0 = = ( L g + L s )C gs (3.9) ( + ) g m L g L s ω T The inductor L g is needed to control the resonant frequency since L s is constrained by the impedance matching criterion. This is a narrow-band matching technique since the impedance is only real at the resonance of the input circuit. This matching method can achieve excellent noise performance because the signal is amplified by the Q of the resonant circuit before reaching the noisy active device. Ignoring losses in L g and L s, the Q of the input circuit is Q 0 ω 0 L ( L g + L s ) = = ω R g m L s L g + L s = ω R s R s C gs (3.10) The noise figure of such an amplifier can be found by considering Figure The FET produces only thermal noise in the inversion layer, modelled by the single 101

108 i o i o L g L g i n R s C gs V ns C gs L s R s L s Figure 3.31 Schematic diagram used for noise figure calculations. current source, i n. The output noise current due to the transistor alone is i o --- i ñ = 1 + sc gs ( R s + s( L g + L s )) (3.11) 1 + s( L s g m + C gs R s ) + s 2 C gs ( L g + L s ) The output noise current due to source resistance alone is i o v ns = g m (3.12) 1 + s( L s g m + C gs R s ) + s 2 C gs ( L g + L s ) And the noise figure is i 2 o γg NF 10log m R s = = log i o ω T, (3.13) γr = 10log s ω T ( L g + L s ) and the effective transconductance in the tuned band is: ω o 102

109 i G o m = = = ω 0 ( R s + ω T L s ) v ns ω T ω T , (3.14) ω 0 2R s which is independent of transistor g m. We see that g m may be chosen arbitrarily low to reduce noise figure while maintaining gain. However, as g m is reduced to improve noise figure, we see from equation (3.9) that L g must be increased to maintain ω 0. From equation (3.10), we see that the Q of the input circuit is also increased. This makes the matching more sensitive to component value variations. For example, if f T of the transistor is biased to be 2.6 GHz, the required L s is 3 nh from equation (3.8). Choosing g m to be 20 ms, L g to be 17.7 nh and barring any other losses, this amplifier will achieve a minimum noise figure of 0.4 db at 1 GHz. The Q of the input resonant circuit is then 1.3 from equation (3.10). Now consider another example where a smaller transistor is biased to have the same f T of 2.6 GHz, but reducing g m to 5 ms. The minimum noise figure would now become 0.1 db at 1 GHz with a nh L g, however, the Q of the input resonant circuit would now become 5.2. This method of reducing noise figure will cause the IIP3 to drop proportionally to the resonant Q. Further, if an inductively tuned load is used, a cascode device must be used because the C gd feedback current suffers large phase shifts which may de-stabilize input and alter matching conditions. Another practical issue involved in this topology is the effect of parasitic capacitance at the gate. Using a series of parallel-to-series conversions at the 103

110 L g C gs L g L g Cpar C eq R L g C par L s R= g m L s C gs C par C eq R C eq R Parallel-Series Transformations Figure 3.32 Effect of pad capacitance on matching is analyzed by parallelseries conversion outlined [56]. resonant frequency (Figure 3.32) [56], the real part of the input impedance synthesized by g m, L s and C gs is reduced by the parasitic capacitance, R = R , (3.15) C eq + C par C eq where C par is the sum of pad capacitance, package capacitance, and Miller capacitance from C gd of the input device. This topology was simulated and the half-circuit schematic diagram is shown in Figure The parasitic gate capacitance, resistance, and inductor losses are all included in this simulation. The matching has been designed with 200 ff of parasitic capacitance at the gate. The off-chip 39 nh inductor is modeled by a Coilcraft chip inductor as shown in Figure For simplicity, the AC resistance of the chip inductor is fixed at 2.8Ω which produces the correct NF at 1 GHz. Similarly, the AC resistance of the 3 nh inductor is the value at 1 GHz. The on-chip 104

111 2.6 V 50 Ω 60fF 48 nh 1.1 V Off-chip =39 nh L g 2.3 V 4Ω V out 300µm 1.85 ma 160µm R s V in Bias-T V g C par =200fF 4Ω C gs =300fF On-chip Load 300µm g m =8.106mS L s =3nH R AC =0.37Ω Off-chip Figure 3.33 Simulation schematic diagram of CS circuit, off-chip inductors are modeled by Coilcraft chip inductor model. voltage gain reaches 36.5 db, and the S 11 is -23 db as shown in Figure The same figure also shows the real and imaginary parts of V in. There is indeed a 15 db voltage gain at the gate of the input device, node Vg in Figure This gain is shown in Figure The minimum noise figure of the entire circuit is 1.15 db, and 80 ff 20 Ω R DC =10 mω R AC = 2.8 1GHz R AC =k f 39 nh k=90e-6 Figure 3.34 Coilcraft 39 nh chip inductor model. 105

112 Av db S 11 Re(Vin) Im(Vin) Figure 3.35 Simulated voltage gain, S11, real and imaginary parts of Vin. Resistances in inductors and MOSFET gates are included. Gain at LNA Gate, Vg db Figure db voltage gain at the gate of input device lowers NF. 106

113 db NF of input device alone db NF of complete circuit Figure 3.37 NF of input device alone is 0.26 db, overall circuit NF is 1.15 db at 980MHz. the NF due to the input device alone is 0.26 db (Figure 3.37). As a sanity check, all the resistive losses and the input parasitic capacitance are removed and re-simulated (Figure 3.38), the results are shown in Figure The minimum noise figure from the input device alone is db, which is close to the db predicted by equation (3.13). The matching inductor L g is now increased to 55nH and the S 11 is increased to -13 db due to the absence of the 200 ff parasitic capacitance. We did not use this amplifier because of its sensitivity to parasitic capacitance. Since the parasitic capacitance at the input would have a strong 107

114 2.6 V 50 Ω 60fF 48 nh 2.3 V V out 300µm 160µm R s Vin 1.1 V Bias-T L g = 55 nh V g C gs =300.6 ff 1.85 ma On-chip Load 300µm g m =8.141mS L s =3nH Figure 3.38 Half-circuit schematic diagram of a more ideal CS LNA. Av db S 11 Re(Vin) Im(Vin) db NF of input device alone Figure 3.39 CS LNA without the parasitic gate capacitance and losses. 108

115 influence on matching, the precise package model must be known ahead of time. The common gate amplifier is used instead because it is less sensitive to parasitic capacitance than the CS LNA Common Gate Amplifier When a noise figure of 3 db is acceptable, as it is in our receiver, it is simpler to regulate the input impedance with a common-gate input stage [57]. For the sake of discussion, first suppose that the load resistance at the drain is much less than the FET r ds, and that g m r ds 10. Then the input resistance at the FET source is 1/g m. At 1 GHz, the FET C gs and parasitic input capacitance, C p, due to the bonding pads and external strays significantly shunt this resistance. Therefore, to achieve a good impedance match, the size and bias of the FET are selected for 1/g m = 50 Ω, and an inductor tunes out the shunt capacitance by parallel resonance in a frequency band L Out C d +C P AC Gnd Z in = gm 1 C gs C p Figure 3.40 Common-gate amplifier used as LNA. 109

116 around 1 GHz. As the capacitance at the LNA input is to be tuned, it makes good sense to do so with a grounded off-chip low-loss inductor, which also carries the LNA bias current. Fortuitously, a FET with a small-signal channel resistance of 50 Ω produces a lower thermal noise current than a linear resistor of the same value [22]. The noise current spectral density in the FET is 4kTγg m A 2 /Hz, where γ 0.67 owing to the distributed inversion layer. Thus, ruling out any other noise sources in a matched LNA, the noise figure due to the FET alone is 10 log 1.67 = 2.2 db. In a shortchannel FET biased at unfavorable conditions, hot-electron effects may augment this [30] to raise the noise figure. Flicker noise in the FET is unimportant at RF. A tuned load peaks the frequency response of the LNA in the band of interest (Figure 3.40), in effect transforming the inherent lowpass characteristic of the amplifier to a bandpass. The load also helps to reject out-of-band signals and noise. However, the LNA passband is seldom sufficiently flat and narrow for RF preselection, that is, to suppress image channels and out-of-band interferers. Rather, a sharply tuned discrete filter, such as SAW or dielectric resonator, is inserted before the LNA for this purpose. Since signal energy occupy both upper and lower sidebands after downconversion in a direct-conversion receiver as explained in Section 1.3, no preselect filter need follow this LNA, nor the associated RF buffers to drive the filter. 110

117 The tuned load, therefore, comprises an inductor resonating with the FET drain capacitance, C D, and the sum, C P, of the input capacitance of the subsequent downconversion mixer and any other parasitic capacitance. Another advantage of the common-gate stage is that the somewhat large C gd of the FET returns its current to a fixed bias, rather than to the input node as it would in a common-source amplifier. This current undergoes rapid phase-shifts with frequency in an RF tuned amplifier, and makes it difficult to design an input matching circuit. The inductance, L, to tune this total capacitive load to the resonant frequency ω 0, in our case 2π Grad/s, is L = 1/ω 2 0 (C d +C P ). (3.16) In most modern FETs, the drain junction capacitance C d C gs. Furthermore, the unity-current gain frequency, ω T = g m /C gs. The inductance may then be expressed as L = (3.17) ω 2 0 ( g m ω T + C P ) If inductor loss, as modelled by a series resistance R ind, limits the impedance of the tuned load at resonance, then using equation (3.17), the voltage gain of the common-gate stage is, ( ω 0 L) 2 Gain = g m = R ind ω T L (3.18) 1 + ω T C P g m R ind This form makes it clear which parameters are within the circuit designer's 111

118 reach to determine RF gain. ω T mainly depends on FET channel length, but is also controlled by gate bias as shown in Section 1.5. However, even with infinite ω T, parasitic-related quantities will limit the maximum achievable gain to: Max Gain min g m L = , g m r ds. (3.19) C P R ind In the common-gate amplifier, the desired input impedance sets g m. Thus, a large parasitic capacitance at the drain means a smaller achievable gain, unless the loss in the load inductor is somehow lowered to boost the gain. The relative quality of the inductor, L/R ind, depends on how it is physically realized, and there are limits to how large this may be in practice. For instance, at 1 GHz the L/R ind is 4 nh/ω for a discrete 10 nh chip inductor meant for RF applications [58]. This argues for an on-chip inductor load, because it is unlikely that a discrete off-chip inductor can overcome, simply because of a higher quality, the RF gain loss due to the large parasitic capacitance of the bond pads, bondwires, package leads, and board traces. Also, as shown in Chapter 2, high impedance at a chosen frequency can only be achieved by large inductance, not just high L/R ind ratio. Using equation (3.17), the load inductance may be calculated which tunes the LNA to a certain frequency in the absence of any significant parasitics. For instance, if the FET is biased at an f T of 5 GHz, then the LNA requires a 40 nh inductor load to achieve a peak at 1 GHz in its frequency response. This inductor 112

119 may be implemented on-chip using the suspended inductor technique described in Chapter 2. Figure 2.8 shows that in the inductance range of 30 to 50 nh, the relative quality, L/R ind, of the spiral is about 0.7 nh/ω. It is seen from equation (3.18), equation (1.59) and Figure 1.20 that the LNA may achieve a gain as large as 20 db at 1 GHz in the absence of parasitic capacitance, while drawing 1.5 ma of current per FET. As discussed in Chapter 2, the main impediment to a practical implementation of the tuned amplifier arises from the parasitic capacitance of a 50 nh spiral inductor to the semiconductor substrate when it is not suspended. This is so large through the typical 1um-thick field oxide (Figure 2.10) that the spiral selfresonates at 700 MHz, and at 1 GHz appears as a capacitive, rather than inductive, load on the LNA. This is why it is generally believed that medium- to large-value inductors may only be integrated on semi-insulating substrates, while on a standard silicon substrate inductors no larger in value than 5 to 10 nh are usable at 1 GHz [59]. Using XeF 2 etching technique described in Chapter 2, inductors as large as 100 nh may be fabricated in CMOS, whose self-resonance frequency, now limited by the small fringing capacitance through the air gap to the distant ground plane, lies beyond 2 GHz. It was assumed in the earlier analysis that the impedance, Z, of the LNA tuned load is much less than the FET r ds. When this is not so, the expressions for the gain and input impedance is modified to: 113

120 Z Z g g m r ds V out C gs V in Z in Figure 3.41 Input impedance of a common-gate stage. Gain g m Z 1 = ; Z. (3.20) Z in g Z = m r ds r ds When parasitic impedance is present at the gate bias, the input impedance of a common-gate stage as shown in Figure 3.41 is modified to, ( Z+ r Z ds ) ( 1 + jωc gs Z g ) in = , (3.21) 1 + g m r ds + jωc gs ( Z g + Z+ r ds ) and the gain is, Gain = g m Z Z jωc gs Z g r ds. (3.22) Z r ds If Z g is an inductor, it would resonate with C gs to shunt the input to ground causing Z in to be zero, and the gain would approach infinity. Thus, it is crucial to properly decouple the bias on the gate to obtain proper input impedance and gain. An LNA prototype was fabricated along with a downconversion mixer. The 114

121 Vc 3V M µm To Mixer L bond M1 On-Chip Suspended Inductors C gs C gd +C par V g 50 nh, 50Ω, 60 ff To Mixer M2 300 µm 4nH Off Chip C Pkg C pad 1pF 0.2pF 10nH Figure 3.42 LNA in the stand-alone front-end prototype. LNA is shown in Figure 3.42, and the mixer will be discussed in the next section. The 50 nh inductor has 12 turns, 10 µm wide metal-2 windings separated by 2 µm spacing. Its outer dimension is 420x420 µm. This inductor design achieves a L/R ratio of 1 nh/ω. A power-conserving, passive balun converts a single-ended antenna signal into a balanced input drive to the LNA. A printed-circuit balun may even be integrated into the transceiver case. Figure 3.43 shows a rat-race balun which has less than 0.5 db of loss, and it was found that most of the loss came from the SMA connector-to-board interface. The bias, V G, at the common-gate FETs regulates the LNA input impedance. An on-chip scaled-down replica circuit may stabilize this impedance against variations in process and temperature as follows.. Original design by Ahmadreza Rofougaran and Maryam Rofougaran.. Rat-race balun prototype was designed and characterized by Joe Colburn. 115

122 6cm Figure 3.43 Rat-race balun fabricated on a Duroid board, the loss of this prototype is less than 0.5 db. An op-amp drives the V G bias voltage of the replica to servo the DC value of 1/g m to an off-chip reference resistance, and the same voltage is then applied to the main LNA, thereby regulating its input impedance to within the FET matching in the replica and the main circuits. As the feedback loop bandwidth is well below 1 MHz, the op-amp does not contribute any RF noise. The inductor loads on each half of the circuit share a common top-node, which connects to the 2V power supply. It sets the DC bias at the LNA output which in turn sets the mixer input bias. Taking into account the capacitive load of the mixer, the LNA requires 50 nh load inductors to obtain a peak at 1 GHz in its frequency response. 116

123 The LNA transistors are laid out in an interdigitated fashion, similar to the layout shown in Figure Sixty 5/1 µm transistors are placed in parallel to reduced gate resistance, whose noise adds to the noise figure directly. The polysilicon gate resistance is reduced to approximately 2 Ω by shorting both edges with metal. A ring of grounded diffusion contacts surrounds the transistors to reduce interference due to substrate coupling. The LNA input pads are specially designed for low-noise operation. The standard MOSIS pad consists of 100-µm squares of Metal-2 and Metal-1 shorted together. This pad is however unsuitable for RF applications, because it is capacitively coupled through the oxide to the non-zero spreading resistance of the grounded silicon substrate. At 1 GHz, the pad impedance is resistive when the capacitive portion is tuned out by an external inductor. Consider a 100x100 µm metal-2 pad over field oxide and silicon substrate, the spreading resistance in the 10 µm thick epitaxial layer is, R ρl 10Ω-cm 10µm = ---- = = 100Ω, (3.23) A 100µm 100µm and its capacitance is approximately 220 ff. The impedance at 1 GHz is therefore 100-j723 Ω. When the capacitance is tuned out by a matching circuit, the pad impedance would be 100 Ω. In practice, this resistance can range anywhere from 30 to 80 Ω depending on the actual pad area and interconnect width. This parasitic resistance upsets the input impedance matching, but more seriously it is a 117

124 10~14 µm thick 10 Ω cm Epi Metal-1 Shield l Highly Conductive Substrate Si Figure 3.44 RF input pads to LNA. Metal-1 shields the input signal from spreading resistance of substrate. significant source of thermal noise. In fact, due to the pad alone, the LNA noise figure would be about 3 db before any FET noise is taken into account. This problem always appears on silicon substrates at RF, although its magnitude varies with substrate doping. It has been noted before in discrete RF bipolar transistors [60]. The pad is modified to shield the RF input from this parasitic resistance (Figure 3.44). Instead of shorting the two layers of metal, Metal 1 is connected to a high-frequency ground, and the RF input pad is composed of Metal 2 alone. The pad impedance is now purely the capacitance between Metal 2 and Metal 1, and is no longer a source of noise. The off-chip inductor tunes out the pad capacitance with the various other capacitances that appear at the input node. This is a satisfactory though fragile solution, in that the pad is more susceptible to damage through the weak inter-metal dielectric during wirebonding, and it cannot tolerate the loading of standard electrostatic protection devices. An alternative is to short the 118

125 Balanced Signals Virtual Ground for balanced Signals Diffusion Layer as Shield Si Figure 3.45 Alternative RF pad shielding method for differential signals. two layers of metal, but then place a heavily diffused layer under them which is connected either to ground, or stays at virtual ground when a balanced signal is applied to adjacent pads (Figure 3.45). Post-layout simulation in Figure 3.46 shows 28 db of voltage gain, and -10 db S 11. The gate bias is at 1.2 V drawing 3.2 ma each, and the g m is 11.2 ms at this bias level using worst case BSIM model. The minimum NF is 2.6 db at 1 GHz, lowered from the 3.4 db calculated from 11.2 ms of g m due to a moderate gain of 2.44 db at the input. When a more complete package model, like the one shown in Figure 3.19, and lossy off-chip inductor models are used, the simulated results are shown in Figure The additional package parasitics would reduce the real part of the input impedance to 38 Ω and improves the S 11 to db, thus lowering the NF to 119

126 R in R s Balun LNA Vs=1 Re(In) = 0.5 if R in = R s =50 Ω Av at input 2.44dB LNA Av 20log S11 Re(In) Im(In) NF(dB) Figure 3.46 LNA Vg biased at 1.2V drawing 3.2 ma each. G m =11.2 ms, gain at input of LNA reduces NF to 2.6 db. Ideal off-chip inductor. below 2 db. It is interesting to note that both 38 Ω or 66 Ω of R in would yield -17 db of S 11, however, they would yield different NF in this circuit. The off-chip 10 nh inductor includes a 1 Ω AC resistance in this simulation, and a conservative estimate of 4 Ω gate resistance is also included. The common-gate stage is much less sensitive to input parasitics than the common-source amplifier when it comes to matching since the 50 Ω input resistance of the amplifier is in parallel with the reactive network of the input parasitics, thus reducing the Q of input reactive circuit. 120

127 LNA Av Av at input 2.75dB 20log S11 Re(in) 38Ω Im(in) NF (db) Figure 3.47 LNA with package model, g m =11.2 ms at 1.2 V gate bias. Matching inductor includes 1Ω ac resistance, and the input transistor has 4Ω of gate resistance. A series of two-tone transient simulations were performed on the LNA to determine its linearity. One example of HSPICE generated FFT result is shown in Figure With -30 dbm (incident power) tones at 976 and 986 MHz enter the input, this LNA achieves an IIP3 of IIP3 70 = ( 30) = +5 dbm, (3.24) 2 The vertical scale of this plot is 20log ( V amp ) 6 db FFT loss, thus the db outputs on this plot in response to a 10 mv amp input corresponds to a voltage gain of 28.8 db. This corresponds to an OIP3 of dbvrms. 121

128 70 dbc dbv amp - 6 Figure 3.48 LNA output spectrum of two-tone IM3 simulation. 3.3 Downconversion Mixer The amplified signal at the LNA output is converted down in frequency for further amplification, channel-select filtering, and detection. The frequency mixer is an integral part of the RF front-end. There are two fundamentally different ways to implement a mixer in CMOS. The first, somewhat unconventional method, uses a MOSFET as a wideband analog switch. A passive track-and-hold circuit, consisting of a 1-µm FET switch and a grounded capacitor, is designed for a trackmode bandwidth of greater than 1 GHz. This follows the waveform of a modulated 1 GHz carrier, and samples it at a much lower rate which must be at least twice the 122

129 Sampling instants RF In IF Out Figure 3.49 Subsampling mixer working principle. modulation bandwidth. An op-amp feedback circuit clocked at this low sample rate buffers the held output, and removes signal-dependent charge injected by the switch. When the sample rate is an integer sub-multiple of the carrier frequency, the interpolated samples directly downconvert the RF signal to DC (Figure 3.49). A prototype evaluated at a 900 MHz RF shows very good linearity, but fundamentally suffers from a large noise figure, because while tracking the narrowband signal, it also tracks and aliases wideband noise [61]. This, and the difficulty of buffering such a switched mixer to the inductive load of an integrated LNA, make it inappropriate in a sensitive receiver. The second, more conventional, mixer resembles the Gilbert analog multiplier. It consists of a linear RF voltage-to-current (V-I) converter, or RF transconductor, whose output current is commutated by the local oscillator (LO) (Figure 3.50). As commutation conserves the total current, it downconverts only a fraction of the RF current to the IF, and the remaining RF current upconverts around one or more harmonics of the LO. The voltage conversion-gain of the active mixer 123

130 Asin(ω RF t) + g m - LO R LO IF Out LO LO Figure 3.50 Fundamental components of a mixer. is independently set by choice of the transconductance and load resistance. The internal current conversion-loss penalizes mixer noise, as is analyzed later. A good mixer is highly linear, and its input-referred noise does not overwhelm the amplified noise of the preceding LNA. The mixer handles larger signals than the LNA, and therefore its nonlinearity must be lower by at least a factor of the LNA gain if it is not to become the bottleneck to receiver dynamic range. This is why the following discussion concentrates on mixer nonlinearity, as the LNA, with the choice of bias voltages, is not the bottleneck to front-end linearity. Third-order intermodulation distortion in a double-balanced mixer may cause two large adjacent-channel signals to create energy at spurious frequencies coincident with a weak desired channel. The linearity of a front-end is specified by the input-referred third-order intercept point (IIP3) [62]. Often this is set by the static and dynamic nonlinearity in the RF V-I converter of the mixer, or by the static nonlinearity in the mixer load. 124

131 i i V V 1 - V V 2 i=2k ( V gs V t ) v i=k v 2I ---- V 2 K Figure 3.51 Linear MOS transconductor. Differential pair is not as linear. Linear MOS transconductance circuits have been studied extensively in the context of continuous-time active filters operating at frequencies up to tens of MHz [63]. These circuits exploit the property that the dominant second-order nonlinearity in a MOSFET circuit cancels in balanced differential inputs and outputs. For instance, if two identical common-source FETs conforming to the classic long-channel I-V characteristics are biased at some V GS (Figure 3.51) and excited differentially by a large signal V in whose amplitude is less than 2(V gs -V t ), then the differential output current W I out = µc ox ---- L ( V gs V t )V in (3.25) depends linearly on V in, and the bias V gs -V t sets the transconductance [64]. Residual third-order nonlinearity produces a small distortion in the transconductor. However, its large signal handling is limited by clipping, when an 125

132 M12 M13 g m7 3/5µm 960µm 960µm M14 M10 M11 M15 M6 M7 LO- 300µm M9 LO+ From LNA g m4 80µm M5 Figure 3.52 Schematic diagram of the downconversion mixer in the front-end prototype. input swing of V gs -V t turns off one of the FETs in the circuit. These sources of static nonlinearity are expected to govern the mixer up to and beyond 1 GHz, as no significant nonquasi-static effects are likely to set in given the short carrier transit time in the 1-µm channel. Dynamic nonlinear currents which grow with frequency will flow in any voltage-dependent capacitance, and this might even become the significant form of distortion at 1 GHz. The MOSFET, however, is benign in this respect, as its main capacitance, C gs, is relatively independent of bias for V gs > V t and behaves like a linear capacitor in the saturation region of operation. The MOS downconversion mixer is a balanced circuit (Figure 3.52),. Original design by Ahmadreza Rofougaran. 126

133 comprising a linear common-source FET transconductor (as opposed to a differential pair in the bipolar Gilbert multiplier shown in Figure 3.51), four commutating FET switches, and a high-swing load consisting of a center-tapped polysilicon resistor across pull-up current sources. Common-mode feedback from the center tap biases the current sources at a well-defined voltage. The LNA output is directly connected into the differential mixer input. The mixer attains its peak conversion gain when a sinewave of at least 1 Vptp (+5 dbm into 50Ω) is applied to the commutating switches M6-M9. This also lowers the total front-end noise figure. While it is obvious that incomplete commutation leads to conversion loss, what may not be evident is how it also degrades noise figure. The transconductor FET s and the loads clearly contribute noise in the mixer. In addition, the commutating switch FETs also contribute noise at discrete time intervals over the switching cycle. The time-varying aspects of the circuit must be understood to estimate the magnitude of this contribution. Over most of the duty cycle, one FET in each switched pair appears as a resistor in series with transconductor, while its companion FET is off. The series FET contributes very little noise, determined only by the finite output impedance of the transconductor FET s at 1 GHz. However, during a zero-crossing of the LO, the two companion switch FET s carry comparable drain currents, and act, for the purposes of noise analysis, like a differential pair amplifier. They then contribute a short burst of balanced noise current to the mixer load with a spectral density proportional to 127

134 the switch FET transconductance, which elevates the average mixer output noise [53]. A larger LO drive to the mixer forces zero crossings with a greater slope, and as the switches now dwell for a shorter fraction of the period in the high noise condition, the overall mixer noise is lowered. It is a good assumption that under large LO drive, the mixer commutates the RF transconductance current with a square wave. Simple expressions may now be derived for the mixer conversion gain and its equivalent input noise. Referring to Figure 3.52, suppose a unit sinusoidal input voltage of frequency ω RF is linearly converted to a current, and commutated by the switches at ω LO, which amounts to multiplying the sinusoidal current by a square wave, sq(ω LO t), alternating between +1 and -1. The current flowing into the loads, I IF, is then I IF = g m1 sinω RF t sqω LO t = = g m1 4 ω RF t -- 1 sin π sinω LO t + -- sin3ω 3 LO t π gm1 cos ( ω RF ω LO )t (3.26) where the square wave is expanded as a Fourier series, and the term containing the downconverted frequency at ω RF -ω LO is retained. Equation (3.26) shows a current conversion loss of at least 2/π (=0.64) through this mixer. The overall mixer voltage gain is Mixer Gain 2 = --, (3.27) π gm1 R L 128

135 which may be adjusted to any reasonable value by the load resistance, R L, attached to the low-frequency output node. Noise due to the mixer loads is referred to the input in the following way: the noise current is divided by the conversion loss; the noise spectrum is translated from ω IF to ω RF ; and the noise is distributed equally between two image sidebands around ω LO which will downconvert to the same ω IF if ω IF is small. Suppose that the transconductor and load FETs (M12, M13) (Figure 3.52) produce only thermal (white) noise, that the commutating switch FETs contribute no noise, and that the noise due to the polysilicon resistor loads is negligible. Then the noise referred to the mixer input is: ν n2 = 1 1 4kTγ π -- 2 g m12 +. (3.28) g m4 g m4 As M4 and M12 share the same bias current, it follows that with the FET sizes used in this circuit, g m g m4 = µ P W( M12) (3.29) µ N W( M4) From (3.28) and (3.29), this means that noise voltage referred at the mixer input is 1.8x larger than if the input FET s (M4) were the sole source of noise. In the case of direct-conversion where ω IF =0, flicker noise in the load will further elevate, indeed dominate, the mixer input noise. The NFET s at the mixer input are biased at V gs - V t = 0.75V, and drain 2.4 ma each from the 3 V supply. From equation (3.28), the input-referred noise 129

136 voltage level of this mixer is about 3.5 nv/ Hz, which is overwhelmed by LNA output noise of roughly 12 nv/ Hz due to its own FETs. We conclude that the mixer does not appreciably degrade the noise figure of the front-end. The V gs -V t of the pull-up PFET current sources is also 0.75V, and as the signal level at the mixer input is 1.4x at the output, clipping will commence at the transconductor input. It is shown in equation (1.36) on page 28 that the rms value of a sinewave falls by 1 db when it is clipped to 79% of its undistorted amplitude. This predicts that at the above bias points, the conversion gain of the front-end will compress by 1 db due to clipping at the mixer input when a balanced sinewave of about -4 dbm is applied to the LNA. For the purposes of stand-alone testing, open-drain PFET s connect to the mixer output to drive off-chip loads. They require an additional bias current, which is high enough to enable them to drive a large power level into the 50Ω impedance of measuring instruments. However, in the intended on-chip use, they will be radically scaled down in size to drive a small capacitive load. The simulated output spectrum of a two-tone test on the LNA and mixer front-end is shown in Figure The input is applied to the LNA as shown in Figure 3.48, and a 952 MHz LO is applied to the mixer which downconverts the input tones to 24 and 34 MHz. The front-end IP3 at LNA input is then, 130

137 60 dbc Figure 3.53 Mixer output spectrum of two-tone IM3 simulation. 60 LNA and mixer combined IIP3 = ( 30) = 0 dbm. (3.30) 2 With the overall conversion gain of 26 db, the OIP3 is then +26 dbm or +16 dbvrms. This is very close to the measured OIP3 of +28 dbm shown in the next section. 3.4 Front-End Prototype Evaluation A stand-alone version of this RF front-end, LNA and mixer combination, was fabricated and tested prior to receiver integration [65]. Figure 3.54 is the chip. Measurements in this section were performed by Ahmadreza Rofougaran. 131

138 Figure 3.54 LNA and Mixer front-end prototype chip photo. photo. The chip is mounted in the 40-lead LCC microwave package and tested in the socket-and-board system described previously (Figure 3.8 to Figure 3.11). A low-loss, power-conserving balun (M/A-COM H-183-4, 30MHz-3GHz balun) applies a balanced RF stimulus from a single-ended signal source. A low frequency power-combiner converts the balanced outputs into a single-ended signal for measurement. In most cases, the LO is offset from the RF input to produce a 10 MHz IF, which makes it easy to use AC-coupled instruments. However, the circuit is also evaluated in selected ways as a direct-conversion front-end. The LNA frequency response (Figure 3.55) is deduced from measurements on the overall conversion gain, by accounting for the mixer gain from transient simulations. Due 132

139 25 20 LNA Gain (db) Measured Gain SPICE Simulation -5 to oscillation observed at high-gain bias condition, the measurement was done at V gs -V t =0.35V, drawing 2.2 ma each. SPICE, with standard static FET models and a simple three-element inductor model [38][44], predicts the LNA response quite well Frequency (GHz) Figure 3.55 LNA frequency response, measured and SPICE simulation. The scattering parameter S 11 measures the input reflection coefficient, and thus the quality of the LNA input impedance match (Figure 3.56). An S 11 of -16 db at 1 GHz is satisfactory for many applications, and implies a net input resistance of about 70 Ω, consistent with the FET g m. Due to the lower bias condition to avoid oscillation, the input impedance is now higher than 50 Ω, instead of lower than 50 Ω as shown in Figure 3.47, but the magnitude of S 11 remains similar. 133

140 Input S 11 (db) Frequency (GHz) Figure 3.56 Measured input reflection coefficient versus frequency. Another relevant attribute of the front-end is its ability to handle large signals without harmful distortion. Two equal-strength, closely-spaced tones around 1 GHz are applied to the LNA, and the strength of the corresponding downconverted tones f 1, f 2 is measured, as well as the strength of the spurious tones at 2f 1 - f 2 and at 2f 2 - f 1 produced by third-order intermodulation. Whereas the main tones grow proportionally with the RF input amplitude, the distortion terms grow as the third power, and when extrapolated on logarithmic scales, the spurious tones grow as large as the main downconverted tones at an input of +8 dbm (Figure 3.57). This is the input-referred third-order intercept point (IIP3). The measured IIP3 is higher than the simulated value due to the lower measured gain. To compensate for this gain loss in IIP3 comparison, output IP3 is compared instead. The measured 134

141 20 IF Fund. & IM3 (dbm) RF Input (dbm) Figure 3.57 Linearity of front-end, LNA and mixer combined, measured with two-tone in LNA passband. OIP3 is +28 dbm which is close to the simulated +26 dbm. In practice, the LNA gain will collapse at a lower input, and although the IIP3 is the standard for specifying linearity, the 1-dB compression point better expresses the limits to linear operation. This is the input level, about -3 dbm for this circuit, at which conversion gain falls by 1 db because of the onset of clipping. This is very close to the -4 dbm predicted previously. It is something of a challenge to measure the noise-figure of a directconversion receiver. A noise figure meter such as the HP 8970B can only measure noise at 10 MHz IF or above, yet its accuracy is unmatched by any other technique, because it simultaneously measures output noise and conversion gain. This meter is 135

142 therefore first used to calibrate the noise-figure of the front-end at a 10 MHz IF. It measures the output IF noise levels in response to two reference levels of wideband noise spanning 10 MHz to 1.6 GHz. The correct double-sideband (DSB) noise figure is obtained when there is no RF preselect filter [62], because just as in the intended use for direct-conversion, both image sidebands around the LO contribute noise, as well as providing the input stimulus for gain measurement. Then, after grounding the input of the front-end through a 50 Ω resistor and applying a 1 GHz LO, the output noise spectral density is measured on a spectrum analyzer in the frequency interval from 0 to 10 MHz. If necessary, a wideband amplifier with a known gain and a bandwidth of more than 10 MHz is used to boost the front-end noise above the measurement floor of the spectrum analyzer. Any inaccuracy in the figure for double-sideband conversion-gain of the system is corrected by matching the input-referred noise spectral density at 10 MHz with the reading from the noisefigure meter. The noise-figure is then extrapolated to an arbitrary low frequency from the readings on the spectrum analyzer. A DSB noise figure of 3.2 db is measured on the noise-figure meter at a 10 MHz IF, which compares very favorably with the theoretical 2.9 db noise figure of a single FET with a common-gate input impedance of 70 Ω (Figure 3.58). In typical fashion of narrowband amplifiers, the noise figure rises as the matching deteriorates away from the tuned frequency of the input matching circuit-in this case, 0.9 GHzand this is exacerbated by the declining LNA gain on either side of 1 GHz (Figure 136

143 DSB Noise Figure (db) IF=10 MHz RF Input Freq. (GHz) Figure 3.58 Direct noise figure measurement at 10 MHz IF. 3.55), when the mixer contributes more noise. Noise figure at low IF is deduced from spectrum analyzer measurements. Flicker noise now appears (Figure 3.59), contributed by the mixer pull-up current sources (M12, M13), and the PFET output 16 DSB Noise Figure (db) Ideal 1/f Intermediate Frequency (MHz) Figure 3.59 Noise figure deduced from output noise spectrum at frequency offsets from zero IF. 137

144 buffers (M14, M15). The load FET s (M10, M11) do not carry a bias current, and therefore contribute no flicker noise. After direct downconversion, the peaks in the spectrum of a 160 kb/s FSK signal lie at ± 160 khz, where flicker noise raises the front-end DSB noise figure to about 4.5 db. Second-order nonlinearity in the baseband section of a front-end also impairs a direct-conversion receiver [8][66]. It detects the envelope of any unwanted AM signal in the LNA passband, and creates spurious energy at DC which overlaps, and may even overwhelm, the downconverted desired signal at DC. A fully-balanced circuit mitigates this to a large extent. The residual distortion is characterized by downconverting a 918 MHz carrier, which is amplitudemodulated at a 100% index by a 150 khz tone, to an 18 MHz IF, and observing the spurious energy appearing at 150 khz. The spurious tone grows with the second power of the carrier amplitude, and the magnitude of this nonlinearity is characterized by a second-order intercept, which referred to the input of this circuit is about +25 dbm (Figure 3.60). This is much higher than the IIP3, and therefore is not expected to be a major limitation to receiver dynamic range. Finally, the DC offset at the output of a zero-if receiver appears in the middle of the downconverted signal spectrum. This offset will overwhelm the received signal, unless removed with capacitive coupling or nulled by some form of digital offset estimation [8]. These remedies are, however, only partly effective in the case of a dynamic offset. For instance, the offset may consist of a component 138

145 40 Carrier & Spurious (dbm) RF Input (dbm) Figure 3.60 Second-order intercept plots growth of detected envelope at DC versus AM signal strength. due to self-downconversion of LO leakage (Figure 1.7), and in this frequencyhopped receiver, this will inevitably change with the instantaneous LO frequency. The output offset has been measured on two IC s over a broad sweep of the LO (Figure 3.61). Interestingly, it remains constant to within 5 µv over the sweep from 950 to 1025 MHz, but then changes rapidly by up to 60 µv in the vicinity of 1050 MHz. Over the MHz ISM band, the output offset changes by about 10 µv. The methods to remove offset described above cannot easily track the variations produced by an LO hopped by a pseudo-noise code, but it is expected that the spectrum of the varying offset will be noise-like, and given the small size of the dynamic offset, it will only slightly raise the receiver noise floor. It is not clear what 139

146 60 40 Mean Offset ~ 3 µv Output Offset (µv) Frequency (MHz) Figure 3.61 Change in output DC offset as LO frequency is varied, as measured on two samples of the front-end test chip. causes the offset to depend so sharply on frequency, but parasitic resonances onchip and in the package are suspected. 140

147 Chapter 4 Baseband Circuits and Receiver Integration 4.1 Channel-Select Filter An on-chip switched-capacitor filter selects the desired user's channel after the entire ISM band has been downconverted and de-hopped by the front-end. The circuit design details of this filter can be found in [12] and [67]. This section relates the filter performance to the system. The channel-select specifications call for a lowpass filter with a passband edge at 230 khz, and a stopband edge at 320 khz with a stopband loss of 50 db to suppress the adjacent channel (Figure 4.1). Since the order of the filter determines. Original design by P. J. Y. Chang and A. Rofougaran. 141

148 0 db f pass = 230kHz 0 to -1dB 280kHz -24dB 320kHz dB f (khz) User 1 User 2 Figure 4.1 Channel-select filter specification. Frequency spectrum of 4- FSK pseudorandom modulation shown in passband. the number of op-amps, a low-order realization is sought to reduce size and power consumption. A sixth-order elliptic filter fulfills the magnitude specification, given the sharp transition band. The group delay, however, changes somewhat across the elliptic filter's passband. This happens to be not very important for FSK detection, where the detector is sensitive only to frequency and not to phase. The group delay of the elliptic filter varies by 3 µs across the range of the signal frequency spectrum (Figure 4.2), which is 10% of the 12.5 µs symbol period. This degrades the received SNR by at most 0.5 db [5]. In this application, the main impairment arises at a carrier frequency hop, when the sudden change in phase upon a new frequency propagating through the wireless channel from the transmitter to receiver stimulates a time-domain transient in the receiver's channel-select filter. The sixth-order elliptic filter is implemented by a cascade of three 142

149 20 Group Delay (µs) Signal BW Frequency (khz) Figure 4.2 Group delay variation of elliptic filter. biquadratic sections (Figure 4.3). Although the filter characteristics of a ladder are less sensitive to element-value variations, a cascade of biquads with distributed gain gives the circuit designer more flexibility to optimize dynamic range. The nonlinearity of the filter is measured by how well it handles overload caused by RF Prefilter 26 MHz 915 MHz >40 db LNA Dehop & Downconvert 12 db 57.2 MHz 620 khz 12dB 2nd-Order Butterworth Prefilter 50dB at 13 MHz 14.3 MHz 230 khz 320 khz 50dB 6th-Order Elliptic Channel Filter To Q-Channel BQ1 Q = 0.65 Gain = 2 BQ2 Q = 8.1 Gain = 2 BQ3 Q = 1.9 Gain = 1 Figure 4.3 Switched-capacitor channel-select filter specifications. 143

150 large off-channel interferers. By interspersing amplification with filtering, the desired signal progressively grows through the filter and the interferers diminish, and at the later stages of the filter where the signal swing is largest, the interferers are substantially attenuated. The three biquad sections are cascaded according to their Q-factors [68]. The low-q section appears first, to attenuate high frequency out-of-band signals and input noise, and to ease the requirements on any antialiasing filter prior to the SCF. The high-q section follows, so the preceding gain lessens the noise it contributes to the filter input, particularly near the passband edge where its input-referred noise spectrum rises. The medium-q section is placed last. Nonlinearity defines the upper end of the dynamic range, and filter noise the lower end. The input-referred noise spectrum rises as the frequency approaches the passband edge. This phenomenon is well-understood, arising from the noise contributions of high-q sections [68]. Similarly, at low frequencies the noise spectrum rises because of flicker noise. If the spectral density of the input-referred noise is unequal at the frequencies of the two baseband FSK tones, then the higher noise of the two sets the filter dynamic range. The capacitance spread in a switched-capacitor filter is approximately set by the ratio between the sampling rate and the corner frequency of the filter [68]. To lower this spread, a multirate filter-cascade configuration is used. The elliptic filter is clocked at 14.3 MHz, and a second-order Butterworth prefilter is placed before the elliptic filter clocked at a four-times higher rate, 57.2 MHz. The prefilter rejects 144

151 downconverted channels 14.3 MHz away and its integer multiples of this offset, which fall in the images of the elliptic filter passband. When combined with the offchip RF prefilter, which attenuates non-ism band signals 57 MHz away from the desired channel by at least 15 db, the net filter stopband loss is at least 52 db, typically 65 db, extending from 320 khz to well beyond 60 MHz. For convenience, the sampling frequencies of the Butterworth prefilter and the elliptic filter are derived by dividing down the LO in the receiver, f LO, by a power-of-2. For two reasons both related to lower noise, this filter must also amplify the signal. First, with amplification in the first stage of the filter cascade, later stages contribute less to the overall noise. Second, for a given feedback capacitor, gain in the first biquad requires use of a larger sampling capacitor, which therefore also contributes a lower kt/c noise. Gain is assigned to each block in the cascade to balance signal amplification and lower noise on the one hand, and on the other hand to preserve good large signal-handling. That is, with too high a gain in the blocks, the filter input noise becomes so small that it is overwhelmed by the noise of the preceding stages, but now a small input signal to the filter clips the output and compromises the overall receiver dynamic range. Various gain assignments were considered to optimize the dynamic range of the filter, and finally a gain of 4x is assigned to the pre-filter, 2x to both the low-q and high-q biquad sections, resulting in a total filter voltage gain of 16x, or 24 db. In addition to improving dynamic range, this distribution of gains flattens the input noise spectrum across the 145

152 passband. Placing gain in the first few biquads compromises the filter IIP3 because a smaller input signal now saturates the last op-amp in the cascade. However, as is shown later in Section 4.4 on system dynamic range planing, a lower IIP3 is a price worth paying to lower filter noise. With a total voltage gain of 16x (24 db), the filter's input-referred voltage noise spectral density is 40 nv/ Hz. The balanced filter uses a total capacitance of 200 pf, and drains 7 ma from 3V. For two input tones located 1 MHz in the stopband, whose intermodulation product falls in the filter passband, the measured IIP3 is 7V (rms). The filter samples the output of the mixer buffer (Figure 4.24), whose role is also discussed in Section 4.4. The on-chip 30 pf capacitor at the buffer output limits high frequency noise, which otherwise aliases in-band after sampling and raises the receiver noise figure. 4.2 Limiting Amplifier and RSSI The filter output is directly connected to a limiting amplifier. This circuit also provides a logarithmic measure of the input voltage [69]. The core of the limiter consists of a direct-coupled cascade of 7 differential pairs, each with a voltage gain of 12 db (Figure 4.4). The 84 db gain is so large that in the absence of an input signal, the amplifier output limits on its own noise.. Design and tested by S. Khorram, M. Djafari, and A. Rofougaran. 146

153 I II III 140 µf 40 kω Off-chip RSSI Figure 4.4 Limiter consists of three types of amplifiers. Full-wave rectifiers generate RSSI using successive-detection algorithm. In a direct-coupled receiver, offsets are typically on the order of tens of millivolts can overwhelm the received signal, typically fractions of a millivolt at baseband, and pin the limiting amplifier output to one extreme or the other. DC feedback around this limiting amplifier suppresses offsets added by the mixer or filter, or within the limiting amplifier itself. A lowpass filter in the feedback loop measures the average value of the limited output, and subtracts this off from the input (Figure 4.4) in a differential differencing stage. Although the limiting amplifier is nonlinear, the action of the DC suppressing feedback may be roughly understood with a superposition argument. The negative feedback loop gain at DC 147

154 is 84 db, and the dominant pole in this loop, set by the off-chip R and C, rolls off the loop gain to below 0 db at the lowest signal frequency, 80 khz in this system. Therefore, if at a very small input signal none of the limiting amplifier stages is clipped, feedback suppresses the DC component by 84 db with respect to the signal. As the signal gets larger, it drives the later stages of the amplifier into clipping, which at first sight may lower the relative suppression of the DC offset. However, actually this is not so, because the offset manifests itself in the duty cycle of the clipped output signal. It is found by simulation that the output duty cycle with feedback remains unchanged, whether the input is a sinewave of 100 µv or 1 V with an added offset of 100 mv. Any deviation from a 50% duty cycle lowers the correlation output from the detector over a symbol period, as described in the next section, and thus the output SNR. Using a large clipping level counteracts this, because feedback now overcomes a given offset by a smaller imbalance in duty cycle. The clipping levels here are ±1V. Noise on the input signal randomly modulates the zero crossings of the clipped output. The common-source differential differencing stage at the limiting amplifier input (Figure 4.5) can handle input offsets even greater than 1 V. If a large offset cuts off one input FET, the other common-source FET converts the (now singleended) input signal to a differential swing at the loads, the limiting amplifier senses this, and feedback corrects the offset through the other half of the differencing input stage. 148

155 From Feedback Amp-I 100 µm 60 µm 5 kω 60 µm L=1 µm Figure 4.5 Limiter Input stage, Amp I. Figure 4.6 is the schematic diagram of the core amplifier, type-ii in Figure 4.4. This seven-amplifier cascade is followed by the output buffers shown in Figure Amp-II 6 µm 6 µm 200 µm 200 µm 54 µm L=1 µm Figure 4.6 Gain-of-four core amplifier in limiter. 149

156 Amp-III 60 µm To Detector 5 kω 20 µm L=1 µm Figure 4.7 Limiter output stage, Amp-III. 4.7, labelled as III in Figure 4.4. The buffer is capable of driving 12 pf of off-chip loading. The limiting amplifier is designed with a relatively wide small-signal bandwidth of 10 MHz. As the preceding channel-select filter has suppressed adjacent channels by more than 52 db, the limiting amplifier's own noise and filter noise in the stopband mainly occupy the excess bandwidth. The subsequent correlating detector filters out this noise. Full-wave rectifiers, each consisting of two unbalanced differential pairs [70] with a unidirectional current output, tap each differential pair and sum their currents into a 10 kω on-chip resistor (Figure 4.8). This implements the successivedetection algorithm [71], and the resulting approximately logarithmic voltage indicates the received signal-strength (RSSI). Measurements on a stand-alone prototype verify that over 80 db range of input signal, the RSSI output conforms to 150

157 10/5 µm 10/5 µm RSSI 7/5 µm 28/5 µm 7/5 µm 28/5 µm From Amp II Output 80/5 µm Figure 4.8 Received-Signal-Strength-Indicator, RSSI rectifier. an ideal logarithm within 1 db (Figure 4.9). The limiter s group delay changes by 90 ns over its 80 db logarithmic range, with the greatest rate of change at small inputs (Figure 4.9). The group delay varies with input level because at small inputs, the slope of phase versus frequency sets the group delay. Whereas at large inputs, some of the stages in the cascade slew-rate limit and prolong the circuit delay until it reaches a maximum, when all stages are slew-rate limited. This converts amplitude fluctuations in the received signal into phase fluctuations (AM-to-PM conversion), which potentially degrades the SNR in the phase-sensitive FSK detector. The changing multipath interference pattern of a mobile user, or shadowing and fading, all cause random amplitude fluctuations. 151

158 0 5 Group Delay Variation (ns) Log Error Group Delay 85 C 0 C Log Error (db) Input Level (dbm) Figure 4.9 Measured group delay variation and log conformity through limiting amplifier. Simulations show that even in the unlikely event that the received signal suddenly drops by 80 db, and as a result is delayed 90 ns less in the limiting amplifier, the AM-to-PM conversion is so small that the SNR falls by only about 0.2 db. 4.3 Correlating FSK Detector FSK modulation may be fully recovered from the sequence of the zerocrossing times of the carrier (in direct-conversion, this is at 0 Hz). Each limiting amplifier in the quadrature channels drives the downconverted signal to binary levels, preserving the zero crossings. The modulation may be recovered in a frequency discriminator, or in a correlating detector. The latter correlates the. Designed and tested by H.-C. Liu, J. S. Min, and H. Samueli. 152

159 received signal with a locally generated noise-free offset frequency, and it is the optimal detector in the sense that it minimizes the noise bandwidth [72]. The digital 4-FSK correlating detector for this receiver is shown in Figure 4.10 [13]. The detector's front-end clocks at half the frequency of the channel-select switchedcapacitor filter, that is, at 88x the bit rate of 80 khz. An accumulator (digital integrator) increments or decrements the correlation at this clock rate between each one-bit limiting amplifier output and quadrature phases of locally generated 80 khz and 160 khz square waves. By comparing the absolute values of the four sets of correlations accumulated over each symbol interval, the detector makes a one-offour decision. This process seeks the closest match between the received signal and the four possible FSK offsets. The oversampling factor locates the zero-crossing instant to within a quantization error of 1/88 of a symbol period. Lim-I 1-bit Processing cos2π f t I&D + f A + B +2 f Max Select Data (MSB) I&D A + B cos4π f t sin4π f t -2 f sin2π f t I&D A + B - f Mux Sync (9b) Lim-Q I&D A + B Figure 4.10 Digital correlating 4-FSK detector. 153

160 In the frequency domain, correlation with a noiseless signal of period T is equivalent to bandpass filtering around the frequency 1/T. Thus, the four correlators are bandpass filters centered, respectively, at +2 f, + f, - f, and -2 f (Figure 4.11). Their passband width is inversely proportional to the correlation interval, here one symbol period. Figure 4.12 and Figure 4.13 are the measured frequency responses of the detector centered at -80kHz and -160 khz respectively. The frequency responses for 80kHz and 160kHz are simply the mirror images these two plots. These frequency responses are generated by sweeping the frequency of the I and Q input square waves from -300 to 300 khz, and the output values of the four correlators (before Max select) are recorded. Negative frequency is represented by changing the relative phase of I and Q signals by 180 degrees. The correlator frequency response has sidelobes, the largest 10 db below the main lobe. The FSK offsets used in this transceiver were specifically chosen -160k LPF -80k 80k Max Select 160k Figure 4.11 Conceptual picture of 4-FSK detector. 154

161 Magnitude khz Figure 4.12 Measured detector frequency response at -80 khz Magnitude khz Figure 4.13 Measured detector frequency response at -160 khz. 155

162 such that harmonics of one FSK tone generated by the limiting process do not fall in the sidelobes of a detector centered at another FSK tone. This will happen with the conventional, equally-spaced 4-FSK offsets of -3 f, - f, + f, and +3 f, since the fifth harmonic of, say, - f will induce an unacceptably large response in the largest sidelobe of the correlator centered at +3 f. However, with offsets of +2 f, + f, - f, and -2 f, at the frequency where the response of one correlator is at a peak, the sidelobes of all the others are at a null. This minimizes the undesirable interaction. A stand-alone prototype of this correlating detector including digital phaselock loops to track symbol timing and frequency hopping was implemented and evaluated prior to the integration of the final receiver [13]. The total power dissipation of the digital blocks at 3V is 4.5 mw. The detector takes a one-bit estimate of the received signal from the output of the limiting amplifiers, and constructs eight-bit correlation coefficients over each symbol which are used for all the other functions. No A/D converter is thus required. However, because of the one-bit approximation, there is an implementation loss in detection sensitivity of 1.5 db from ideal [13]. In summary, there are three sets of progressively narrower filters in this receiver (Figure 4.14). The detector is the narrowest, and it sets the overall noise bandwidth used in minimum detectable signal calculations in the next section. 156

163 RF BPF LNA LPF Limiter I&Q LO RSSI FSK Detector 26 MHz 230kHz -40 db 915 MHz -50 db 320kHz khz Figure 4.14 Progressive filtering in receiver. 4.4 Stand-alone Receiver Prototype A stand-alone receiver was fabricated prior to the integration of final transceiver. The chip photo of the stand-alone chip is shown in Figure It is apparent from the chip photo that the passive components, 400 pf capacitor arrays for 2 LPF s, and inductors in the LNA take up most of the chip area. The chip was bonded in a 84-lead ceramic QFP from Mini-Systems. The bonding diagram is shown in Figure The paddle was grounded by 28 bondwires to provide a good ground plane underneath the chip, and the RF and LO inputs were separated by grounded leads to reduce signal coupling. The LO was supplied from an off-chip frequency synthesizer (HP8657B) which was quadrature-split by a 90 phase splitter (M/A-COM JH-140) on the test board. Two 180 phase splitters (M/A- COM HH-128) further converted the single-ended quadrature LO into differential 157

164 6.0 mm I 4.25 mm Q RF Front-end SC LPF Limiter + RSSI Figure 4.15 Stand-alone receiver prototype chip photo. signals. An on-chip poly-phase filter [73] further aligns the LO signals. Figure 4.17 shows the 4-layer FR-4 test board of the receiver. There were two major problems found in the stand-alone receiver: the minimum detectable was much higher than expected, and there was a significant amount of LO feed-through. Figure 4.18 shows the noise and gain distribution in the stand-alone receiver. Quadrature downconversion bifurcates the signal into two channels after RF amplification in the LNA. The noise is uncorrelated in the mixers and subsequent blocks in each channel, and it adds to quadrature phases of the 158

165 GND 62 GND 61 GND 60 CAP1 59 ISOURCE 58 GND 57 OUT_buf_n 56 GND 55 OUT_buf_P 54 RSSI2 53 RSSI2 52 OUT_buf_P 51 GND 50 OUT_buf_n 49 GND 48 ISOURCE 47 CAP1 46 GND 45 GND 44 GND 43 GND Mix Vdd Mix Vdd I Ib LNA Vdd RF in LNA Bias 270 GND 90 GND 180 GND 0 LNA Bias RF in LNA Vdd Qb Q Mix Vdd Mix Vdd GND GND GND GND GND GND DC Probe DC Probe DC Probe DC Probe VCM Filter VDD Filter VDD CLKb GND CLK RSSI0 VDD GND GND CAP2 GND GND GND GND GND GND DC Probe DC Probe DC Probe DC Probe VCM Filter VDD Filter VDD CLKb GND CLK RSSI0 VDD GND GND CAP2 Figure 4.16 Bonding diagram of stand-alone receiver. downconverted signal. If the output voltages at the two channels sum at the detector, the rms noise voltage is 2x larger than the noise in one channel alone. However, the quadrature components of the signal also sum to a value 2x larger than in one channel. Thus, the combined SNR remains the same as single channel SNR. For the purposes of calculating receiver noise figure, therefore, the noise contribution of each building block is accounted for only once. Using the individual 159

166 Figure 4.17 Stand-alone receiver evaluation board. I-Ch LPF Limiter LNA LPF Limiter Q-Ch LNA+Mixer Voltage Gain = 22dB NF = 3.5 db SSB LPF Voltage Gain = 12 db Input Noise = 35 nv/ Hz Limiter Voltage Gain = 84 db NF = 40 nv/ Hz Figure 4.18 Gain distribution in the stand-alone receiver. 160

167 numbers for noise and gain in Figure 4.18 and equations (1.8), (1.11) of Section 1.4.1, the input-referred noise of the entire receiver was computed as: ( 1.01) (4.1) = nv Hz This translates to noise figure of 16.7 db in 50 Ω. Using equation (1.1), the MDS was estimated to be, MDS = log ( 80k) = 99.8 dbm. (4.2) However, the measured minimum detectable signal using the stand-alone 4-FSK detector was -81 dbm at 10-3 BER. Figure 4.19 shows the measured output noise Output Noise Power in dbm/hz khz Figure 4.19 Measured output noise of stand-alone receiver prototype, the dashed lines are error bounds. 161

168 spectrum of the receiver at the limiter outputs when the RF input is terminated in 50 Ω. The shape indicates that the noise is dominated by the channel select filter. Taking the average noise level of -42 dbm/hz in the 20k-200kHz band, and subtracting the filter and limiter gain of 12+84=96 db, the noise level at the input of the filter is 30 nv/ Hz, which is close to the simulated input-referred noise of the LPF. The discrepancy in measured MDS was caused by two reasons. First, the measured front-end gain (LNA and mixer) at the mixer outputs was only 12dB, thus raising the receiver noise figure to 26 db, and MDS to -90 dbm. The cause of the gain drop was unclear, it was speculated that the substrate resistance of the LNA reduced the gain. Figure 4.20 is the SPICE simulation of LNA gain, S 11, and NF with different substrate resistances. The substrate resistance influences both impedance matching and NF heavily, but not so much on the gain. Nevertheless, simulations show that a substrate resistance in the range of hundred s of ohms seems to match up with measurements of the stand-alone LNA better. Using equation (3.23), it would imply that the substrate area is in the neighborhood of 50x50 to 100x100 µm 2, which is the size of the overall area occupied by the interdigitated transistor (Figure 4.21). It is postulated that the fringing fields of each finger of the transistor have merged into one (Figure 4.22), and the substrate resistance is, ρl 10Ω-cm 10µm R = ---- =. (4.3) A = 67µm 46µm 324Ω 162

169 Vc 3V M µm 50 nh, 50Ω, 60 ff Substrate Resistance v n To Mixer 324Ω M1 300 µm M2 To Mixer 324Ω v n L bond C gs V g 4nH Off Chip C Pkg C pad 1pF 0.2pF 10nH 0Ω 324 Ω 3.33 kω Voltage Gain 3.33 kω 20log S11 324Ω 0Ω 3.33 kω 324Ω NF(dB) 0Ω Figure 4.20 LNA performance is influenced by the substrate resistance. 163

170 67x46µm 2 14µm Substrate Contacts Figure 4.21 Transistor layout of the LNA in the stand-alone receiver. Channel Area 67x46µm 2 Figure 4.22 Merging the fringing field lines of fingers into one, the substrate resistance of an interdigitated transistor is estimated by using the overall area occupied by the complete transistor. The second cause for the discrepancy between estimated and measured MDS was that the noise floor of the LPF was assumed to be flat, and the detector was assumed to integrate noise only in a 80 khz BW. In reality however, the 4-FSK 164

171 db Noise Integrated by 80 khz Detector LPF output noise dbv -140 Input referred noise khz Figure 4.23 Filter output noise of the revised LPF and 4-FSK detector response. Noise peaking at the band edge must be reduced, otherwise it will be detected by the sidelobes of the 4-FSK detector. detector s sidelobes will integrate noise energy in the band-transition edge where the noise floor peaks (Figure 4.23). When the simulated output noise of the filter is multiplied by the measured frequency response of the 4-FSK detector and summed over -300kHz to +300 khz, together with the measured 12 db front-end gain, the minimum detectable signal was raised to -81 dbm, exactly the same as the measured value. The other problem in the stand-alone receiver was that the LO signal leaked to the mixer output and it was subsampled by the 57 MHz clock of the LPF input Butterworth filter. That is, when 165

172 f LO 57 MHz N 200 khz, (4.4) where N is an integer, a spur appears in the output. The spur was as high as -10 dbc of the main tone. These problems lead to the several modifications on the final receiver, which will be presented in the next section. 4.5 Final Receiver on Integrated Transceiver The blocks must be redesigned, or intermediate gain stages must be strategically placed to improve the cascaded performance in the final transceiver. For example, the channel-select filter is only preceded by the 20 db voltage conversion gain of the LNA and mixer, its 40 nv/ Hz input noise leads to a 17 db receiver NF, which is unacceptably high. The reason why the receiver prototype had only 20 db of front-end gain was that the IIP3 of the filter was calculated using inband interferers, thus under-estimating its IIP3 performance. When it was realized that the interferers ought to be defined as adjacent channel tones, i.e. in the stopband of the filter, the front-end and filter gain could be increased dramatically Modifications in the Baseband Circuits Since the filter's own noise can only be lowered at a quadratic expense of current drain and chip area, a better solution is to insert a baseband amplifier after the downconversion mixer, to lower the contribution of filter noise by the buffer gain. In addition, a simple RC filter can be placed after the buffer to remove the LO 166

173 leakage. The filter was modified to have a gain distribution of 4x,2x,2x,1x in the 4 biquads respectively instead of the 4x,1x,1x,1x gain assignment in the stand-alone receiver. This new arrangement places more gain in the Butterworth and the low-q biquads and reduces the noise peaking at the filter transition due to the high-q biquad. The baseband buffer uses two common-source PFET s in balanced mode as a linear transconductor, and polysilicon resistor loads for linearity and low flicker noise. Figure 4.24 shows the schematic diagram of the baseband buffer. The gate area of the NFET current sources is purposely enlarged to lower flicker noise. The differentially connected 30 pf on-chip capacitor provides a 3-dB bandwidth of 1 MHz with the 2.9 KΩ load resistors. Thus it provides approximately 60 db of rejection at 900 MHz and effectively removes LO leakage. The simulated From mixer 30 pf 320/1 µm To LPF 2.9 kω Pad 320/4 µm 60 pf Figure 4.24 Baseband buffer between the mixer and channel-select filter. 167

174 Figure 4.25 Simulated frequency response of baseband buffer. frequency response of this buffer is shown in Figure The rationale for the 14 db gain is shown later. The RC low-pass filter will also prevent the front-end noise from being aliased by the switched-capacitor filter whose prefilter is sampling at 57.2 MHz. Pads are connected to the outputs for monitoring the front-end (LNA, mixer and buffer) performance of the integrated transceiver. Since the flicker noise can vary to an order of magnitude from process to process [74], the NFET current source is designed such that the flicker noise power is more than an order of magnitude lower than the (8/3)KT/g m thermal noise at the 4-FSK tone locations. Figure 4.26 shows the input-referred flicker noise and 168

175 10-13 Input-Referred Noise Voltage Squared (V 2 ) Flicker Thermal k k 160k 10 6 Hz Figure 4.26 Flicker noise estimate of a 320/4 NFET with g m =1.7 ms (found to be incorrect). thermal noise voltage squared of a 320/4 NMOS generated by a MATLAB script. The flicker noise is estimated by scaling the Fabricator A data in [75] to HPCMOS34 gate oxide thickness of 200 Å. The flicker noise corner is at 3.6 khz when the FET is biased at g m = 1.7 ms. PMOS typically has 10 times less flicker noise (power) than an NMOS [75], thus the 320/1 PMOS input pair is equivalent to the gate area of a 3200/1 NMOS, and its flicker noise power would be 2.5 times lower than that of the NFET shown. However, a mistake was later found in the. Program provided by Jacob Rael. 169

176 10-12 Input-Referred Noise Voltage Squared (V 2 ) Thermal Flicker k 403.5k k Hz Figure 4.27 Revised estimate of a 320/4 NFET biased at g m =1.7 ms. program and the actual corner is at 403 khz (Figure 4.27). The AF and KF parameters in the flicker noise expression, ṽ n 2 = KF WLC ox f AF (4.5) are extracted to be and 5.267e-25 V 2 F respectively. It is shown later in the test results that this mistake does not cause any detrimental effects Modifications in the RF Circuits Realizing that the substrate resistance can have a strong influence on the 170

177 On-Chip Suspended Inductors 30 nh, 30Ω, 60fF To I&Q Mixers v n 500 µm M2 To I&Q Mixers 165Ω v n L bond C gs V g 4nH Off-Chip C Pkg C pad 2.3pF 0.67 pf 0.5pF 20nH Figure 4.28 LNA for in the final transceiver including package parasitics. LNA performance from previous SPICE simulations (Figure 4.20), some efforts are made to lower the value. Since exactly how the substrate resistance varies with device size and layout is not known, these design choices are rough estimates. First, the widths of the LNA devices for the final transceiver are enlarged to 500 µm (Figure 4.28), the total substrate area occupied by the transistor is now 112x54 µm 2, and the substrate resistance is estimated to be, (from equation (3.23) and Figure 4.22) ρl 10Ω-cm 10µm R = ---- =. (4.6) A = 112µm 54µm 165Ω Second, a ring of substrate contacts are placed as close as 5-10 µm away from the transistor channel, these contacts along with the P+ substrate 10 µm away from the bottom of the transistor together should further reduce the substrate resistance 171

178 7µm Reduced from 14µm (Fig 4.21) Substrate Contacts 112x54µm 2 Figure 4.29 LNA transistor layout /1µm transistors in parallel to reduce gate resistance. Substrate contacts are placed 5-10 µm away from the channel. (Figure 4.29). Figure 4.30 shows the SPICE simulated performance of the final LNA, the effect of including a substrate resistance is shown. Due to a reduction in r ds, load inductance, and the presence of substrate resistances, the simulated gain is reduced to 20 db. Thermal noise from the substrate resistance adds to the total NF through g mb, the body-effect transconductance [22]. From measurements performed later, it is found that 100Ω of substrate resistance fits measurements better. The further reduction in substrate resistance can be attributed to the presence of the ring of substrate contacts. Figure 4.31 is the IIP3 simulation of the LNA, it predicts an IIP3 of, 72.6 LNA IIP3 = ( 24) = dbm. (4.7) 2 172

179 0Ω 100Ω 165Ω LNA Av(dB) 100Ω 0Ω 165Ω 20log S11 Im(In) 165Ω 100Ω 0Ω 165Ω 100Ω 0Ω Re(In) 165Ω 100Ω NF(dB) 0Ω Figure 4.30 Simulated LNA performance with different substrate resistances. Vg=1.15 V drawing 4mA each, the g m is 16.3 ms. The mixer switching devices are reduced to 40 µm each in order to be driven by the on-chip LO buffer [48], the schematic diagram is shown in Figure The PFET load resistors might modulate the signal current with flicker noise, so they are replaced by polysilicon resistors. The IIP3 simulation of the mixer is shown in Figure The mixer IIP3 is, Mixer IIP3 IM3 (dbc) = Input Level at LNA + LNA gain 2 48 = ( 24) + 20 = +20 dbm 2 (4.8) Dynamic Range Planning It is generally prudent to add gain sparingly prior to channel-select filtering, 173

180 72.6 dbc Figure 4.31 IIP3 simulation of LNA. Incident signal level is 20 mv amp = -24 dbm. M7 M8 g m7 320µm R L 900 Ω Poly-R M3 M4 LO- 40µm M6 LO+ From LNA g m1 40µm M2 Figure 4.32 Downconversion mixer schematic diagram. 174

181 48 dbc Figure 4.33 IIP3 simulation of the mixer. Signal level at mixer input is -4 dbm. Differential amplitude of LO signal is 1.8V. otherwise small blocking signals may create in-band intermodulation products. The gain should be enough to enable the desired minimum signal to overcome noise. With too much gain, the cascade intercept point falls proportionally, while the receiver noise figure flattens out to a constant value set by the LNA, and the overall dynamic range suffers. The receiver overall noise figure, IIP3, MDS, and SFDR trade-offs are illustrated as a function of buffer gain in Figure 4.34 and Figure It is assumed in these calculations that the mixer buffer's load resistors set the gain, and that its input-referred noise and output clipping level remain constant. A gain of 14 db was chosen to optimize cascade NF against SFDR. However, the receiver 175

182 Noise Figure (db) Cascaded IIP3 (dbm) Buffer Gain (db) Figure 4.34 NF and IIP3 trade-off. 14 db gain was chosen. may be customized in other ways: for instance, with more gain to lower NF at a known expense of IIP3. The cascade effect of the various blocks is seen in a signal level diagram (Figure 4.36). Using the individual numbers for noise and gain in Figure 4.36 and equations (1.8), (1.11) of Section 1.4.1, the input-referred noise of the entire receiver is predicted as: ( 1.01) ,(4.9) = = nv Hz which induces a noise figure of 8.6 db in 50 Ω. The filter noise, the third term in the sum, still dominates. From equation (1.33), the mixer with its buffer limit the 176

183 MDS (dbm) Buffer Gain (db) Figure 4.35 MDS and SFDR trade-off. SFDR (db) +30 dbm Cascade IIP3 = -8 dbm Cascade SFDR = 62 db Cascade NF = 8.6 db dbm LNA 80 db 3.4 db 20 db Mixer+Buffer 73 db 20 db +15 dbm 15 db ( khz) 14 db 14 db Filter 66 db 24 db Limiter 40 db 40 db 84 db 122 db Baseband Gain Figure 4.36 Signal level plan in receiver. Noise figures of blocks after LNA include the effect described in equation (1.11). 177

184 cascade third-order intercept point to about -8 dbm. As the signal advances down the cascade, it can tolerate blocks with higher input noise, but up to and including the channel-select filter each block must handle a progressively larger signal before it clips. To enable comparison with publications on receiver building blocks, this level diagram specifies the input noise voltage of the blocks (measured on stand-alone prototypes) as the power spectral density across a hypothetical 50 Ω reference resistor, and, similarly, the input intercept point in dbm. The dynamic range of each circuit block and the overall receiver dynamic range is summarized in detail in Table 4.1. LNA Mixer and Buffer LPF Limiter Total Voltage Gain (db) IIP3 (dbm) (dbvrms) 1-dB Comp. (dbm) (dbvrms) NF (db) Noise Floor (dbm) MDS (dbm) (dbvrms) BDR (db) SFDR (db) Table 4.1 Receiver dynamic range breakdown. 178

185 Second-order distortion in the baseband circuits of a direct-conversion receiver, where the signal is largest, detects the envelope of out-of-band amplitudemodulated interferers to create spurious tones in the filter passband [8]. This is specified by the extrapolated second-order intercept point, IIP2. Ideally, the IIP2 is infinite in a fully balanced receiver, but it is finite in practice because of element mismatches. Systematic mismatches arise from asymmetries in layout, and random mismatches from statistical fluctuations in FET s and passive components. These cannot be easily predicted. The IIP2 is found by measurements on the finished receiver. Surprisingly though, the LPF is simulated to have a finite IIP2 even when it is without any element mismatches. This is shown in the next chapter. The final receiver SFDR is about 62 db, limited by the 66 db SFDR of the filter. It is 18 db lower than the LNA SFDR, and 13 db lower than the SFDR of the stand-alone front-end, comprising the LNA and mixer (Section 3.4). The discrepancy in dynamic range of isolated building blocks and the complete receiver cautions against simple extrapolation of the latter's performance from measurements on the former. It also demonstrates that baseband building blocks, however seemingly mundane, must be designed with great care if they are not to severely limit the total receiver dynamic range. Figure 4.37 is the layout of the LNA, I & Q channel mixers and buffers in the final receiver. The LO lines from the RF buffer are suspended along with the inductors to reduce the capacitive loading on the LO buffer. The LNA input pads 179

186 30 pf 30 pf Suspended 3000 µm LO LNA shielded input pads Figure 4.37 Front-end layout in the final transceiver. Boxed area contains half of the LNA and single channel mixer and buffer. are shielded from the substrate by grounded metal-1. The two sets of 30 pf capacitors are connected to the outputs of the mixer buffers. The boxed area is enlarged in Figure 4.38 to show the details of the mixer layout. Grounded substrate contacts are used liberally to surround RF transistors in an effort to reduce substrate resistance and cross-talk. 180

187 460 µm 510 µm LNA Substrate Contacts Figure 4.38 Enlarged view of front-end layout. 181

188 Chapter 5 Receiver Experimental Results 5.1 Prototype Assembly The receiver is integrated with the transmitter as shown in Figure 5.1. The IC was fabricated in a double-metal, single-poly 1-µm N-well epi-cmos process offered by MOSIS (HPCMOS34/AMOSI). The receiver occupies the right side of the transceiver. The arrangement of the low-pass filter and limiter remains unchanged from the stand-alone receiver, the RF front-end is rotated ninety degrees in order to move the mixer closer to the local oscillator signal lines. The chip was then etched by XeF 2 using procedures outlined in Chapter 2 to suspend the twelve on-chip inductors and LO interconnects over the substrate. In order to unify the etch-time, all inductors occupy the same amount of substrate area despite their 182

189 10.5 mm 7.3 mm Figure 5.1 Transceiver die photograph. differences in inductance values. The etched transceiver chip is shown in Figure 5.2. The silicon surface of each smoothly-etched hemisphere is a miniature concave mirror which reflects light passing through the transparent oxy-nitride dielectric, and gives the optical illusion of shiny balls on top of the inductor. The cluster of individual cavities under each inductor coalesce into a large pit as deep as 150 µm. The curvy patterns are chemical residues from the etching process. These pits are useful in another way: they lower the substrate capacitance under long interconnects carrying 900 MHz signals. A case in point is the set of four lines, each 3 mm long, which connect the balanced quadrature frequency-hopped signals from the RF buffer in the transmitter section to the downconversion mixer in the receiver. Lines of minimum width are limited by distributed RC effects to a low cutoff 183

190 Figure 5.2 Transceiver after XeF 2 etching. The pits underneath inductors appear to be solder blobs due to reflection. frequency. In wider lines, the large capacitance to substrate heavily loads the RF buffer. The solution is to place via holes between pairs of these lines, through which pits form under the lines (Figure 5.3). With the substrate capacitance now gone, the lines are widened to lower their series resistance that otherwise damps the tuned loads of the RF buffers. More discussion on the suspended interconnects can be found in [48]. 5.2 Device Package and Evaluation Board The chip is attached with conductive silver epoxy to a 148-lead gullwing flatpack with a metallic cavity from Mini-Systems, Inc. (MSI 25W148M-2). The 184

191 interconnect Figure 5.3 Enlarged view of boxed area in Figure 5.2 showing pits under inductor and long RF interconnects. bonded chip in the package is shown in Figure 5.4. Ground bondwires directly attach to the metallized paddle in the cavity, while signal and supply bondwires span an average length of about 5 mm. All analog circuits are balanced, and for circuits operating at a constant current, bondwire inductance is of no concern. For differential circuits not operating at constant current, only the second-harmonic Figure 5.4 Transceiver mounted in a 148-lead flatpack from MSI. 185

192 flows through the bondwire inductance to produce a common-mode fluctuation, which the next balanced stage rejects. At the RF signal pads, the bondwire inductance is absorbed into the matching network (Figure 4.28). The metallic paddle in the package cavity is used as a ground plane for the chip. Most unused leads are bonded to the base metal and connected to ground on the test board. The ground pads of the chip are bonded directly to the base metal to minimize bond wire length. This can be seen in the bonding diagram, Figure 5.5. All the leads adjacent to RF leads are also grounded to provide isolation. The base metal is thus grounded by a total of thirty-one leads and bond wires. A four-layer printed circuit board using FR-4 epoxy fiberglass dielectric material (ε r = 4.7) is fabricated for transceiver performance evaluation. 50 Ω microstrip lines are designed on the top layer of this board to convey RF signals. Wire lengths for differential signals are carefully matched to maintain phase balance. Figure 5.6 shows the test board. The single-ended RF signal is converted into differential signals by a MHz flatpack hybrid balun from M/A COM(HH-128). The balun contributes less than 1.5 db of loss and noise figure from 10 MHz to 1 GHz. Surface-mount chip inductors from Coil Craft are used for LNA matching. Low-inductance Tektronix probe sockets are installed for probing mixer outputs. End-launch SMA connectors are used for cable connections. Other than the one filter capacitor connected across the balanced lines in the DC feedback 186

193 loop of each limiting amplifier, no other filtering is necessary, nor is shielding called for. Compared to the multi-component transceivers found in many wireless devices produced over the past several years, this clearly shows a highly integrated transceiver simplifying assembly and testing Metallic Base Gnd Figure 5.5 Transceiver bonding diagram. The metallic cavity is used as a ground plane, 31 leads are used to ground the paddle. Lead 87 and 89 are LNA inputs, isolated by grounded leads 86, 88, and

194 900 MHz VCO Outputs Delay Matched LPF Clock Receiver Outputs DAC Clock DDFS Controls Matching Inductors 50Ω T-Lines Balun LNA Input Mixer Outputs Power Amp Output Figure 5.6 Transceiver mounted on the evaluation board. 188