BTA08, BTB08, T810 T835, T850 Datasheet

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1 BTA08, BTB08, T810 T835, T850 Datasheet Snubberless, logic level and standard 8 A Triacs A2 Features On-state rms current, I T(RMS) 8 A G Repetitive peak off-state voltage, V DRM / V RRM 600 V to 800 V A2 A1 Triggering gate current, I GT 5 to 50 ma Description TO-220AB G A2 A1 A2 TO-220AB Ins. G A2 A1 Available either in through-hole and surface-mount packages, these devices are suitable for general purpose AC switching. They can be used as an ON/OFF function in applications such as static relays, heating regulation, induction motor starting circuits or for phase control operation in light dimmers and motor speed controllers, etc. A2 IPAK D²PAK G A2 A1 A2 G A1 A2 DPAK A2 G A1 The Snubberless versions (BTA, BTB08_xxxxW and T8 series) are specially recommended for use on inductive loads, thanks to their high commutation performance. Logic level versions are designed to interface directly with low power drivers such as Microcontrollers. By using an internal ceramic pad, the BTA series provide voltage insulated tab (rated at 2500 V RMS ) in compliance with UL standards (file ref.: E81734). Product status link BTA08 BTB08 T810 T835 T850 DS Rev 14 - May 2018 For further information contact your local STMicroelectronics sales office.

2 Characteristics 1 Characteristics Table 1. Absolute maximum ratings (T j = 25 C unless otherwise stated) Symbol Parameter Value Unit I T(RMS) RMS on-state current (full sine wave) IPAK, DPAK,TO-220AB, D²PAK T c = 110 C TO-220AB Ins. T c = 100 C 8 A I TSM Non repetitive surge peak on-state current (full cycle, T j initial = 25 C) f = 50 Hz t = 20 ms 80 f = 60 Hz t p = 16.7 ms 84 A I 2 t I 2 t value for fusing t p = 10 ms 36 A 2 s dl/dt Critical rate of rise of on-state current I G = 2 x I GT, tr 100 ns f = 120 Hz T j = 125 C 50 A/µs I GM Peak gate current t p = 20 µs T j = 125 C 4 A P G(AV) Average gate power dissipation T j = 125 C 1 W T stg Storage junction temperature range -40 to +150 C T j Operating junction temperature range -40 to +125 C Table 2. Electrical characteristics (T j = 25 C, unless otherwise specified) Snubberless and logic level (3 quadrants) Symbol Parameter Quadrant T8 BTA08/BTB TW SW CW BW Unit I GT (1) I - II - III Max ma V D = 12 V, R L = 30 Ω V GT I - II - III Max. 1.2 V V GD V D = V DRM, R L = 3.3 kω, T j = 125 C I - II - III Min. 0.2 V I (2) H I T = 100 ma I - II - III Max ma I L I G = 1.2 x I GT I - III Max II Max ma dv/dt (2) V D = 67% V DRM, gate open, T j = 125 C Max V/µs (dv/dt)c = 0.1 V/µs, T j = 125 C Min (dl/dt)c (2) (dv/dt)c = 10 V/µs, T j = 125 C Min Without snubber, T j = 125 C Min A/ms 1. Minimum I GT is guaranteed at 5 % of I GT max. 2. For both polarities of A2 referenced to A1 DS Rev 14 page 2/21

3 Characteristics Table 3. Standard (4 quadrants) Symbol Parameter Quadrant BTA08/BTB08 C B Unit I GT (1) V D = 12 V, R L = 33 Ω I - II - III Max. IV ma V GT All Max. 1.3 V V GD V D = V DRM, R L = 33 Ω, T j = 125 C All Min. 0.2 V I H (2) I T = 500 ma I - II - III Max ma I L I G = 1.2 I GT I - III - IV Max II ma dv/dt (2) V D = 67 % V DRM gate open, T j = 125 C Min V/µs (dv/dt)c (2) (di/dt)c = 3.5 A/ms, T j = 125 C Min A/ms 1. Minimum I GT is guaranteed at 5 % of I GT max. 2. For both polarities of A2 referenced to A1 Table 4. Static electrical characteristics Symbol Test conditions Value Unit V (1) TM I TM = 11 A, t p = 380 µs T j = 25 C Max V V (1) TO threshold on-state voltage T j = 125 C Max V R (1) D Dynamic resistance T j = 125 C Max. 50 mω I DRM I RRM V DRM = V RRM T j = 25 C Max. 5 µa T j = 125 C Max. 1 ma 1. For both polarities of A2 referenced to A1 Table 5. Thermal resistance Symbol Parameter Value Unit R th(j-c) Max. junction to case thermal resistance (AC) IPAK / D2PAK / DPAK / TO-220AB 1.6 TO-220AB Insulated 2.5 C/W R th(j-a) Junction to ambient (typ.) Junction to ambient (typ.) S = 2 cm² (1) D²PAK 45 S = 1 cm² (1) DPAK 70 TO-220AB / TO-220AB Insulated 60 IPAK 100 C/W 1. S = Copper surface under tab. DS Rev 14 page 3/21

4 Characteristics (curves) 1.1 Characteristics (curves) Figure 1. Maximum power dissipation versus on-state RMS current (full cycle) Figure 2. RMS on-state current versus temperature (full cycle) P(W) I T(RMS) (A) I T(RMS) (A) 10 9 BTB/T8 8 7 BTA T c ( C) Figure 3. RMS on-state current versus ambient temperature (full cycle) Figure 4. Relative variation of thermal impedance versus pulse duration I T(RMS) (A) K = [Z th /R th ] D²PAK (S = 1 cm²) Printed circuit board FR4, copper thickness: 35 µm 1E+0 1E-1 Zth(j-c) DPAK/IPAK Zth(j-a) DPAK (S = 0.5 cm²) 1E-2 TO-220AB/D²PAK Zth(j-a) 0.5 T c ( C) E-3 t p (s) 1E-3 1E-2 1E-1 1E+0 1E+1 1E+2 5E+2 DS Rev 14 page 4/21

Characteristics (curves) Figure 5. On-state characteristics (maximum values) Figure 6. Surge peak on-state current versus number of cycles 100 I TM (A) Tj max. Vto = 0.85 V Rd = 50 mω Tj = Tj max.

5 Characteristics (curves) Figure 5. On-state characteristics (maximum values) Figure 6. Surge peak on-state current versus number of cycles 100 I TM (A) Tj max. Vto = 0.85 V Rd = 50 mω Tj = Tj max I TSM (A) Non repetitive T j initial = 25 C t = ms One cycle 10 Tj = 25 C Repetitive T C = 110 C 1 V TM (V) Number of cycles Figure 7. Non repetitive surge peak on-state current for a sinusoidal pulse (t p < 10 ms) Figure 8. Relative variation of gate trigger current 1000 I TSM (A) Tj initial=25 C I GT,I H,I L [Tj] / I GT,I H,I L [Tj = 25 C] 2.5 Holding current and latching current versus junction temperature (typical values) 2.0 I GT di/dt limitation: 50A/µs ITSM I H and I L α 0.5 t p(ms) T j ( C) Figure 9. Relative variation of critical rate of decrease of main current versus (dv/dt)c (typical values) Figure 10. Relative variation of critical rate of decrease of main current versus (dv/dt)c (typical values) (dl/dt)c [(dv/dt)c / specified (dl/dt)c TW Snubberless and logic level types T835/T850/CW/SW/BW T810/SW (dv/dt)c (V/µs) (dl/dt)c [(dv/dt)c] / specified (dl/dt)c 2.0 Standard types 1.8 C B (dv/dt)c (V/µs) DS Rev 14 page 5/21

6 Characteristics (curves) Figure 11. Relative variation of critical rate of decrease of main current versus junction temperature Figure 12. DPAK and D2PAK thermal resistance junction to ambient versus copper surface under tab (dl/dt)c [Tj] / [Tj specified] Tj( C) R th(j-a) ( C/W) 100 Printed circuit board FR4, copper thickness: 35 µm DPAK D²PAK S(cm²) DS Rev 14 page 6/21

7 Package information 2 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: ECOPACK is an ST trademark. DS Rev 14 page 7/21

8 DPAK package information 2.1 [Package name] package information Epoxy meets UL94, V0 Lead-free package Recommended torque: 0.4 to 0.6 N m Figure 13. DPAK package outline A E b4 c2 H D L2 A1 E1 e L4 b c e1 L V2 A2 D1 DS Rev 14 page 8/21

9 DPAK package information Table 6. DPAK package mechanical data Dimensions Ref. Millimeters Inches (1) Min. Typ. Max. Min. Typ. Max. A A A b b c c D D E E e e H L L L V Dimensions in inches are given for reference only Note: This package drawing may slightly differ from the physical package. However, all the specified dimensions are guaranteed. Figure 14. DPAK recommended footprint (dimensions are in mm) A The device must be positioned within B 0.05 AB 1.6 DS Rev 14 page 9/21

10 IPAK package information 2.2 IPAK package information Figure 15. IPAK package outline L2 E b4 V1 A c2 D L1 e b2 L A1 H B5 e1 b c Note: This package drawing may slightly differ from the physical package. However, all the specified dimensions are guaranteed. DS Rev 14 page 10/21

11 IPAK package information Table 7. IPAK package mechanical data Dimensions Ref. Millimeters Inches (1) Min. Typ. Max. Min. Typ. Max. A A b b b B c c D E e e H L L L V Inch dimensions are for reference only. DS Rev 14 page 11/21

12 TO-220AB Insulated package information 2.3 TO-220AB Insulated package information Figure 16. TO-220AB Insulated package outline B C Resin gate 0.5 mm max. protusion (1) I L b2 F A I4 l3 a1 c2 l2 a2 e b1 Resin gate 0.5 mm max. protusion (1) (1)Resin gate position accepted in one of the two positions or in the symmetrical opposites. M c1 DS Rev 14 page 12/21

13 TO-220AB Insulated package information Figure 17. TO-220AB Insulated package outline Table 8. TO-220AB Insulated package mechanical data Dimensions Ref. Millimeters Inches Min. Typ. Max. Min. Typ. Max. A a a B b b C c c e F I L I I I M Inch dimensions are for reference only. DS Rev 14 page 13/21

14 D²PAK package information 2.4 D²PAK package information Figure 18. D²PAK package outline E L2 c2 A E1 E2 L3 D2 H D D1 b2 b e G Resin gate 0.5 mm max. protrusion(1) A1 A2 A3 L V2 c R Gauge Plane (1) Resin gate position accepted in one of the two positions or in the symmetrical opposites DS Rev 14 page 14/21

15 D²PAK package information Table 9. D²PAK package mechanical data Dimensions Ref. Millimeters Inches Min. Typ. Max. Min. Typ. Max. A A A A b b c c D D D e E E E G H L L L R V Dimensions in inches are given for reference only DS Rev 14 page 15/21

16 D²PAK package information Figure 19. D²PAK recommended footprint (dimensions are in mm) DS Rev 14 page 16/21

17 Ordering information 3 Ordering information Figure 20. Ordering information scheme (BTA08 and BTB08 series) BT A BW (RG) Triac Insulation A = Insulated B = Non-insulated Current 08 = 8A Voltage 600 = 600 V 800 = 800 V Sensitivity and type B = 50 ma C = 25 ma standard SW = 10 ma logic level Packing mode RG = Tube BW = 50 ma Snubberless CW = 35 ma Snubberless TW = 5 ma logic level Figure 21. Ordering information scheme (T8 series) T B (-TR) Triac series Current 08 = 8A Sensitivity 10 = 10 ma 35 = 35 ma 50 = 50 ma Voltage 600 = 600 V 800 = 800 V Package B = DPAK H = IPAK G = D²PAK Packing mode Blank = Tube TR = Tape and reel DS Rev 14 page 17/21

18 Ordering information Table 10. Product selector Part Number Voltage (xxx) Sensitivity Type Package T810-xxxB X X 10 ma Logic Level DPAK T835-xxxH X 35 ma Snubberless IPAK T810-xxxG X 10 ma Logic Level D 2 PAK T835-xxxG X X 35 ma Snubberless D 2 PAK T850-xxxG X X 50 ma Snubberless D 2 PAK BTA08-xxxS X 10 ma Logic Level TO-220AB Ins. BTA08-xxxC X X 35 ma Standard TO-220AB Ins. BTA08-xxxB X 50 ma Standard TO-220AB Ins. BTA08-xxxTW X 5 ma Logic Level TO-220AB Ins. BTA08-xxxSW X 10 ma Logic Level TO-220AB Ins. BTA08-xxxCW X 35 ma Snubberless TO-220AB Ins. BTA08-xxxBW X X 50 ma Snubberless TO-220AB Ins. BTB08-xxxS X 10 ma Logic Level TO-220AB BTB08-xxxC X 35 ma Standard TO-220AB BTB08-xxxB X 50 ma Standard TO-220AB BTB08-xxxTW X X 5 ma Logic Level TO-220AB BTB08-xxxSW X 10 ma Logic Level TO-220AB BTB08-xxxCW X X 35 ma Snubberless TO-220AB BTB08-xxxBW X 50 ma Snubberless TO-220AB DS Rev 14 page 18/21

19 Ordering information Table 11. Ordering information Order code Marking Package Weight Base qty. Delivery mode T B T T B T Tube T B T T B-TR T DPAK 0.30 T B-TR T T B-TR T Tape&Reel 13" T B-TR T T H T IPAK Tube T G T835-8G T850-6G T850-8G T G T835-8G T850-6G T850-8G 50 Tube T G-TR T G-TR T G T G D 2 PAK 1.50 T835-8G-TR T850-6G-TR T850-8G-TR BTA08-600SRG BTA08-600BRG BTA08-600CRG BTA08-800CRG T835-8G T850-6G T850-8G BTA08-600S BTA08-600B BTA08-600C BTA08-800C 1000 Tape&Reel 13" BTA08-600BWRG BTA08-600CWRG BTA08-600SWRG BTA08-600TWRG BTA08-600BW BTA08-600CW BTA08-600SW BTA08-600TW TO-220AB Ins. BTA08-800BWRG BTB08-600BRG BTB08-600CRG BTB08-600SRG BTB08-600BWRG BTA08-800BW BTB08-600B BTB08-600C BTB08-600S BTB08-600BW Tube BTB08-600CWRG BTB08-600SWRG BTB08-600TWRG BTB08-800CWRG BTB08-800TWRG BTB08-600CW BTB08-600SW BTB08-600TW BTB08-800CW BTB08-800TW TO-220AB DS Rev 14 page 19/21

20 Table 12. Document revision history Date Revision Changes Apr A Last update. 13-Feb TO-220AB delivery mode changed from bulk to tube. ECOPACK statement added. 10-Mar Updated ECOPACK statement and Figure Jun Updated DPAK and IPAK package information and reformatted to current standard. 07-Nov Updated Table 1 and reformatted to current standard. 06-Jan Updated Figure 20: "Ordering information scheme (T8 series)", Table 10: "Product selector" and Table 11: "Ordering information". 09-Feb Added T850 package information. 24-Apr Mar Updated Figure 6.. Minor text changes to improve readability. Updated Table 2. Electrical characteristics (Tj = 25 C, unless otherwise specified) Snubberless and logic level (3 quadrants), cover image, Figure 9. Relative variation of critical rate of decrease of main current versus (dv/dt)c (typical values) and Figure 21. Ordering information scheme (T8 series). 14-May Updated product status links. DS Rev 14 page 20/21

21 IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ( ST ) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document STMicroelectronics All rights reserved DS Rev 14 page 21/21

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