Polyphase based Wideband Digital SSB Converter of CDAS. L. Chen; X.Z. Zhang; Y. J. Wu; R.J.Zhu

Size: px
Start display at page:

Download "Polyphase based Wideband Digital SSB Converter of CDAS. L. Chen; X.Z. Zhang; Y. J. Wu; R.J.Zhu"

Transcription

1 Polyphase based Wideband Digital SSB Converter of CDAS L. Chen; X.Z. Zhang; Y. J. Wu; R.J.Zhu

2 Abstract CDAS (Chinese VLBI Data Acquisition System) has been developed in Shanghai astronomical Observatory since the beginning of year During the last few years, we have developed wideband Digital SSB Converter based on poly-phase filter-banks. The digital SSB Converter segments each IF into 2 n to USB and LSB channels. adjacent frequencies The experiments was done on the CDAS of 1U board s size.

3 Introduction THE ARCHITECTURES AND ARITHMETIC OF A WIDE BAND DIGITAL ADJACENT SSB CONVERTER (1) Channelization (a) ωk = 2π k /K for even arrangement (b) ωk = 2π k/k+π /K for odd arrangement

4 (2) Low-pass filter banks (a)the frequency characteristics of an ideal low-pass filter (b)the frequency characteristics of an practical lowpass filter The practical low-pass filter has transition bandwidth. The band-width of the filter output signal in each channel is 2π/D, so it is possible to perform down sampling by factor D on the output.

5 (3) The polyphase architecture for complex signal with even arrangement and noncritical sampling 2π kp 2π j j km K 1 ' y (m) = [ s( md p) * h ( m) ] e K }e F k p= 0 2π j km ' = IDFT[ s( md p) * h ( m) ] e F p p Where: D: decimator p K ' h( l ) p 0 1,, K DF l h( ), p F 1 Digital base-band converter architecture when,k=fd

6 If F = 2, e j 2π km F = j πkm e Digital base-band converter architecture: e jπkm = 1 for k even m ( 1) for k odd Thus, after channelization by the poly-phase filters and IFFT, the data rate of signal yk (m) has been reduced to 1/D of that of the input signal s(n).the prototype of a low-pass filter h p (m) has the bandwidth B = 1/(2D). K is the number of output channels, the output of 0-th channel and K/2-th channel are real, the others are complex. For real input signals, half of the channels are redundant.

7 (4) Digital adjacent SSB base-band converter based on the decimation structure of a real bandpass signal A real signal is symmetrical in the frequency domain. We denote its spectrum with X, X+ for positive frequencies and X- for negative frequencies. Time domain signal:

8 Architecture of the transformation from a real band pass signal to a real upper side band signal for F = 2, the data rata of yi (m) is Fs/D, where Fs stands for the data rate of the signal s(n). Its bandwidth is B = 1/2

9 SIMULATION AND VERIFICATION (1)Impulse response of prototype low-pass filter fpass : 0.9*32MHz fstop : 32MHz sample clock : 1024MHz Pass band ripple : 0.2dB stop-band attenuation :60dB Tap:1599

10 K=1024/32=32, decimation factor is D=16, a 32 point FFT, s( n ) = f f f f sin ( 2n ) + cos( 2nπ ) + sin ( 2nπ ) + cos( 2nπ ) + noi se F F F F s s s s Where: f0=20mhz, f1=60mhz, f2 =98Mhz, f3 =186Mhz, SNR=5dB,Fs=1024Mhz

11 (2)The input time series s(n) and its normalized spectrum and the relations with the polyphase filters:

12 Output signals generated by the new approach for the example of 0, 1st,2nd, 3rd,6th,7thUSB channels Magnitude (db) The output spectrum of the 0 channel Frequency (M Hz) The output spectrum of the 1st channel The output signal of each channel is real, with a bandwidth of 32MHz. The middle frequency of the k-th (k=1,2, 15) channel represents 16, 48, 80, 112, 144, 176, 208, 240, 272, 304, 336, 368, 400, 432, 464 MHz. The signal frequencies f0 to f3 are located in channels 1, 2, 3, 6. They appear there as 4, 12, 18, 10MHz base-band signals the corresponding base-band channel. Magnitude (db) Magnitude (db) Magnitude (db) Magnitude (db) Magnitude (db) Frequency (M Hz) The output spectrum of the 2nd channel Frequency (M Hz) The output spectrum of the 3rd channel Frequency (M Hz) The output spectrum of the 6th channel The output spectrum of the 7th channel Frequency (M Hz)

13 (3)The input signal with a 1024MHz clock is converted to an IF from 16 to 496MHz, into 15 real USB channels. Channel 0 is not useful due to aliasing. Since this channel is situated at the band-pass edge, it would be unusable anyway due to the shape of the analog band-pass filter ahead of ADC.

14 THE HARDWARE OF THE WIDEBAND DIGITAL SSB CONVERTER BASED ON POLY PHASE FILTERS The CDAS of 1U board 1U size signal process board

15 Control computer Xilinx FX60 IF Input 512MHz A/D Xilinx LX160-1 Xilinx LX160-2 Xilinx LX160-3 Xilinx LX160-4 MK5B/ VDIF Format 1024Mx8bit 16channel 32M 2bit VSI

16 A. The full spectrum of noise test:

17 B:Zero baseline test 50 X auto-corr AMP 60 XY co-corr AMP Amplitude(dB) Amplitude(dB) Amplitude(dB) freq(mhz) Y auto-corr AMP freq(mhz) pha(degree) freq(mhz) XY co-corr PHS freq(mhz) X: The correlation spectrum of one CDAS of 1U board's data Y: The correlation spectrum of another CDAS of 1U board's data XY: The cross correlation spectrum We could find that the phase spectrum is linear in each channel.

18 Thanks!

Multirate DSP, part 1: Upsampling and downsampling

Multirate DSP, part 1: Upsampling and downsampling Multirate DSP, part 1: Upsampling and downsampling Li Tan - April 21, 2008 Order this book today at www.elsevierdirect.com or by calling 1-800-545-2522 and receive an additional 20% discount. Use promotion

More information

Technology Development in Chinese VLBI Network

Technology Development in Chinese VLBI Network Technology Development in Chinese VLBI Network Xiuzhong ZHANG, Zhihan QIAN, Xiaoyu HONG, Zhiqiang SHEN and Team of CVN xzhang@shao.ac.cn Shanghai Astronomical Observatory, CAS 1st International VLBI Technology

More information

EE25266 ASIC/FPGA Chip Design. Designing a FIR Filter, FPGA in the Loop, Ethernet

EE25266 ASIC/FPGA Chip Design. Designing a FIR Filter, FPGA in the Loop, Ethernet EE25266 ASIC/FPGA Chip Design Mahdi Shabany Electrical Engineering Department Sharif University of Technology Assignment #8 Designing a FIR Filter, FPGA in the Loop, Ethernet Introduction In this lab,

More information

Team proposals are due tomorrow at 6PM Homework 4 is due next thur. Proposal presentations are next mon in 1311EECS.

Team proposals are due tomorrow at 6PM Homework 4 is due next thur. Proposal presentations are next mon in 1311EECS. Lecture 8 Today: Announcements: References: FIR filter design IIR filter design Filter roundoff and overflow sensitivity Team proposals are due tomorrow at 6PM Homework 4 is due next thur. Proposal presentations

More information

Design Of Multirate Linear Phase Decimation Filters For Oversampling Adcs

Design Of Multirate Linear Phase Decimation Filters For Oversampling Adcs Design Of Multirate Linear Phase Decimation Filters For Oversampling Adcs Phanendrababu H, ArvindChoubey Abstract:This brief presents the design of a audio pass band decimation filter for Delta-Sigma analog-to-digital

More information

FYS3240 PC-based instrumentation and microcontrollers. Signal sampling. Spring 2015 Lecture #5

FYS3240 PC-based instrumentation and microcontrollers. Signal sampling. Spring 2015 Lecture #5 FYS3240 PC-based instrumentation and microcontrollers Signal sampling Spring 2015 Lecture #5 Bekkeng, 29.1.2015 Content Aliasing Nyquist (Sampling) ADC Filtering Oversampling Triggering Analog Signal Information

More information

Data Acquisition Systems. Signal DAQ System The Answer?

Data Acquisition Systems. Signal DAQ System The Answer? Outline Analysis of Waveforms and Transforms How many Samples to Take Aliasing Negative Spectrum Frequency Resolution Synchronizing Sampling Non-repetitive Waveforms Picket Fencing A Sampled Data System

More information

An Overview of the Decimation process and its VLSI implementation

An Overview of the Decimation process and its VLSI implementation MPRA Munich Personal RePEc Archive An Overview of the Decimation process and its VLSI implementation Rozita Teymourzadeh and Masuri Othman UKM University 1. February 2006 Online at http://mpra.ub.uni-muenchen.de/41945/

More information

DSP Laboratory (EELE 4110) Lab#10 Finite Impulse Response (FIR) Filters

DSP Laboratory (EELE 4110) Lab#10 Finite Impulse Response (FIR) Filters Islamic University of Gaza OBJECTIVES: Faculty of Engineering Electrical Engineering Department Spring-2011 DSP Laboratory (EELE 4110) Lab#10 Finite Impulse Response (FIR) Filters To demonstrate the concept

More information

Experiment 2 Effects of Filtering

Experiment 2 Effects of Filtering Experiment 2 Effects of Filtering INTRODUCTION This experiment demonstrates the relationship between the time and frequency domains. A basic rule of thumb is that the wider the bandwidth allowed for the

More information

Multirate Filtering, Resampling Filters, Polyphase Filters. or how to make efficient FIR filters

Multirate Filtering, Resampling Filters, Polyphase Filters. or how to make efficient FIR filters Multirate Filtering, Resampling Filters, Polyphase Filters or how to make efficient FIR filters THE NOBLE IDENTITY 1 Efficient Implementation of Resampling filters H(z M ) M:1 M:1 H(z) Rule 1: Filtering

More information

DISCRETE-TIME CHANNELIZERS FOR AERONAUTICAL TELEMETRY: PART II VARIABLE BANDWIDTH

DISCRETE-TIME CHANNELIZERS FOR AERONAUTICAL TELEMETRY: PART II VARIABLE BANDWIDTH DISCRETE-TIME CHANNELIZERS FOR AERONAUTICAL TELEMETRY: PART II VARIABLE BANDWIDTH Brian Swenson, Michael Rice Brigham Young University Provo, Utah, USA ABSTRACT A discrete-time channelizer capable of variable

More information

Implementation of CIC filter for DUC/DDC

Implementation of CIC filter for DUC/DDC Implementation of CIC filter for DUC/DDC R Vaishnavi #1, V Elamaran #2 #1 Department of Electronics and Communication Engineering School of EEE, SASTRA University Thanjavur, India rvaishnavi26@gmail.com

More information

Low-Power Decimation Filter Design for Multi-Standard Transceiver Applications

Low-Power Decimation Filter Design for Multi-Standard Transceiver Applications i Low-Power Decimation Filter Design for Multi-Standard Transceiver Applications by Carol J. Barrett Master of Science in Electrical Engineering University of California, Berkeley Professor Paul R. Gray,

More information

ECE 6560 Multirate Signal Processing Chapter 13

ECE 6560 Multirate Signal Processing Chapter 13 Multirate Signal Processing Chapter 13 Dr. Bradley J. Bazuin Western Michigan University College of Engineering and Applied Sciences Department of Electrical and Computer Engineering 1903 W. Michigan Ave.

More information

PoS(11th EVN Symposium)113

PoS(11th EVN Symposium)113 High-order sampling technique for geodetic VLBI and the future National Institute of Information and Communications Technology, 893-1 Hirai, Kashima, Ibaraki 314-8501, Japan E-mail: takefuji@nict.go.jp

More information

ALMA Memo No. 579 Revised version of September 20, The new 3-stage, low dissipation digital filter of the ALMA Correlator

ALMA Memo No. 579 Revised version of September 20, The new 3-stage, low dissipation digital filter of the ALMA Correlator ALMA Memo No. 579 Revised version of September 2, 28 The new -stage, low dissipation digital filter of the ALMA Correlator P.Camino 1, B. Quertier 1, A.Baudry 1, G.Comoretto 2, D.Dallet 1 Observatoire

More information

IIR Filter Design Chapter Intended Learning Outcomes: (i) Ability to design analog Butterworth filters

IIR Filter Design Chapter Intended Learning Outcomes: (i) Ability to design analog Butterworth filters IIR Filter Design Chapter Intended Learning Outcomes: (i) Ability to design analog Butterworth filters (ii) Ability to design lowpass IIR filters according to predefined specifications based on analog

More information

EECS 452 Midterm Exam Winter 2012

EECS 452 Midterm Exam Winter 2012 EECS 452 Midterm Exam Winter 2012 Name: unique name: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. Scores: # Points Section I /40 Section II

More information

Window Method. designates the window function. Commonly used window functions in FIR filters. are: 1. Rectangular Window:

Window Method. designates the window function. Commonly used window functions in FIR filters. are: 1. Rectangular Window: Window Method We have seen that in the design of FIR filters, Gibbs oscillations are produced in the passband and stopband, which are not desirable features of the FIR filter. To solve this problem, window

More information

VIIP: a PCI programmable board.

VIIP: a PCI programmable board. VIIP: a PCI programmable board. G. Bianchi (1), L. Zoni (1), S. Montebugnoli (1) (1) Institute of Radio Astronomy, National Institute for Astrophysics Via Fiorentina 3508/B, 40060 Medicina (BO), Italy.

More information

Noise removal example. Today s topic. Digital Signal Processing. Lecture 3. Application Specific Integrated Circuits for

Noise removal example. Today s topic. Digital Signal Processing. Lecture 3. Application Specific Integrated Circuits for Application Specific Integrated Circuits for Digital Signal Processing Lecture 3 Oscar Gustafsson Applications of Digital Filters Frequency-selective digital filters Removal of noise and interfering signals

More information

The Fundamentals of Mixed Signal Testing

The Fundamentals of Mixed Signal Testing The Fundamentals of Mixed Signal Testing Course Information The Fundamentals of Mixed Signal Testing course is designed to provide the foundation of knowledge that is required for testing modern mixed

More information

CHAPTER. delta-sigma modulators 1.0

CHAPTER. delta-sigma modulators 1.0 CHAPTER 1 CHAPTER Conventional delta-sigma modulators 1.0 This Chapter presents the traditional first- and second-order DSM. The main sources for non-ideal operation are described together with some commonly

More information

Implementation of Decimation Filter for Hearing Aid Application

Implementation of Decimation Filter for Hearing Aid Application Implementation of Decimation Filter for Hearing Aid Application Prof. Suraj R. Gaikwad, Er. Shruti S. Kshirsagar and Dr. Sagar R. Gaikwad Electronics Engineering Department, D.M.I.E.T.R. Wardha email:

More information

The EVN DBBC Project. G. Tuccari Istituto di Radioastronomia Noto, Italy. Digital Backend Workshop - Bonn, Germany

The EVN DBBC Project. G. Tuccari Istituto di Radioastronomia Noto, Italy. Digital Backend Workshop - Bonn, Germany The EVN DBBC Project G. Tuccari Istituto di Radioastronomia Noto, Italy EVN DBBC Working Group S. Pogrebenko, S. Parsley JIVE-Dwingeloo, The Netherlansds W. Alef MPI-Radiastronomie-Bonn, Germany Y. Xiang

More information

ELT Receiver Architectures and Signal Processing Exam Requirements and Model Questions 2018

ELT Receiver Architectures and Signal Processing Exam Requirements and Model Questions 2018 TUT/ICE 1 ELT-44006 Receiver Architectures and Signal Processing Exam Requirements and Model Questions 2018 General idea of these Model Questions is to highlight the central knowledge expected to be known

More information

FYS3240 PC-based instrumentation and microcontrollers. Signal sampling. Spring 2017 Lecture #5

FYS3240 PC-based instrumentation and microcontrollers. Signal sampling. Spring 2017 Lecture #5 FYS3240 PC-based instrumentation and microcontrollers Signal sampling Spring 2017 Lecture #5 Bekkeng, 30.01.2017 Content Aliasing Sampling Analog to Digital Conversion (ADC) Filtering Oversampling Triggering

More information

System on a Chip. Prof. Dr. Michael Kraft

System on a Chip. Prof. Dr. Michael Kraft System on a Chip Prof. Dr. Michael Kraft Lecture 5: Data Conversion ADC Background/Theory Examples Background Physical systems are typically analogue To apply digital signal processing, the analogue signal

More information

Design of FIR Filters

Design of FIR Filters Design of FIR Filters Elena Punskaya www-sigproc.eng.cam.ac.uk/~op205 Some material adapted from courses by Prof. Simon Godsill, Dr. Arnaud Doucet, Dr. Malcolm Macleod and Prof. Peter Rayner 1 FIR as a

More information

A Subsampling UWB Radio Architecture By Analytic Signaling

A Subsampling UWB Radio Architecture By Analytic Signaling EE209AS Spring 2011 Prof. Danijela Cabric Paper Presentation Presented by: Sina Basir-Kazeruni sinabk@ucla.edu A Subsampling UWB Radio Architecture By Analytic Signaling by Mike S. W. Chen and Robert W.

More information

Multistage Implementation of 64x Interpolator

Multistage Implementation of 64x Interpolator ISSN: 78 33 Volume, Issue 7, September Multistage Implementation of 6x Interpolator Rahul Sinha, Scholar (M.E.), CSIT DURG. Sonika Arora, Associate Professor, CSIT DURG. Abstract This paper presents the

More information

3GPP LTE Digital Front End Reference Design Authors: Helen Tarn, Ed Hemphill, and David Hawke

3GPP LTE Digital Front End Reference Design Authors: Helen Tarn, Ed Hemphill, and David Hawke Application Note: Virtex-5 FPGA XAPP3 (v.0) October 9, 008 3GPP LTE Digital Front End eference Design Authors: Helen Tarn, Ed Hemphill, and David Hawke Summary Introduction This application note provides

More information

Reference Clock Distribution for a 325MHz IF Sampling System with over 30MHz Bandwidth, 64dB SNR and 80dB SFDR

Reference Clock Distribution for a 325MHz IF Sampling System with over 30MHz Bandwidth, 64dB SNR and 80dB SFDR Reference Clock Distribution for a 325MHz IF Sampling System with over 30MHz Bandwidth, 64dB SNR and 80dB SFDR Michel Azarian Clock jitter introduced in an RF receiver through reference clock buffering

More information

Interpolators And Interpolation

Interpolators And Interpolation Interpolators And Interpolation 1 Applications Fixed Up-Sampler Interpolators Fixed Down-Sample Filters Reduced Cost Filtering When Large Ratio of Sample Rate to Bandwidth Timing Recovery Re-Sampling of

More information

Filter Banks I. Prof. Dr. Gerald Schuller. Fraunhofer IDMT & Ilmenau University of Technology Ilmenau, Germany. Fraunhofer IDMT

Filter Banks I. Prof. Dr. Gerald Schuller. Fraunhofer IDMT & Ilmenau University of Technology Ilmenau, Germany. Fraunhofer IDMT Filter Banks I Prof. Dr. Gerald Schuller Fraunhofer IDMT & Ilmenau University of Technology Ilmenau, Germany 1 Structure of perceptual Audio Coders Encoder Decoder 2 Filter Banks essential element of most

More information

Frequency Domain Representation of Signals

Frequency Domain Representation of Signals Frequency Domain Representation of Signals The Discrete Fourier Transform (DFT) of a sampled time domain waveform x n x 0, x 1,..., x 1 is a set of Fourier Coefficients whose samples are 1 n0 X k X0, X

More information

Accurate Harmonics Measurement by Sampler Part 2

Accurate Harmonics Measurement by Sampler Part 2 Accurate Harmonics Measurement by Sampler Part 2 Akinori Maeda Verigy Japan akinori.maeda@verigy.com September 2011 Abstract of Part 1 The Total Harmonic Distortion (THD) is one of the major frequency

More information

CHAPTER 2 FIR ARCHITECTURE FOR THE FILTER BANK OF SPEECH PROCESSOR

CHAPTER 2 FIR ARCHITECTURE FOR THE FILTER BANK OF SPEECH PROCESSOR 22 CHAPTER 2 FIR ARCHITECTURE FOR THE FILTER BANK OF SPEECH PROCESSOR 2.1 INTRODUCTION A CI is a device that can provide a sense of sound to people who are deaf or profoundly hearing-impaired. Filters

More information

National Radio Astronomy Observatory

National Radio Astronomy Observatory National Radio Astronomy Observatory Charlottesville, Virginia Mey 3, 1968 To: From: Arthur M. Shalloway Subject: Revised Functional Description of NRAO Correlation Receiver Model II (See Original Description

More information

Timing Error Analysis in Digital-to-Analog Converters

Timing Error Analysis in Digital-to-Analog Converters Timing Error Analysis in Digital-to-Analog Converters - Effects of Sampling Clock Jitter and Timing Skew (Glitch) - Shinya Kawakami, Haruo Kobayashi, Naoki Kurosawa, Ikkou Miyauchi, Hideyuki Kogure, Takanori

More information

Advantages of Analog Representation. Varies continuously, like the property being measured. Represents continuous values. See Figure 12.

Advantages of Analog Representation. Varies continuously, like the property being measured. Represents continuous values. See Figure 12. Analog Signals Signals that vary continuously throughout a defined range. Representative of many physical quantities, such as temperature and velocity. Usually a voltage or current level. Digital Signals

More information

A DSP IMPLEMENTED DIGITAL FM MULTIPLEXING SYSTEM

A DSP IMPLEMENTED DIGITAL FM MULTIPLEXING SYSTEM A DSP IMPLEMENTED DIGITAL FM MULTIPLEXING SYSTEM Item Type text; Proceedings Authors Rosenthal, Glenn K. Publisher International Foundation for Telemetering Journal International Telemetering Conference

More information

arxiv:astro-ph/ v1 3 Mar 2005

arxiv:astro-ph/ v1 3 Mar 2005 Astronomy & Astrophysics manuscript no. 2227 June 12, 218 (DOI: will be inserted by hand later) A Field Programmable Gate Array Spectrometer for Radio Astronomy arxiv:astro-ph/5367v1 3 Mar 25 First Light

More information

RPG XFFTS. extended bandwidth Fast Fourier Transform Spectrometer. Technical Specification

RPG XFFTS. extended bandwidth Fast Fourier Transform Spectrometer. Technical Specification RPG XFFTS extended bandwidth Fast Fourier Transform Spectrometer Technical Specification 19 XFFTS crate equiped with eight XFFTS boards and one XFFTS controller Fast Fourier Transform Spectrometer The

More information

DIGITAL SIGNAL PROCESSING TOOLS VERSION 4.0

DIGITAL SIGNAL PROCESSING TOOLS VERSION 4.0 (Digital Signal Processing Tools) Indian Institute of Technology Roorkee, Roorkee DIGITAL SIGNAL PROCESSING TOOLS VERSION 4.0 A Guide that will help you to perform various DSP functions, for a course in

More information

Advanced AD/DA converters. ΔΣ DACs. Overview. Motivations. System overview. Why ΔΣ DACs

Advanced AD/DA converters. ΔΣ DACs. Overview. Motivations. System overview. Why ΔΣ DACs Advanced AD/DA converters Overview Why ΔΣ DACs ΔΣ DACs Architectures for ΔΣ DACs filters Smoothing filters Pietro Andreani Dept. of Electrical and Information Technology Lund University, Sweden Advanced

More information

Module 9 AUDIO CODING. Version 2 ECE IIT, Kharagpur

Module 9 AUDIO CODING. Version 2 ECE IIT, Kharagpur Module 9 AUDIO CODING Lesson 30 Polyphase filter implementation Instructional Objectives At the end of this lesson, the students should be able to : 1. Show how a bank of bandpass filters can be realized

More information

Other Modulation Techniques - CAP, QAM, DMT

Other Modulation Techniques - CAP, QAM, DMT Other Modulation Techniques - CAP, QAM, DMT Prof. David Johns (johns@eecg.toronto.edu) (www.eecg.toronto.edu/~johns) slide 1 of 47 Complex Signals Concept useful for describing a pair of real signals Let

More information

DECIMATION FILTER FOR MULTISTANDARD WIRELESS RECEIVER SHEETAL S.SHENDE

DECIMATION FILTER FOR MULTISTANDARD WIRELESS RECEIVER SHEETAL S.SHENDE DECIMATION FILTER FOR MULTISTANDARD WIRELESS RECEIVER SHEETAL S.SHENDE Abstract The demand for new telecommunication services requiring higher capacities, data rates and different operating modes have

More information

Acquisition and Tracking of IRNSS Receiver on MATLAB and Xilinx

Acquisition and Tracking of IRNSS Receiver on MATLAB and Xilinx Acquisition and Tracking of IRNSS Receiver on MATLAB and Xilinx Kishan Y. Rathod 1, Dr. Rajendra D. Patel 2, Amit Chorasiya 3 1 M.E Student / Marwadi Education Foundation s Groups of Institute 2 Accociat

More information

Design and Implementation of Digital Signal Processing Hardware for a Software Radio Reciever

Design and Implementation of Digital Signal Processing Hardware for a Software Radio Reciever Utah State University DigitalCommons@USU All Graduate Theses and Dissertations Graduate Studies 5-2008 Design and Implementation of Digital Signal Processing Hardware for a Software Radio Reciever Jake

More information

Interpolated Lowpass FIR Filters

Interpolated Lowpass FIR Filters 24 COMP.DSP Conference; Cannon Falls, MN, July 29-3, 24 Interpolated Lowpass FIR Filters Speaker: Richard Lyons Besser Associates E-mail: r.lyons@ieee.com 1 Prototype h p (k) 2 4 k 6 8 1 Shaping h sh (k)

More information

OKAN UNIVERSITY FACULTY OF ENGINEERING AND ARCHITECTURE. EEE 403 Digital Signal Processing 10 Periodic Sampling

OKAN UNIVERSITY FACULTY OF ENGINEERING AND ARCHITECTURE. EEE 403 Digital Signal Processing 10 Periodic Sampling OKAN UNIVERSITY FACULTY OF ENGINEERING AND ARCHITECTURE EEE 403 Digital Signal Processing 10 Periodic Sampling Fall 2013 Yrd. Doç. Dr. Didem Kivanc Tureli didemk@ieee.org didem.kivanc@okan.edu.tr 12/20/2013

More information

Research Article Design and Simulation of a Fully Digitized GNSS Receiver Front-End

Research Article Design and Simulation of a Fully Digitized GNSS Receiver Front-End Discrete Dynamics in Nature and Society Volume 211, Article ID 329535, 11 pages doi:1.1155/211/329535 Research Article Design and Simulation of a Fully Digitized GNSS Receiver Front-End Yuan Yu, Qing Chang,

More information

A Closer Look at 2-Stage Digital Filtering in the. Proposed WIDAR Correlator for the EVLA

A Closer Look at 2-Stage Digital Filtering in the. Proposed WIDAR Correlator for the EVLA NRC-EVLA Memo# 1 A Closer Look at 2-Stage Digital Filtering in the Proposed WIDAR Correlator for the EVLA NRC-EVLA Memo# Brent Carlson, June 2, 2 ABSTRACT The proposed WIDAR correlator for the EVLA that

More information

Channelization and Frequency Tuning using FPGA for UMTS Baseband Application

Channelization and Frequency Tuning using FPGA for UMTS Baseband Application Channelization and Frequency Tuning using FPGA for UMTS Baseband Application Prof. Mahesh M.Gadag Communication Engineering, S. D. M. College of Engineering & Technology, Dharwad, Karnataka, India Mr.

More information

Pre-distortion. General Principles & Implementation in Xilinx FPGAs

Pre-distortion. General Principles & Implementation in Xilinx FPGAs Pre-distortion General Principles & Implementation in Xilinx FPGAs Issues in Transmitter Design 3G systems place much greater requirements on linearity and efficiency of RF transmission stage Linearity

More information

Getting Started. MSO/DPO Series Oscilloscopes. Basic Concepts

Getting Started. MSO/DPO Series Oscilloscopes. Basic Concepts Getting Started MSO/DPO Series Oscilloscopes Basic Concepts 001-1523-00 Getting Started 1.1 Getting Started What is an oscilloscope? An oscilloscope is a device that draws a graph of an electrical signal.

More information

Summary Last Lecture

Summary Last Lecture Interleaved ADCs EE47 Lecture 4 Oversampled ADCs Why oversampling? Pulse-count modulation Sigma-delta modulation 1-Bit quantization Quantization error (noise) spectrum SQNR analysis Limit cycle oscillations

More information

arxiv: v1 [cs.it] 9 Mar 2016

arxiv: v1 [cs.it] 9 Mar 2016 A Novel Design of Linear Phase Non-uniform Digital Filter Banks arxiv:163.78v1 [cs.it] 9 Mar 16 Sakthivel V, Elizabeth Elias Department of Electronics and Communication Engineering, National Institute

More information

From Digital to RF Debugging in the Time and Frequency Domain. Embedded Systems Conference 2015 May 6-7, 2015

From Digital to RF Debugging in the Time and Frequency Domain. Embedded Systems Conference 2015 May 6-7, 2015 From Digital to RF Debugging in the Time and Frequency Domain Embedded Systems Conference 2015 May 6-7, 2015 Agenda In this seminar we ll discuss ı The challenges of debugging mixed domain embedded systems

More information

Problems from the 3 rd edition

Problems from the 3 rd edition (2.1-1) Find the energies of the signals: a) sin t, 0 t π b) sin t, 0 t π c) 2 sin t, 0 t π d) sin (t-2π), 2π t 4π Problems from the 3 rd edition Comment on the effect on energy of sign change, time shifting

More information

EECS 452 Midterm Exam (solns) Fall 2012

EECS 452 Midterm Exam (solns) Fall 2012 EECS 452 Midterm Exam (solns) Fall 2012 Name: unique name: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. Scores: # Points Section I /40 Section

More information

01/26/2015 DIGITAL INTERLEAVED PWM FOR ENVELOPE TRACKING CONVERTERS. Pallab Midya, Ph.D.

01/26/2015 DIGITAL INTERLEAVED PWM FOR ENVELOPE TRACKING CONVERTERS. Pallab Midya, Ph.D. 1 DIGITAL INTERLEAVED PWM FOR ENVELOPE TRACKING CONVERTERS Pallab Midya, Ph.D. pallab.midya@adxesearch.com ABSTRACT The bandwidth of a switched power converter is limited by Nyquist sampling theory. Further,

More information

IP-DDC Channel Digital Downconversion Core for FPGA FEATURES DESCRIPTION APPLICATIONS IMPLEMENTATION SUPPORT HARDWARE SUPPORT

IP-DDC Channel Digital Downconversion Core for FPGA FEATURES DESCRIPTION APPLICATIONS IMPLEMENTATION SUPPORT HARDWARE SUPPORT 128 Channel Digital Downconversion Core for FPGA v1.0 FEATURES 128 individually tuned DDC channels 16 bit 200MHz input Tuning resolution Fs/2^32 SFDR 96 db for 16 bits input Decimation range from 512 to

More information

Choosing the Best ADC Architecture for Your Application Part 4:

Choosing the Best ADC Architecture for Your Application Part 4: Choosing the Best ADC Architecture for Your Application Part 4: Hello, my name is Luis Chioye, Applications Engineer for the Precision the Data Converters team. And I am Ryan Callaway; I am a Product Marketing

More information

Microcomputer Systems 1. Introduction to DSP S

Microcomputer Systems 1. Introduction to DSP S Microcomputer Systems 1 Introduction to DSP S Introduction to DSP s Definition: DSP Digital Signal Processing/Processor It refers to: Theoretical signal processing by digital means (subject of ECE3222,

More information

EE247 Lecture 14. To avoid having EE247 & EE 142 or EE290C midterms on the same day, EE247 midterm moved from Oct. 20 th to Thurs. Oct.

EE247 Lecture 14. To avoid having EE247 & EE 142 or EE290C midterms on the same day, EE247 midterm moved from Oct. 20 th to Thurs. Oct. Administrative issues EE247 Lecture 14 To avoid having EE247 & EE 142 or EE29C midterms on the same day, EE247 midterm moved from Oct. 2 th to Thurs. Oct. 27 th Homework # 4 due on Thurs. Oct. 2 th H.K.

More information

B.Tech III Year II Semester (R13) Regular & Supplementary Examinations May/June 2017 DIGITAL SIGNAL PROCESSING (Common to ECE and EIE)

B.Tech III Year II Semester (R13) Regular & Supplementary Examinations May/June 2017 DIGITAL SIGNAL PROCESSING (Common to ECE and EIE) Code: 13A04602 R13 B.Tech III Year II Semester (R13) Regular & Supplementary Examinations May/June 2017 (Common to ECE and EIE) PART A (Compulsory Question) 1 Answer the following: (10 X 02 = 20 Marks)

More information

The Case for Oversampling

The Case for Oversampling EE47 Lecture 4 Oversampled ADCs Why oversampling? Pulse-count modulation Sigma-delta modulation 1-Bit quantization Quantization error (noise) spectrum SQNR analysis Limit cycle oscillations nd order ΣΔ

More information

DDC_DEC. Digital Down Converter with configurable Decimation Filter Rev Block Diagram. Key Design Features. Applications. Generic Parameters

DDC_DEC. Digital Down Converter with configurable Decimation Filter Rev Block Diagram. Key Design Features. Applications. Generic Parameters Key Design Features Block Diagram Synthesizable, technology independent VHDL Core 16-bit signed input/output samples 1 Digital oscillator with > 100 db SFDR Digital oscillator phase resolution of 2π/2

More information

ELEC-C5230 Digitaalisen signaalinkäsittelyn perusteet

ELEC-C5230 Digitaalisen signaalinkäsittelyn perusteet ELEC-C5230 Digitaalisen signaalinkäsittelyn perusteet Lecture 10: Summary Taneli Riihonen 16.05.2016 Lecture 10 in Course Book Sanjit K. Mitra, Digital Signal Processing: A Computer-Based Approach, 4th

More information

NCR Channelizer Server

NCR Channelizer Server NCR Channelizer Server Thousands of Signals One Receiver Novator Channelizer Receiver system lets you analyze thousands of signals with a single receiver. It streams channelized data to other systems where

More information

UNIVERSITY OF SWAZILAND

UNIVERSITY OF SWAZILAND UNIVERSITY OF SWAZILAND MAIN EXAMINATION, MAY 2013 FACULTY OF SCIENCE AND ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONIC ENGINEERING TITLE OF PAPER: INTRODUCTION TO DIGITAL SIGNAL PROCESSING COURSE

More information

DIGITAL FILTERING AND THE DFT

DIGITAL FILTERING AND THE DFT DIGITAL FILTERING AND THE DFT Digital Linear Filters in the Receiver Discrete-time Linear System Tidbits DFT Tidbits Filter Design Tidbits idealized system Software Receiver Design Johnson/Sethares/Klein

More information

Phased Array VLBI Processor for SMA PHased-array Recording INstrument for Galactic Event-horizon Studies 29 September 2009

Phased Array VLBI Processor for SMA PHased-array Recording INstrument for Galactic Event-horizon Studies 29 September 2009 Phased Array VLBI Processor for SMA PHased-array Recording INstrument for Galactic Event-horizon Studies 29 September 2009 Rurik A. Primiani Rurik Primiani & Jonathan Weintroub, CfA-SMA Collaborators:

More information

CLOUDSDR RFSPACE #CONNECTED SOFTWARE DEFINED RADIO. final design might vary without notice

CLOUDSDR RFSPACE #CONNECTED SOFTWARE DEFINED RADIO. final design might vary without notice CLOUDSDR #CONNECTED SOFTWARE DEFINED RADIO final design might vary without notice 1 - PRELIMINARY SPECIFICATIONS http://www.rfspace.com v0.1 RFSPACE CloudSDR CLOUDSDR INTRODUCTION The RFSPACE CloudSDR

More information

Digital Filters IIR (& Their Corresponding Analog Filters) Week Date Lecture Title

Digital Filters IIR (& Their Corresponding Analog Filters) Week Date Lecture Title http://elec3004.com Digital Filters IIR (& Their Corresponding Analog Filters) 2017 School of Information Technology and Electrical Engineering at The University of Queensland Lecture Schedule: Week Date

More information

6 Sampling. Sampling. The principles of sampling, especially the benefits of coherent sampling

6 Sampling. Sampling. The principles of sampling, especially the benefits of coherent sampling Note: Printed Manuals 6 are not in Color Objectives This chapter explains the following: The principles of sampling, especially the benefits of coherent sampling How to apply sampling principles in a test

More information

VLSI Implementation of Digital Down Converter (DDC)

VLSI Implementation of Digital Down Converter (DDC) Volume-7, Issue-1, January-February 2017 International Journal of Engineering and Management Research Page Number: 218-222 VLSI Implementation of Digital Down Converter (DDC) Shaik Afrojanasima 1, K Vijaya

More information

Cascaded Noise-Shaping Modulators for Oversampled Data Conversion

Cascaded Noise-Shaping Modulators for Oversampled Data Conversion Cascaded Noise-Shaping Modulators for Oversampled Data Conversion Bruce A. Wooley Stanford University B. Wooley, Stanford, 2004 1 Outline Oversampling modulators for A/D conversion Cascaded noise-shaping

More information

Optimal Design RRC Pulse Shape Polyphase FIR Decimation Filter for Multi-Standard Wireless Transceivers

Optimal Design RRC Pulse Shape Polyphase FIR Decimation Filter for Multi-Standard Wireless Transceivers Optimal Design RRC Pulse Shape Polyphase FIR Decimation Filter for ulti-standard Wireless Transceivers ANDEEP SINGH SAINI 1, RAJIV KUAR 2 1.Tech (E.C.E), Guru Nanak Dev Engineering College, Ludhiana, P.

More information

Analog-to-Digital Converter Survey & Analysis. Bob Walden. (310) Update: July 16,1999

Analog-to-Digital Converter Survey & Analysis. Bob Walden. (310) Update: July 16,1999 Analog-to-Digital Converter Survey & Analysis Update: July 16,1999 References: 1. R.H. Walden, Analog-to-digital converter survey and analysis, IEEE Journal on Selected Areas in Communications, vol. 17,

More information

Summary Last Lecture

Summary Last Lecture EE47 Lecture 5 Pipelined ADCs (continued) How many bits per stage? Algorithmic ADCs utilizing pipeline structure Advanced background calibration techniques Oversampled ADCs Why oversampling? Pulse-count

More information

A Faster Method for Accurate Spectral Testing without Requiring Coherent Sampling

A Faster Method for Accurate Spectral Testing without Requiring Coherent Sampling A Faster Method for Accurate Spectral Testing without Requiring Coherent Sampling Minshun Wu 1,2, Degang Chen 2 1 Xi an Jiaotong University, Xi an, P. R. China 2 Iowa State University, Ames, IA, USA Abstract

More information

Electrical & Computer Engineering Technology

Electrical & Computer Engineering Technology Electrical & Computer Engineering Technology EET 419C Digital Signal Processing Laboratory Experiments by Masood Ejaz Experiment # 1 Quantization of Analog Signals and Calculation of Quantized noise Objective:

More information

Design of a Down Converter for a Galileo Receiver Master of Science Thesis

Design of a Down Converter for a Galileo Receiver Master of Science Thesis Design of a Down Converter for a Galileo Receiver Master of Science Thesis Alexander Vickberg Yue Wu Chalmers University of Technology University of Gothenburg Department of Computer Science and Engineering

More information

Performance Analysis of FIR Filter Design Using Reconfigurable Mac Unit

Performance Analysis of FIR Filter Design Using Reconfigurable Mac Unit Volume 4 Issue 4 December 2016 ISSN: 2320-9984 (Online) International Journal of Modern Engineering & Management Research Website: www.ijmemr.org Performance Analysis of FIR Filter Design Using Reconfigurable

More information

Cyclone II Filtering Lab

Cyclone II Filtering Lab May 2005, ver. 1.0 Application Note 376 Introduction The Cyclone II filtering lab design provided in the DSP Development Kit, Cyclone II Edition, shows you how to use the Altera DSP Builder for system

More information

Digital Transceiver V605

Digital Transceiver V605 Embedded PC-based Instrument with up-to 4 Independent DDCs, 4 DUCs and Dual Spectrum Analyzers System Features Intel i7 Quad Core, 8 GB RAM, 240 GB SSD, Win 7 Pro 64-bit Sustained logging rate up-to 1600

More information

Keywords: CIC Filter, Field Programmable Gate Array (FPGA), Decimator, Interpolator, Modelsim and Chipscope.

Keywords: CIC Filter, Field Programmable Gate Array (FPGA), Decimator, Interpolator, Modelsim and Chipscope. www.semargroup.org, www.ijsetr.com ISSN 2319-8885 Vol.03,Issue.25 September-2014, Pages:5002-5008 VHDL Implementation of Optimized Cascaded Integrator Comb (CIC) Filters for Ultra High Speed Wideband Rate

More information

F I R Filter (Finite Impulse Response)

F I R Filter (Finite Impulse Response) F I R Filter (Finite Impulse Response) Ir. Dadang Gunawan, Ph.D Electrical Engineering University of Indonesia The Outline 7.1 State-of-the-art 7.2 Type of Linear Phase Filter 7.3 Summary of 4 Types FIR

More information

Discrete Fourier Transform, DFT Input: N time samples

Discrete Fourier Transform, DFT Input: N time samples EE445M/EE38L.6 Lecture. Lecture objectives are to: The Discrete Fourier Transform Windowing Use DFT to design a FIR digital filter Discrete Fourier Transform, DFT Input: time samples {a n = {a,a,a 2,,a

More information

Subband coring for image noise reduction. Edward H. Adelson Internal Report, RCA David Sarnoff Research Center, Nov

Subband coring for image noise reduction. Edward H. Adelson Internal Report, RCA David Sarnoff Research Center, Nov Subband coring for image noise reduction. dward H. Adelson Internal Report, RCA David Sarnoff Research Center, Nov. 26 1986. Let an image consisting of the array of pixels, (x,y), be denoted (the boldface

More information

ECE 6560 Multirate Signal Processing Lecture 9

ECE 6560 Multirate Signal Processing Lecture 9 Multirate Signal Processing Lecture 9 Dr. Bradley J. Bazuin estern Michigan University College of Engineering and Applied Sciences Department of Electrical and Computer Engineering 193. Michigan Ave. Kalamazoo

More information

4. Design of Discrete-Time Filters

4. Design of Discrete-Time Filters 4. Design of Discrete-Time Filters 4.1. Introduction (7.0) 4.2. Frame of Design of IIR Filters (7.1) 4.3. Design of IIR Filters by Impulse Invariance (7.1) 4.4. Design of IIR Filters by Bilinear Transformation

More information

The Filter Wizard issue 35: Turn linear phase into truly linear phase Kendall Castor-Perry

The Filter Wizard issue 35: Turn linear phase into truly linear phase Kendall Castor-Perry The Filter Wizard issue 35: Turn linear phase into truly linear phase Kendall Castor-Perry In the previous episode, the Filter Wizard pointed out the perils of phase flipping in the stopband of FIR filters.

More information

Digital audio filter design based on YSS920B. Mang Zhou1,a

Digital audio filter design based on YSS920B. Mang Zhou1,a 3rd International Conference on Mechatronics and Industrial Informatics (ICMII 2015) Digital audio filter design based on YSS920B Mang Zhou1,a 1 ChongQing College of Electronic Engineering, ChongQing 401331,P.

More information

Continuously Variable Bandwidth Sharp FIR Filters with Low Complexity

Continuously Variable Bandwidth Sharp FIR Filters with Low Complexity Journal of Signal and Information Processing, 2012, 3, 308-315 http://dx.doi.org/10.4236/sip.2012.33040 Published Online August 2012 (http://www.scirp.org/ournal/sip) Continuously Variable Bandwidth Sharp

More information