3GPP LTE Digital Front End Reference Design Authors: Helen Tarn, Ed Hemphill, and David Hawke

Transcription

1 Application Note: Virtex-5 FPGA XAPP3 (v.0) October 9, 008 3GPP LTE Digital Front End eference Design Authors: Helen Tarn, Ed Hemphill, and David Hawke Summary Introduction This application note provides designers with an optimized solution for Digital Up Conversion (DUC), Digital Down Conversion (DDC), and Crest Factor eduction (CF) required in a typical 3rd Generation Partnership Protocol (3GPP) Long Term Evolution (LTE) radio. The design is configurable to support seven single and multi-carrier scenarios, while offering an optimized solution for each chosen configuration that allows designers to select their requirement without paying a penalty on design area, and therefore cost and power. Developed in Xilinx System Generator for DSP, the design allows customization to meet the needs of radio designs for the 3GPP LTE specification. Accompanying this application note are design files, test vectors, and scripts that allow designers to quickly evaluate the performance of the reference design within MATLAB. Additionally, instructions on how to integrate the reference design into a larger system design are included. Design files are available for Virtex -5 device architectures. The wireless industry is aggressively reducing Capital Expenditure (CapEx) and Operating Expenditure (OpEx). It is estimated that up to 60 percent of the overall CapEx cost is incurred within the radio elements of a typical base station. Additionally, since the radio also contains the power amplifiers, the radio portion of the design is responsible for much of the OpEx incurred during the lifetime of the site. educing CapEx can be achieved through the use of less costly non-linear power amplifiers, and highly integrated digital radio transceivers. Integration, low cost, high reliability, and low power are key elements to the Xilinx radio solution. To meet industry cost needs, designs must be realized in Xilinx devices in the most efficient manner possible. This application note demonstrates that high clock rates and efficient design techniques for DUC, DDC, and CF processing in Xilinx devices enables designers to meet the needs of their radio designs with very low cost and low power, while benefiting from smaller PCB area and greater reliability. Additionally, OpEx can be reduced through the use of advanced algorithms. OpEx is directly related to the power amplifier efficiency in the base station. Currently, a very small proportion of the DC power consumed by the base station is converted to radiated energy. The efficiency at which a power amplifier can be operated is a function of the transmitted signal. LTE signals have a high Peak-to-Average Power atio (PAP) or Crest Factor. This imposes significant operating restrictions on the power amplifier. To handle the peaks, the amplifier is heavily backed off from its most efficient operating point. To increase efficiency, CF algorithms can be used to decrease the PAP of the transmitted signal prior to it entering the power amplifier. By doing so, the power amplifier can operate with less back off and thus increased efficiency. Another method of improving the efficiency of power amplifiers is to use Digital Pre-Distortion (DPD). ather than use digital signal processing to reduce the dynamic range of the transmitted signal as with CF, DPD is used to linearize the power amplifier itself. DPD is outside the scope of this document, but its reference is included as a widely used method of amplifier efficiency improvement. 008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. XAPP3 (v.0) October 9, 008

2 Introduction Acronyms and Abbreviations 3GPP AGC Block AM BS BTS CapEx CF db DDC DDS DFE DPD DSP DUC EDGE EDGE or e-edge FPGA FI GSM GUI HDL IF LSB LUT MAC MSB OpEx PAP PA PSD MS SFD SN TDM XST 3rd Generation Partnership Project Automatic Gain Control Block andom Access Memory (Xilinx device resource) Base Station Base Transceiver Station Capital Expenditure Crest Factor eduction Decibels Digital Down Converter Direct Digital Synthesizer Digital Front End Digital Pre-Distortion Digital Signal Processing/Processor Digital Up Converter Enhanced Data rates for GSM Evolution Evolved EDGE Field Programmable Gate Array Finite Impulse esponse Global System for Mobile (Communications), originating from Groupe Spécial Mobile Graphical User Interface Hardware Description Language Intermediate Frequency Least Significant Bit(s) Look-Up Table Multiply-Accumulate Most Significant Bit(s) Mega-samples per second (,000,000 samples per second) Operation Expenditures Peak-to-Average Power atio Place and oute Power Spectral Density oot Mean Square Spurious-Free Dynamic ange Signal-to-Noise atio Time Division Multiplex Xilinx Synthesis Technology XAPP3 (v.0) October 9, 008

3 Contents Contents Summary Introduction Acronyms and Abbreviations Contents Figures Tables System-Level Overview Transmit Downlink eceive Uplink Transmit Downlink Design & Implementation Performance equirements Digital Up Converter Architecture Crest Factor eduction Architecture System Performance Implementation eceive Uplink Design & Implementation System Performance Implementation esource Utilization Summary esource Utilization for Downlink esource Utilization for Uplink Power Consumption Power Consumption for Downlink Power Consumption for Uplink Interface equirements Downlink Interface Description Downlink Interface Timing Uplink Interface Description Uplink Interface Timing Latency Software equirements Hardware Verification System Integration Conclusion eferences evision History Notice of Disclaimer Figures Figure. Digital Front-End Architecture for Transmit Downlink Figure. Digital Front-End Architecture for eceive Uplink Figure 3. eference Point for EVM Measurement on an LTE System Figure 4. Digital Up Converter Architecture Figure 5. PSD of the Baseband LTE Signal for 0-MHz Bandwidth Figure 6. Magnitude esponse of Single-ate Channel Filter Figure 7. Interpolation Filter Structure for x5 MHz Configuration Figure 8. Interpolation Filter Structure for x0 MHz Configuration Figure 9. Interpolation Filter Structure for x5 MHz Configuration Figure 0. Interpolation Filter Structure for x0 MHz Configuration Figure. Interpolation Filter Structure for x5 MHz Configuration Figure. PSD after Multi-Carrier 5.36 MHz for x5 MHz Configuration Figure 3. Interpolation Filter Structure for x0 MHz Configuration Figure 4. PSD after Multi-Carrier 30.7 MHz for x0 MHz Configuration Figure 5. Interpolation Filter Structure for 4x5 MHz Configuration Figure 6. PSD after Multi-Carrier 30.7 MHz for 4x5 MHz Configuration Figure 7. 4-Channel Mixing and Combining Module Figure 8. Time Domain View of Peak Cancellation Figure 9. Block Diagram of PC-CF Method (One Iteration) Figure 0. CCDF of CF Input and Output with Two Iterations of PC-CF (x0 MHz) Figure. PSD of CF Input and Output with Two Iterations of PC-CF (x0 MHz) Figure. Constellation Plot for 64 QAM (x0 MHz) 4% EVM Figure 3. CCDF of CF Input and Output with Two Iterations of PC-CF (x0 MHz) Figure 4. PSD of CF Input and Output with Two Iterations of PC-CF (x0 MHz) Figure 5. CCDF of CF Input and Output with [ ] Carrier Configuration, 4% EVM Figure 6. Non-ideal CCDF Curve with [ ] Carrier Configuration Figure 7. PSD of CF Input and Output with [ 0 0 ] Carrier Config, 4% EVM Figure 8. System Generator Block Diagram of Transmit Downlink for 4x5 MHz Configuration XAPP3 (v.0) October 9,

4 Tables Figure 9. System Generator DUC Configuration Subsystem Figure 30. GUI for Single Carrier DUC Configuration Figure 3. System Generator Block Diagram of DUC for x5 MHz Configuration Figure 3. System Generator Block Diagram of DUC for x5 MHz Configuration Figure 33. System Generator Block Diagram of Mixer & Combiner for 4x5 MHz Configuration Figure 34. System Generator Block Diagram of asterized DDS (Half Wave Storage Figure 35. System Generator Diagram of Step Terminal Count Block (4x5 MHz Configuration) Figure 36. System Generator Block Diagram of asterized DDS (Full Wave Storage) Figure 37. System Generator Diagram of Step Terminal Count Block (x5 MHz Configuration) Figure 38. System Generator Block Diagram of ate and Data Format Conversion Block Figure 39. System Generator Block Diagram of PC-CF Design Figure 40. System Generator Diagram of Cancellation Pulses (c_pulses) Module, 6 CPGs version.. 45 Figure 4. Decimation Filter Structure for x0 MHz Configuration Figure 4. Decimation Filter Structure for x5 MHz Configuration Figure 43. Decimation Filter Structure for x0 MHz Configuration Figure 44. Decimation Filter Structure for x5 MHz Configuration Figure 45. Decimation Filter Structure for x0 MHz Configuration Figure 46. Decimation Filter Structure for 4x5 MHz Configuration Figure 47. Magnitude esponse of Channel Filter Figure 48. Example DDS Output Spectrum Figure 49. Block Diagram of eceive Uplink Simulation Software Figure 50. PSD of DDC Input with No Noise and No Interference Figure 5. Transmitted and eceived Constellation with No Noise and No Interference Figure 5. PSD of DDC Input for Noise Only Case Figure 53. Transmitted and eceived Constellation for Noise Only Case Figure 54. PSD of DDC Input for Wideband ACS Test Figure 55. PSD of DDC Input for Narrowband ACS Test Figure 56. PSD of DDC Input for Wideband Intermod Test Figure 57. PSD of DDC Input for Narrowband Intermod Test Figure 58. System Generator Block Diagram of DDC Top Level Figure 59. System Generator Block Diagram of DDC for x5 MHz Configuration Figure 60. System Generator Block Diagram of DDC for 4x5 MHz Configuration Figure 6. System Generator Block Diagram of Fs_4_Mixer Figure 6. System Generator Block Diagram of HB4 Module Figure 63. Screen Shots of FI Compiler 4.0 GUI Figure 64. System Generator Block Diagram of Four-Carrier Mixer Figure 65. System Generator Block Diagram of Four-Carrier Mixer Figure 66. System Generator Block Diagram of TDM Circuit for Carrier Frequencies Figure 67. System Generator Block Diagram of Frequency-to-Phase Accumulator Figure 68. System Generator Block Diagram of Sine/Cosine Lookup Table Figure 69. Dynamic Power versus Frequency of LTE DUC/CF Figure 70. Dynamic Power versus Frequency of LTE DDC Figure 7. Downlink Top-Level Component Figure 7. Timing Diagram of Input Data Interface for Downlink Figure 73. Timing Diagram of Input Control Interface for Downlink Figure 74. Timing Diagram of CF Configuration Interface Figure 75. Timing Diagram of Output Data Interface for Downlink Figure 76. DDC Top-Level Component Figure 77. Timing Diagram of Data Interface for DDC Tables Table. Performance Summary for Transmit Downlink Table. Performance Summary for eceive Uplink Table 3. General LTE Emission Limits Table 4. Additional LTE Emission Limit Table 5. Spectral Mask equirements for LTE (5/0/5/0 MHz BW) Table 6. Properties for Different Carrier Bandwidth Settings Table 7. Filter Parameters for the Channel Filter Table 8. Filter Parameters for eference Design Configurations Table 9. Prototype Filter for Designing Cancellation Pulse Coefficients Table 0. PC-CF Performance for Single-Carrier Configurations Table. PC-CF Performance for Dual-Carrier Configurations Table. PC-CF Performance for 4x5MHz Configuration Table 3. FI Compiler Settings for x5 MHz Configuration Table 4. FI Compiler Settings for x0 MHz Configuration Table 5. FI Compiler Settings for x5 MHz Configuration Table 6. FI Compiler Settings for x0 MHz Configuration Table 7. FI Compiler Settings for x5 MHz Configuration XAPP3 (v.0) October 9,

5 Tables Table 8. FI Compiler Settings for x0 MHz Configuration Table 9. FI Compiler Settings for 4x5 MHz Configuration Table 0. esource Utilization Summary for PC-CF Design Table. E-UTA BS eference Sensitivity Level (From 3GPP T 36.04, Table 7.-) Table. ACS equirement with Wideband Interferer (from Table of [ef ]) Table 3. ACS equirement with Narrowband Interferer (from Tables 7.5-, of [ef ]) Table 4. In-Band Blocking equirements (from Tables 7.6-, of [ef ]) Table 5. Wideband Intermodulation equirements (from Tables 7.8-, of [ef ] Table 6. Narrowband Intermodulation equirements (from Table of [ef ]) Table 7. Summary of ACS, Blocking, and Intermodulation equirements Table 8. Filter Parameters for Halfband Decimator that Follows Fs/4 Mixer Table 9. Filter Parameters for x5 MHz Configuration Table 30. Filter Parameters for x5 MHz Configuration Table 3. Filter Parameters for x0 MHz Configuration Table 3. Filter Parameters for x0 MHz Configuration Table 33. Filter Parameters for x5 MHz Configuration Table 34. Filter Parameters for x0 MHz Configuration Table 35. Filter Parameters for 4x5 MHz Configuration Table 36. Filter Parameters for the Channel Filter Table 37. Decimation Filter Characteristics after 8-Bit Quantization Table 38. SC-FDMA Parameters for Uplink Table 39. SC-FDMA Parameters for Uplink Table 40. Performance Data for Noise Only Case Table 4. Performance Data for Wideband ACS Test Table 4. Performance Data for Narrowband ACS Test Table 43. Performance Data for In-Band Blocking Test Table 44. Performance Data for Wideband Intermod Test Table 45. Performance Data for Narrowband Intermod Test Table 46. FI Compiler Settings for x5 MHz Configuration Table 47. FI Compiler Settings for x0 MHz Configuration Table 48. FI Compiler Settings for x5 MHz Configuration Table 49. FI Compiler Settings for x0 MHz Configuration Table 50. FI Compiler Settings for x5 MHz Configuration Table 5. FI Compiler Settings for x0 MHz Configuration Table 5. FI Compiler Settings for 4x5 MHz Configuration Table 53. esource Utilization Summary for Downlink Design (DUC+CF) Table 54. esource Utilization Summary for DDC Table 55. Dynamic Power of LTE DUC/CF Table 56. Dynamic Power of LTE DDC Table 57. Port Definitions for Downlink Design Table 58. Period for Input Valid Signal (vin) in Downlink Configurations Table 59. Port Definitions for DDC Table 60. Latency and Total Delay of DUC+CF XAPP3 (v.0) October 9,

6 System-Level Overview System-Level Overview Transmit Downlink Figure shows the top-level block diagram for the transmit downlink portion of the digital frontend reference design. The downlink portion includes a DUC, which up samples the baseband signals to.88 Mega-samples per second (), and a peak cancellation crest factor reduction (PC-CF) module to control the peak of the signal to average power ratio (PAP). The reference design supports seven different configurations: Single-carrier 5-MHz, 0-MHz, 5-MHz, and 0-MHz bandwidths Dual-carrier 5-MHz and 0-MHz bandwidths Four-carrier 5-MHz bandwidth The common zero intermediate frequency (IF) architecture is assumed. Therefore, for singlecarrier configurations, the DUC consists of several stages of interpolation filtering and no mixer stage is required. For multi-carrier configurations, a mixing and combining stage is necessary to allocate an individual carrier to its relative position in a 0-MHz or 0-MHz bandwidth before further processing. X-ef Target - Figure Digital Up Converter Channel Filter Interpolation Filtering and Multi-carrier Mixing.88 PC-CF.88 Figure : Digital Front-End Architecture for Transmit Downlink X3_0_0008 Performance Summary Table summarizes the performance of the transmit downlink portion of the digital front-end design. Table : Performance Summary for Transmit Downlink Parameter Value Comments Channel Bandwidths (BW) Input Sample ates 7.68, 5.36, 3.04, 30.7 Output Sample ate 5, 0, 5, 0 MHz Also support x5 MHz, x0 MHz, and 4x5 MHz configurations..88 FPGA Clock ate MHz 3.88 MHz Spectral Mask equirements ACL PAP Target For frequency offsets: within 0 ~ MHz: 55 db within ~ 0 MHz: 65 db over 0 MHz: 67 db 60 db 6~8 0.0% clipping probability For channel bandwidths of 5, 0, 5, 0 MHz, respectively. Derived from Table , -7, - and -3 of Table plus 5 db margin (assuming maximum base station power = 46 dbm). XAPP3 (v.0) October 9,

7 System-Level Overview Table : Performance Summary for Transmit Downlink (Cont d) EVM for Digital Portion eceive Uplink For single carrier: % at 8 db PAP 4% at 7 db PAP 7% at 6 db PAP For multi-carrier: Crest Factor eduction Architecture, page 9 for detail. 64 QAM Modulation Input Signal Quantization 6 bits I/Q Complex input Output Signal Quantization Parameter Value Comments Mixer Properties 6 bits I/Q Complex output Tunability: Fixed esolution: 00 khz Spurious-Free Dynamic ange (SFD): Ideal Assume zero IF; used only in multicarrier configurations. Use rasterized DDS based on 00 khz raster. As illustrated in Figure the receive uplink portion of the digital front-end reference design consists of a fi stage mixer, decimation filters, a second stage mixer (for multi-carrier configurations), and a channel filter. The fi stage mixer is based on an IF centered at one fourth the sample rate (Fs/4). This allows for a very efficient hardware implementation of the mixing process and initial halfband filtering. If the IF is centered at a frequency other than Fs/4, an alternate structure must be used. For example, a generic DDS can be generated using the Xilinx DDS Compiler and this can be combined with a DSP48-based complex multiplier to perform the mixing. The output of this more generic mixing process would feed a traditional halfband decimator that can be designed using the Xilinx Finite Impulse esponse (FI) Compiler. Multiple decimation filtering architectures are required to support the various bandwidths and carrier configuration options in a hardware efficient manner. For multi-carrier configurations, the decimation filtering module includes a second stage of mixing that is used prior to final decimation and channel filtering. X-ef Target - Figure All modules MHz. Sample rates are per single complex channel. From AD Converter.88 Fs/4 Mixer Halfband 6.44 Decimation Filtering and Mulit-carrier Mixing Channel Filter To Baseband Processing Figure : Digital Front-End Architecture for eceive Uplink X3_0_0008 Performance Summary Table summarizes the performance of the receive uplink portion of the digital front-end design. The target filter parameters are derived from the adjacent channel selectivity (ACS), blocking, and intermodulation requirements of the LTE BS receiver described in the [ef ]. The ACS, XAPP3 (v.0) October 9,

8 System-Level Overview blocking, and intermodulation requirements are summarized in the following subsections along with some assumptions that were used in deriving the filter requirements. Table : Performance Summary for eceive Uplink Parameter Value Comments Channel Bandwidths (BW) 5, 0, 5, 0 MHz Also supports x5 MHz, x0 MHz, and 4x5 MHz configurations. Input Sample ate Output Sample ates 7.68, 5.36, 3.04, 30.7 For channel bandwidths of 5, 0, 5, 0 MHz, respectively. FPGA Clock ate MHz 3.88 MHz. EVM for DDC % In absence of noise and interferers. eceive Filter equirement F pass = 0.9 BW/ F stop = BW/ A pass 0. db A stop 80 db Input Signal Quantization 4 bits eal input. F pass is the passband frequency. F stop is the stopband frequency. A pass is the peak-to-peak ripple. A stop is the stopband attenuation. Output Signal Quantization 8 bits I, 8 bits Q No Automatic Gain Correction (AGC). Fi Stage Mixer Properties Tunability: None Fs/4 Mixer. Second Stage Mixer Properties (Used only in multi-carrier configurations) Tunability: Fixed esolution: 00 khz SFD: Ideal Use simplified DDS based on 00 khz raster. XAPP3 (v.0) October 9,

9 Transmit Downlink Design & Implementation Transmit Downlink Design & Implementation Performance equirements Spectral Mask equirements The spectral mask requirements used in the digital front-end design are derived from the LTE (also called E-UTA) emission limits defined in [ef ]. The general LTE emission limits are listed in Table 3, and are summarized from the General LTE Emission Limits from Table and Table of [ef ]. Table 3: General LTE Emission Limits Frequency Offset to Measurement Maximum Power in Measurement Measurement Filter Edge (-3 db cutoff) Bandwidth Bandwidth 0 MHz to 5 MHz -7 dbm -4 dbm 00 khz 5 MHz to 0 MHz -4 dbm 00 khz > 0 MHz -5 dbm MHz Table 4 shows the additional LTE emission limits generated from Table and Table of the same volume [ef ]. Table 4: Additional LTE Emission Limit Frequency Offset to Measurement Filter Edge (-3 db cutoff) The maximum BS power is 43 dbm for 5-MHz carrier and 46 dbm for 0-MHz, 5-MHz, and 0-MHz carrier, given in the Table 4.6 of [ef 3]. The spectral mask requirement for 5-MHz, 0-MHz, 5-MHz, and 0-MHz bandwidths, respectively, can be calculated given the combined general LTE emission limits and the additional LTE emission limits shown in these tables. Select the most stringent requirement of the four plus 5 db as the spectral emission mask, so enough margins are guaranteed and the design for various bandwidths configurations can share the same channel filter. The spectral mask requirements are listed in Table 5. Table 5: Spectral Mask equirements for LTE (5/0/5/0 MHz BW) Adjacent Channel Leakage atio Maximum Power in Measurement Bandwidth Measurement Bandwidth 0 MHz to MHz BW = 5 MHz -5 dbm 30 khz For Δf Within the ange BW = 0 MHz -3 dbm 00 khz BW = 5 MHz -5 dbm 00 khz BW = 0 MHz -6 dbm 00 khz > MHz -3 dbm MHz Minimum Attenuation Attenuation with 5 db Margin 0 MHz to MHz MHz to 0 MHz > 0 MHz 5 67 Adjacent Channel Leakage atio (ACL) is defined as the ratio of the in-band power to the power in adjacent LTE carriers. XAPP3 (v.0) October 9,

10 Transmit Downlink Design & Implementation The power in an adjacent channel is measured with a rectangular filter with a bandwidth equal to 80 khz transmission bandwidth configuration (N B ), centered on the fi or second adjacent channel (correspong to ACL and ACL). For 5-MHz, 0-MHz, 5-MHz, and 0-MHz LTE carriers, N B is equal to 5, 50, 75, and 00, respectively. Therefore, the correspong rectangular filter bandwidth is 4.5-MHz, 9-MHz, 3.5-MHz, and 8-MHz, respectively. The minimum requirement is listed in the section of 3GPP TS [ef ]. The limits for ACL and ACL are both 45 db. In the reference design, 60 db is specified as the minimum ACL requirement to provide 5 db margin. Error Vector Magnitude For an LTE system, the reference point in the receiver for Error Vector Magnitude (EVM) measurement is at the point after the Cyclic Prefix (CP) removal, FFT, and subcarrier amplitude and phase correction, as shown in Figure 3. X-ef Target - Figure 3 Pre/Post FFT Time/Frequency Sync eference Point for EVM Measurement Base Station Under Test Cyclic Prefix emoval FFT Pre Sub-carrier Amplitude/Phase Correction Symbol Detection/ Decog Figure 3: eference Point for EVM Measurement on an LTE System X3_03_0008 The basic unit of EVM measurement is defined over one subframe in the time domain ( ms) and one resource block which contains data subcarriers (80 khz) in the frequency domain for frame structure type. To test against the EVM requirements, the oot Mean Square (MS) average of individual EVM is calculated over 0 consecutive downlink subframes (0 ms) and all allocated resource blocks in the frequency domain for both FDD and TDD frame structure type. This can be expressed in Equation as: EVM 0 Ni = 0 i j N = = i i= EVM i, j Where: N i EVM i j is the number of resource blocks Equation, is the EVM for i th subframe and j th resource block. For a more detailed definition, refer to section 6.8. of the 3GPP T v0.7. (007-0) [ef ]. Separate EVM requirements are specified for different modulation schemes: For 64 QAM modulation, a range of 7 ~ 8% is the proposed EVM requirement. XAPP3 (v.0) October 9,

11 Transmit Downlink Design & Implementation For 6 QAM and QPSK,.5% and 7.5% are the proposed minimum performance requirements. Note: These figures are for the total system EVM, which includes the digital and analog portion. This application note uses the minimum requirements that EVM % at 8 db PAP, 4% at 7 db PAP, and 7% at 6 db PAP for digital portion and single carrier configurations. Digital Up Converter Architecture This section describes the detailed architecture of major modules in the digital up-converter. Figure 4 shows the overview block diagram of the DUC. X-ef Target - Figure Single-ate Channel Filter Interpolation Filtering Mixing and Combining (Multi-carrier only) Interpolation Filtering Fractional esampling (x5mhz only).88 Figure 4: Digital Up Converter Architecture X3_04_0008 Single ate Channel Filter The baseband data fi has to pass the channel filter so that the out-of-band power is attenuated to meet the spectral mask requirements. Because the LTE baseband signal is OFDM-based, the power spectral density (PSD) of the input signal to the channel filter already has a natural attenuation starting from the edge of the occupied bandwidth (i.e., 90% of the total channel bandwidth). As shown in Figure 5, for 0-MHz bandwidth configuration, the PSD at 0-MHz frequency point is less than -30 db compared to that at active bins. Similar PSD characteristics are observed for the 5-MHz, 0-MHz, and 5-MHz bandwidth configurations. To ensure the signal at the output of the channel filter can be down by up to 67 db (as summarized in Table 6) outside the desired bandwidth, the channel filter needs to support additional ~40 db attenuation. X-ef Target - Figure 5 Figure 5: PSD of the Baseband LTE Signal for 0-MHz Bandwidth XAPP3 (v.0) October 9, 008

12 Transmit Downlink Design & Implementation Table 6 shows some useful properties for all four bandwidth settings, such as the number of usable subcarriers, subcarrier spacing, occupied bandwidth, and the ratio between occupied and total bandwidth. The DC subcarrier is unused. The following numbers are important when it comes to decig the specification for the channel filter: The passband for the channel filter (F pass ) must be at least BW occupied /. The stopband (F stop ) should be BW total /. Because the normalized passband and stopband frequencies, i.e., ω pass = F pass /(F s /)and ω stop = F stop /(F s /), respectively, are identical for the four bandwidths, the same channel filter can be shared across configurations. Table 6: Properties for Different Carrier Bandwidth Settings Total BW (BW total ) (MHz) Fs () Usable Subcarriers Subcarrier Spacing (khz) Occupied BW (BW occupied ) (MHz) BW occupied / BW total * 00% % % % % Table 7 summarizes the channel filter design parameters. It is a single-rate filter with a total of 8 taps. A channel filter with a rate change of can be designed; however, the filter order can double (~60 taps) and does not necessarily result in an efficient implementation. The magnitude response of the channel filter is shown in Figure 6, where the filter coefficients have been quantized to 8 bits. The F pass used in the W pass calculation is 9.05 MHz, instead of 9 MHz. It makes the filter requirements more stringent (one more tap than if using 9 MHz) but it also ensures that the signal carried at the last active data bin can pass through. Also, this creates an odd numbers of taps and is preferable in an efficient filter implementation when it comes to speed and area consumption. Table 7: Filter Parameters for the Channel Filter BW (MHz) 5, 0, 5, 0 ω pass ω stop Apass (=9.05/(30.7/)) 0.65 (=0.0/(30.7/)) Astop # Taps XAPP3 (v.0) October 9, 008

13 Transmit Downlink Design & Implementation X-ef Target - Figure 6 0 Magnitude esponse of Channel Filter db Interpolation Filtering Frequency (MHz) Figure 6: Magnitude esponse of Single-ate Channel Filter After the channel filter, a cascade of interpolation filters follows to remove the aliasing effect produced by up sampling. The majority of the interpolation filtering chain is implemented using a cascade of halfband filters. Halfband filters are a type of FI filter where its transition region is centered at one quarter of the sampling rate, Fs/4. The end of its passband and the beginning of the stopband are equally spaced on either side of Fs/4. When implementing an interpolation filter with a rate of two, the halfband filter is often the chosen structure of choice, because it requires much less computational power (and thus less hardware) for a filter realization. This results from the fact that every odd indexed coefficient in the time domain is zero except the center tap and even indexed coefficients are symmetric. In x5, x0, and x0 MHz BW configurations, the desired sampling rate (.88 MHz) can be achieved by using a cascade of halfband filters. For x5 MHz, a rate 4/3 fractional resampler follows the halfband filters to convert the sampling rate from 9.6 to.88. The main difference between the single carrier and multi-carrier configurations is that the interpolation filtering process for the multi-carrier configurations includes a mixing and carrier combining stage. For the x0 and 4x5 MHz bandwidth, this stage frequency shifts individual carriers to their relative positions, [-5, 5] and [-7.5, -.5,.5, 7.5] MHz, respectively, in a 0-MHz bandwidth centered at 0 MHz. The composite signal is then processed with further halfband filters. For the x5 MHz, two carriers are fi shifted to [-.5,.5] MHz in a 0-MHz bandwidth centered at 0 MHz before the later halfband filtering. All filters were designed using the MATLAB Filter Design and Analysis Tool (FDATool). The seven reference designs share a similar filtering structure. The halfband interpolation filter parameters are identical. Table 8 summarizes the filter parameters for easy referencing and comparison. XAPP3 (v.0) October 9,

14 Transmit Downlink Design & Implementation Table 8: Filter Parameters for eference Design Configurations Filter x5 MHz Configuration Fs () Fpass (MHz) Fstop (MHz) Apass Astop The interpolation filtering chain for the x5 MHz configuration is shown in Figure 7. # Taps HB # HB # HB # HB # Fractional esampler Each filter is a halfband interpolation filter with parameters as listed in Table 8. The equiripple halfband lowpass input parameters (in FDATool) are Fs, Fpass, and Apass. The passband cutoff frequency for all four halfband filters was set to.5 MHz to protect the entire 5 MHz band and remove the aliasing component completely. The number of taps is the length of the smallest filter that satisfies the requirements specified by the input parameters. X-ef Target - Figure HB # 5.36 HB # 30.7 HB # HB #4.88 (3 taps) ( taps) (7 taps) (7 taps) Figure 7: Interpolation Filter Structure for x5 MHz Configuration X3_07_0008 x0 MHz Configuration The interpolation filtering chain for the x0 MHz configuration is shown Figure 8 and the filter parameters are listed in Table 8. Because the passband cutoff frequencies (after normalizing to the filter sample rates) and the passband ripple for HB#, HB#, and HB#3 are identical to the ones for the x5 MHz configuration, the resultant filter coefficients are identical. The throughput requirement for each filter is doubled in implementation because the sample rates at each stage are doubled (see DUC Implementation section for further details). X-ef Target - Figure HB # 30.7 HB # 6.44 HB #3.88 (3 taps) ( taps) (7 taps) Figure 8: X3_08_0008 Interpolation Filter Structure for x0 MHz Configuration x5 MHz Configuration The interpolation filtering chain for the x5 MHz configuration is shown in Figure 9, and the filter parameters are listed in Table 8. A fractional resampler with the rate of 4/3 is required to convert from the 9.6 rate to the desired.88 rate. To design the resampler, the standard polyphase filter design technique is used. The sampling frequency Fs is set to = XAPP3 (v.0) October 9,

15 Transmit Downlink Design & Implementation The passband frequency is set to 7.5 MHz to protect the entire 5 MHz band. The stopband frequency is =84.66 MHz to remove the aliasing image. X-ef Target - Figure HB # HB # 9.6 Fractional esampler P/Q = 4/3.88 x0 MHz Configuration (3 taps) ( taps) (9 taps) Figure 9: Interpolation Filter Structure for x5 MHz Configuration X3_09_0008 Figure 0 shows the interpolation filtering chain for the x0 MHz configuration, and the filter parameters are listed in Table 8. X-ef Target - Figure HB # 6.44 HB #.88 (3 taps) ( taps) Figure 0: Interpolation Filter Structure for x0 MHz Configuration After normalizing to the sample rate, the filter coefficients are identical to those in the correspong filter for the x0 MHz and x5 MHz configurations. x5 MHz Configuration X3_0_0008 Figure shows the interpolation filtering chain for the x5 MHz configuration. X-ef Target - Figure Complex Channels 7.68 HB # Carrier Mixing & Combining to 0 MHz BW 5.36 HB # 30.7 HB # 6.44 HB #3.88 (3 taps) Carriers Centered at [-.5,.5] MHz (3 taps) ( taps) (7 taps) X Figure : Interpolation Filter Structure for x5 MHz Configuration One major difference here from all the single carrier configurations is that signals from two complex channels need to be combined together to a total allocated bandwidth of 0 MHz. Because a zero IF architecture was assumed, two individual carriers are shifted to fixed frequencies at -.5 and.5 MHz before combining. This simplifies the mixer design as the whole 0-MHz BW is centered at zero so that the multi-carrier mixer can be placed at the lowest possible sample rate. This helps to achieve a significant hardware resource saving. In the case of non-zero IF architecture, it requires a mixer at the end of the DUC chain (at the highest sample rate) to support the capability to shift to any frequencies. After channel filtering, signals from two complex channels enter the fi halfband filter and are up-sampled to This is the earliest point that two carriers are able to be combined together without triggering any aliasing effect because (F s BW individual_carrier ) is greater than BW individual_carrier. Here the sampling rate F s is 5.36 MHz and BW individual_carrier is 5 MHz. XAPP3 (v.0) October 9,

16 Transmit Downlink Design & Implementation After the mixing and combining process, the composite signal is treated as data from one carrier so that the rest of the halfband filters only require supporting a single complex channel. The PSD for x5 MHz LTE data after multi-carrier mixing is shown in Figure. X-ef Target - Figure 0 Power Spectral Density for LTE 5.36MHz Watts/Hz Frequency (MHz) Figure : PSD after Multi-Carrier 5.36 MHz for x5 MHz Configuration The resource trade-off is an important consideration when designing multi-carrier filter structures. Pushing the mixer and combiner to the earlier stage in the DUC chain will increase the complexity of the polyphase filters that are to follow. In this example, instead of using the -tap halfband interpolator as shown in x5 MHz configuration in Figure 7, this architecture requires a 3-tap halfband filter immediately after the mixer to support the (doubled) 0 MHz total BW. This halfband filter has the same specification as the fi filter immediately following the channel filter (both are HB #), as their normalized passband frequencies are equivalent. The passband of the rest of the halfband filters is doubled. The advantage is that the filtering process only needs to apply to one complex channel instead of two, if mixing and combining at the later stage. The filter parameters are listed in Table 8. The mixer and combiner designs are detailed in Multi-Carrier Mixing and Combining, page 4. x0 MHz Configuration Figure 3 shows the interpolation filtering chain for the x0 MHz configuration and the filter parameters are listed in Table 8. Similar to the x5 MHz configuration, signals from two complex channels are shifted to fixed frequencies at -5 MHz and 5 MHz before combining, and this is done at the lowest possible sample rate domain 30.7 MHz. Again, instead of using the -tap halfband interpolator, this architecture requires a 3-tap halfband filter after the mixer to support 0 MHz total BW. This halfband filter has the same specification as the fi filter immediately following the channel filter (both are HB #). XAPP3 (v.0) October 9,

17 Transmit Downlink Design & Implementation X-ef Target - Figure 3 Complex Channels 5.36 HB # (3 taps) Carrier Mixing & Combining to 0 MHz BW Carriers Centered at [-5, 5] MHz 30.7 HB # (3 taps) 6.44 HB # ( taps) Figure 3: Interpolation Filter Structure for x0 MHz Configuration.88 X3_3_0008 Figure 4 shows the PSD for the x0 MHz LTE data after multi-carrier mixing. X-ef Target - Figure 4 0 Power Spectral Density for LTE 30.7MHz Watts/Hz Figure 4: PSD after Multi-Carrier 30.7 MHz for x0 MHz Configuration 4x5 MHz Configuration Frequency (MHz) Figure 5 shows the interpolation filtering chain for the 4x5 MHz configuration and the filter parameters are listed in Table 8, page 4. X-ef Target - Figure 5 4 Complex Channels 7.68 HB # 5.36 HB # Carrier Mixing & Combining to 0 MHz BW 30.7 HB # 6.44 HB #.88 (3 taps) Figure 5: ( taps) 4 Carriers Centered at [-7.5, -.5,.5, 7.5] MHz (3 taps) Interpolation Filter Structure for 4x5 MHz Configuration ( taps) X The multi-carrier output signal has a total allocated bandwidth of 0 MHz. After channel filtering, signals from four complex channels fi enter two stages of halfband filter and are upsampled to Signals are shifted to fixed frequencies at -7.5 MHz, -.5 MHz,.5MHz, and 7.5 MHz before combining. Figure 6 shows the PSD. This is the earliest point that four carriers are able to be combined without any aliasing effect because > 0. After the mixing and combining process, the XAPP3 (v.0) October 9,

18 Transmit Downlink Design & Implementation signals are treated as data from one carrier and the rest of the halfband filters operate on one complex channel. X-ef Target - Figure 6 0 Power Spectral Density for LTE 30.7MHz Watts/Hz Figure 6: PSD after Multi-Carrier 30.7 MHz for 4x5 MHz Configuration DUC Filtering Overall Gain Frequency (MHz) The single rate channel filter was designed to have a unity gain (the sum of all the coefficients is ). The halfband interpolators were designed with a filter gain of (center tap equals to ), so that with the zero insertion between samples in the up-sampling process, the average output signal power is maintained to be the same as that of the input signal. Therefore, for x5, x0, and x0 MHz configurations, the DUC filtering process has an overall gain of 0 db. For x5 MHz configuration, the fractional resampling process generates a gain of.04. This results in an overall gain of 0.86 db. For multi-carrier configurations, the up-sampling process for each carrier also preserves a 0 db gain. With N active carriers, the composite output average amplitude is sqrt(n) times the individual input signal average amplitude. For example, in four carrier [ 0 ] configuration, the output signal average amplitude is expected to be sqrt(3).73 higher than the average amplitude of the input signal from each carrier. Multi-Carrier Mixing and Combining This section describes the architecture of the multi-carrier mixing and combining that is embedded in the interpolation filter chains for the x5, x0, and 4x5 MHz configurations. In this zero-if DUC architecture, this operation frequency shifts individual carriers to their relative positions in a given bandwidth centered at 0 MHz. The architecture of the mixing and combining module used in the 4x5 MHz configuration is described as an example. Figure 7 illustrates the 4-channel mixing and combining module. XAPP3 (v.0) October 9,

19 Transmit Downlink Design & Implementation X-ef Target - Figure 7 c0 Channel 0 Complex Input X c Channel Complex Input X c + 4-Channel Composite Complex Output Channel Complex Input X c3 Channel 3 Complex Input X X3_7_0008 Figure 7: 4-Channel Mixing and Combining Module The input to the mixing and combining module is four complex signals sampled at The mixer multiplies four input signals x 0 (n), x (n), x (n), and x 3 (n) by exp(jω 0 n), exp(jω n), exp(jω n), and exp(jω 3 n), respectively, and then sums the product up to generate a complex composite output signal, where the ω k represent the carrier center frequencies. The real (I channel) and imaginary (Q channel) components of the output signals are given by Equation and Equation 3: 3 y ( n) = ( x ( n)cos( ω n) x sin( ω n)) I Ik k Qk k k = 0 Equation 3 y ( n) = ( x ( n)cos( ω n) + x sin( ω n)) Q Qk k Ik k k = 0 Equation 3 Similar to the DDC, the rasterized DDS is used to generate the sine and cosine waveforms used in the above equations. The detailed discussion on the rasterized DDS concept can be found in the Multi-Carrier Mixing and Combining. Crest Factor eduction Architecture The LTE DFE downlink design uses a peak cancellation crest factor reduction (PC-CF) method to reduce the high PAP signal at the output of the DUC. This section gives an overview of the PC-CF algorithm and architecture. For more detailed information on the PC- CF, refer to [ef 4]. XAPP3 (v.0) October 9,

20 Transmit Downlink Design & Implementation Algorithm Overview The peak cancellation method of CF reduces the peak to average power ratio (PAP) of a signal by subtracting spectrally shaped pulses from signal peaks that exceed a specified threshold. The cancellation pulses are designed to have a spectrum that matches that of the CF input signal and, consequently, introduces negligible out-of-band interference. Each cancellation pulse is rotated to match the phase of the correspong signal peak. The magnitude of a given cancellation pulse is set equal to the difference between the correspong signal peak magnitude and the desired clipping threshold. This reduces the signal peak magnitudes to the threshold value while preserving the signal phase. Figure 8 illustrates the peak cancellation process in the time domain. Note: The blue curve shows a section of the input signal magnitude before the CF iteration. The cyan horizontal line overlaid on the plot indicates the clipping threshold. Any peak that exceeds this threshold is a candidate for cancellation. The magenta curve shows the magnitude of the output signal after subtracting the cancellation pulse from the input signal. X-ef Target - Figure x 04 Signal Magnitude Before and After CF Iteration Input Output 3 Signal Magnitude Architecture Time (Samples) x 0 4 Figure 8: Time Domain View of Peak Cancellation Figure 9 shows a block diagram of the PC-CF algorithm. Peaks in the input signal are detected and cancelled to produce a reduced PAP signal. The peak detect block works on the signal magnitudes to produce a peak location indicator along with magnitude and phase information for each peak. The difference between the peak magnitudes and the clipping threshold is generated by the peak scaling block. The magnitude difference is combined with the phase information to produce the complex weighting that is used to scale the cancellation pulse coefficients. It is this scaling that replaces the more computationally intense convolution that is used in the noise shaping method. Each cancellation pulse generator (CPG) outputs an unscaled version of the cancellation pulse waveform aligned with a peak location. Each CPG can cancel only one peak at a time. The length of the cancellation pulse combined with the number of CPGs determines the rate at which signal peaks can be cancelled. The allocator block controls the distribution of CPGs to incoming peaks. When a new peak is detected the allocator assigns an available CPG to the cancellation of that peak. If all CPGs are busy when a new peak is detected, it will not be cancelled. Multiple iterations of the algorithm are necessary to eliminate the peaks that were not cancelled during an earlier pass of the XAPP3 (v.0) October 9,

21 Transmit Downlink Design & Implementation algorithm. The final algorithm step is to subtract the summation of the CPG outputs from a delayed version of the input signal. In the 3GPP LTE reference design, two iterations of the PC-CF algorithm were used: For single carrier configurations, each iteration consists of three CPGs to achieve acceptable performance, while resulting in slightly lower area than the multi-carrier configuration. For multi-carrier configurations, six CPGs were used in the fi iteration and another 3 CPGs in the second iteration to eliminate most of the peaks and achieve a satisfactory output PAP. X-ef Target - Figure 9 High PAP Signal Delay + + educed PAP Signal Peak Detect Mag Phase Peak Scaling Peak Locations Allocator CPG # X CPG # X Sum CPG #N X Figure 9: Block Diagram of PC-CF Method (One Iteration) X3_9_0008 Designing Cancellation Pulse The cancellation pulse coefficients can be obtained using any preferred filter design methodology and are computed offline before being written to the PC-CF. Memory that is external to the design can be used to store multiple sets of cancellation pulse coefficients correspong to predetermined carrier configurations. Transferring a selected set of coefficients into the PC-CF memory can be handled with some simple multiplexing circuitry. For multi-carrier configurations, it is useful to fi design a prototype filter that is matched to the spectrum of a single carrier. Frequency shifted replicas of the prototype filter are then placed at each carrier center frequency before being summed to create a composite multiband filter. In the 3GPP LTE reference design, the prototype filter was obtained using the firls function in MATLAB. The order of the filter is fixed at 54 (55 taps). Table 9 lists the passband and stopband frequency of the prototype filter. The command prototype_filter_coeff = firls(n, [0 Fpass Fstop Fs/]/(Fs/), [ 0 0], [Wpass Wstop]) generates the prototype filter coefficients. Table 9: Prototype Filter for Designing Cancellation Pulse Coefficients Bandwidth (MHz) Fs () Fpass (MHz) Fstop (MHz) Wpass Wstop Filter Order (N) XAPP3 (v.0) October 9, 008

22 Transmit Downlink Design & Implementation Table 9: Prototype Filter for Designing Cancellation Pulse Coefficients (Cont d) Bandwidth (MHz) Fs () Fpass (MHz) Fstop (MHz) Wpass Wstop Filter Order (N) To generate the cancellation pulse coefficients, fi the prototype filter coefficient is rotated to respective carriers, for example, multiply it by exp(j**pi*fc*k/fs) where: Fc = 0 for single-carrier configurations, Fc = [-.5,.5] in x5 MHz case, Fc = [-5, 5] in x0 MHz case Fc = [-7.5, -.5,.5, 7.5] in 4x5 MHz case, k is integer, from -# of taps/ to # of taps/. Then, sum all the rotated coefficients together to obtain the CP coefficients. System Performance This section summarizes the performance of the LTE transmit downlink using PC-CF method. In all cases, the length of the cancellation pulse is 55, and the cancellation pulse was designed using the least squares filter design method, for example, the firls function in MATLAB, with F pass = 0.9*BW/ for 0, 5, and 0 MHz BW, F pass = 0.8*BW/ for 5 MHz BW, and F stop = BW/. The detailed parameters are described in the Designing Cancellation Pulse. esults are presented based on using two iterations of the algorithm, because no improvement was observed using three or more iterations. Single-Carrier Configuration Table 0 shows the output PAP and PAP reduction (dpap) versus EVM performance of the PC-CF algorithm for single carrier configurations. The number of cancellation pulse generators is three for both iterations. All PAP results are referenced at the 0.0% probability of clip point. With 8 db PAP target, less than % EVM can be achieved. With 7 db PAP target, the EVM is below 4%. The EVM is below 7% when the output PAP is 6 db. ACL and ACL meet the 60 db requirement. Table 0: PC-CF Performance for Single-Carrier Configurations Configuration Input PAP Output PAP dpap EVM (%) ACL/ACL x / x / Compared to other CF methods, such as the Peak Windowing CF (PW-CF) and Noise Shaping CF (NS-CF), it can be concluded that the PC-CF performance is slightly better than that of the NS-CF algorithm, and significantly better than the PW-CF algorithm. Figure 0 shows the performance comparison based on x0 MHz configuration. XAPP3 (v.0) October 9, 008

23 Transmit Downlink Design & Implementation X-ef Target - Figure CF Performance Comparison for 0 MHz BW PW-CF NS-CF ( iterations) PC-CF ( iterations) Output PAP EVM (%) Figure 0: Performance Comparison among Several CF Methods (x0 MHz) The PW-CF method is described in [ef 5]. The NS-CF method is described in [ef 6]. A link to this document can be found in eferences, page 87. Two iterations are used for both the NS-CF and PC-CF methods, while PW-CF used a 40 tap window. Given the same EVM, the PC-CF method can provide the highest PAP reduction of the three. The following three figures are based on x0 MHz configuration: Figure shows a plot of the CCDF for the CF input and output at the 4% EVM operating point for x0 MHz configuration. The curve demonstrates that the PAP reduction is around.7 db at the 0.0% (E-4) probability of clip point. Figure shows the power spectral density (PSD) estimates of the CF input and output for the single carrier at the 4% EVM operating point. Figure 3 shows the constellation plot for 64-QAM modulation. XAPP3 (v.0) October 9,

24 Transmit Downlink Design & Implementation X-ef Target - Figure CCDF 0 0 Before Clipping: PAP (@E-4) = 9.67 db 0 - After Clipping: PAP (@E-4) = 6.95 db Clipping Probability PAP Figure : CCDF of CF Input and Output with Two Iterations of PC-CF (x0 MHz) X-ef Target - Figure 0-0 Power Spectral Density for LTE IF before CF after CF SEM -40 Watts/Hz Frequency (MHz) Figure : PSD of CF Input and Output with Two Iterations of PC-CF (x0 MHz) XAPP3 (v.0) October 9,

25 Transmit Downlink Design & Implementation X-ef Target - Figure 3 Figure 3: Constellation Plot for 64 QAM (x0 MHz) 4% EVM Dual-Carrier Configuration Table shows the output PAP and PAP versus EVM performance of the PC-CF algorithm when using two iterations for the dual carrier configurations (x5 and x0). The PAP of the CF input signal is 9.5 db and 9.55 db at the 0.0% probability of clip point for x5 and x0 BW options, respectively. The number of cancellation pulse generators is six for the fi iteration, and three for the second iteration. Both ACL and ACL meet the 60 db requirement. For the PAP reduction, fewer than % EVM can be achieved with 8 db output PAP. With 7 db PAP target, the EVM is within 4%. When the output PAP is 6 db, the EVM is over 7%, which is higher than the single carrier case due to the destructive effect generated from the adjacent carrier. Table : PC-CF Performance for Dual-Carrier Configurations Configuration Input PAP Output PAP dpap EVM (%) ACL/ACL x / x / XAPP3 (v.0) October 9,

26 Transmit Downlink Design & Implementation Figure 4 shows a plot of the CCDF for the CF input and output when the output PAP is 7 db for x0 MHz configuration. The EVM at 0.0% clipping probability operating point is 3.8%. X-ef Target - Figure 4 CCDF 0 0 Before Clipping: PAP (@E-4) = 9.55 db 0 - After Clipping: PAP (@E-4) = 7.00 db Clipping Probability PAP Figure 4: CCDF of CF Input and Output with Two Iterations of PC-CF (x0 MHz) Figure 5 shows the PSD estimates of the CF input and output for the x0 MHz configuration. X-ef Target - Figure Power Spectral Density for LTE IF before CF after CF SEM -40 Watts/Hz Frequency (MHz) Figure 5: PSD of CF Input and Output with Two Iterations of PC-CF (x0 MHz) XAPP3 (v.0) October 9,

27 Transmit Downlink Design & Implementation Four-Carrier Configuration Table shows the output PAP and dpap versus EVM performance of the PC-CF algorithm when using two iterations for the 4x5 MHz configuration. Because the reference design offers the option to turn on and off each carrier, this configuration includes possible scenarios like three active carriers with one non-adjacent carrier, such as [ 0 ] or [ 0 ], or two non adjacent carriers, such as [ 0 0 ], and the typical four active carriers [ ] carrier settings. Similar to the dual carrier configuration, the number of cancellation pulse generators is six for the fi iteration, and three for the second iteration. Table : PC-CF Performance for 4x5MHz Configuration Configuration Four Active Carriers for example [ ] Three Active Carriers with One Nonadjacent Carrier for example [ 0 ] or [ 0 ] Two Nonadjacent Carriers for example [ 0 0 ] Allocation Spacing None or [0, 5] Input PAP Output PAP dpap In the 4x5 MHz configuration the output PAP vs. EVM performance is worse than all other configurations, though the ACL and ACL still meet the 60 db requirement. In four active carriers setting, although less than % EVM can still be achieved with 8 db PAP and 4% EVM for 7 db output PAP, the CCDF curve for 6 db output PAP will be curved outwards to high PAP region at e-5 and e-6 clipping probability as shown in Figure 7 (instead of a straight line down as the red curve in Figure 6). This is non-ideal as this causes a problem for processing in the digital pre-distortion (DPD) block to follow. Consequently, the minimal achievable (stable) output PAP is approximately 6.5 db. EVM (%) ACL/ACL / None / [0, 5] None / [0, 5] XAPP3 (v.0) October 9,

28 Transmit Downlink Design & Implementation X-ef Target - Figure CCDF 0 - Before Clipping: PAP (@E-4) = 9.65 db After Clipping: PAP (@E-4) = 7.0 db Clipping Probability PAP Figure 6: CCDF of CF Input and Output with [ ] Carrier Configuration, 4% EVM X-ef Target - Figure 7 CCDF 0 0 Before Clipping: PAP (@E-4) = 9.70 db 0 - After Clipping: PAP (@E-4) = 5.98 db Clipping Probability PAP Figure 7: Non-ideal CCDF Curve with [ ] Carrier Configuration In any non-adjacent carrier setting, the allocation spacing technique must be used to reduce the EVM given certain output PAP. For example, in a [ 0 ] or [ 0 ] case, 5.% EVM was seen to achieve 7 db of output PAP, but with the help of allocation spacing, the EVM metric can be reduced to 4.8%, almost 0.3% improvement. The wo case scenario happens in two active carrier with two middle carriers inactive setting, such as [ 0 0 ]. In this case, to achieve 7 db output PAP causes almost 0% EVM. This is much improved with the allocation spacing technique, and nearly 4% improvement is seen at 7 db output PAP operation point. The optimal allocation spacing is [0, 5], meaning space of 0 is used for the fi iteration and 5 is used for the second iteration. XAPP3 (v.0) October 9,

29 Transmit Downlink Design & Implementation Figure 8 illustrates the input and output PSD for [ 0 0 ] configuration at a fixed 4% of EVM. X-ef Target - Figure Power Spectral Density for LTE IF before CF after CF SEM -40 Watts/Hz Frequency (MHz) Figure 8: PSD of CF Input and Output with [ 0 0 ] Carrier Config, 4% EVM Implementation The transmit downlink was implemented using Xilinx System Generator version 0... The top-level GUI lets you select from one of seven carrier configurations as shown in Figure 9. The DUC and CF module settings under the mask change accorgly based on different carrier configurations. The Power Meter block is an optional module and can be turned on and off from the top-level GUI. X-ef Target - Figure 9 Figure 9: System Generator Top-Level GUI of Transmit Downlink Design XAPP3 (v.0) October 9,

30 Transmit Downlink Design & Implementation Under the mask is the block diagram of transmit downlink design. Figure 30 shows the diagram of the 4x5 MHz configuration as an example. There are three major blocks in the design: a DUC configuration subsystem, a rate and data format conversion block, and a PC-CF module (pc_cfr_3x), which are described in the following subsections. X-ef Target - Figure 30 tx_data In dout_i _i dout_i reinterpret Out duc _i duc _i In vin vin dout_q _q dout_q reinterpret Out duc_q duc _q In reset reset vout vin vout Out duc _vout 0 In gain duc _valid gain 0 In gain _we gain_we power 3 rate and data format conversion Out power power 0 In gain_ch _out Out reset gain _ch DUC Configurable Subsystem DUC_4x5 data_i_in data_q_in data_i_out reinterpret Out cfr_i cfr_i data_sync thresh In reinterpret threshold threshold data_q_out reinterpret Out cfr_q -C- In alloc_spacing cfr_q alloc _spacing -C- In alloc_spacing alloc _spacing 55 In filter _numtaps filter _numtaps data_valid Out cfr_vout cfr_valid In filter _ram_addr filter _ram _addr coef coefficients In filter _ram _data filter _ram_data In filter _ram_we ce_3_out Out ce_3_out filter _ram _we ce_3_out reset pc_cfr_3x Out reset3 3 Figure 30: System Generator Block Diagram of Transmit Downlink for 4x5 MHz Configuration DUC Implementation The DUC was implemented with a heavy reliance on the FI Compiler v4.0. The top-level DUC architecture uses a configurable subsystem to select from one of seven unique architectures that are stored in a Simulink library. See the Xilinx reference, System Generator for DSP User Guide, elease 0.. [ef ], for a description of using configurable subsystems in System Generator designs. Because the carrier and BW configuration are determined by the choice in the top-level GUI as shown in Figure 9, the Block Choice menu item changes automatically and the user does not need to (and is not able to) make a selection on this level. XAPP3 (v.0) October 9,

31 Transmit Downlink Design & Implementation Figure 3 shows the DUC configuration subsystem. X-ef Target - Figure 3 Figure 3: System Generator DUC Configuration Subsystem Figure 3 shows another GUI that allows you to add or remove the gain block on the DUC configuration subsystem level if you choose any of the single carrier configurations (x5, x0, x5 or x0 MHz) on the top-level. The default setting is off. For multi-carrier cases, the gain block always exists and cannot be removed. This is because the gain block also can be used to turn on and off certain carriers. The seven architectures are based on the structures described in the Digital Up Converter Architecture, page. The following diagrams provide block diagrams of two configurations: Figure 33, page 3 shows the System Generator block diagram for the x5 MHz configuration. Figure 34, page 3 shows the System Generator block diagram for the 4x5 MHz configuration. In the single-carrier configurations, the data flow from one module to the next is handled in a Time Division Multiplexing (TDM) fashion except for the last module. The valid in (vin) and valid out (vout) signal is paired with TDM data input () and TDM data output (dout), respectively, to indicate the signal availability. Because the output of the DUC needs to feed into the CF module, the I and Q data of the last module are separate and use some time division demultiplexing logic. There is a higher level of design complexity in the multi-carrier configurations due to the existence of the mixer. For all the modules before the mixer, the data input and output stream XAPP3 (v.0) October 9,

32 Transmit Downlink Design & Implementation is handled in a TDM manner. However, the efficient mixer design and the final few FI compilers sometimes generate non-uniform output data, and some data scheduling and FIFO are required in these special situations. X-ef Target - Figure 3 Figure 3: GUI for Single Carrier DUC Configuration X-ef Target - Figure 33 dout dout dout dout dout_i dout _i vin vin vin 3 reset vin gain vin vin vout ch dout_q dout _q 4 gain 5 reset vout reset vout reset vout reset ch reset vout 3 vout gain _we h_channel Gain Stage SC h_ch h_ch h_frac _ch 6 no_gain_stage gain _ch input reg 5 _out I Q valid power 4 power power _meter Figure 33: System Generator Block Diagram of DUC for x5 MHz Configuration X-ef Target - Figure 34 dout vin dout dout dout dout dout dout_i dout _i chin vin vin vout gain vin vin vin vin vout dout_q vin gain_we chin dout _q 3 reset reset chout gain_ch reset vout reset vout reset vout reset vout reset chout reset vout 3 vout h_channel gain _ctrl h_8ch h_8ch mixer h_ch h_ch 4 gain 5 gain _we 5 _out 6 gain _ch input reg I Q valid power 4 power Figure 34: System Generator Block Diagram of DUC for x5 MHz Configuration power _meter XAPP3 (v.0) October 9,

33 Transmit Downlink Design & Implementation Channel Filtering and Interpolation This section summarizes the Filter Compiler 4.0 settings for each filter used in each of the seven configurations in the transmit downlink. In all cases, the number of coefficient sets is equal to one and the reloadable coefficient option is disabled. All filter architectures are based on the systolic multiply accumulate structure with 8-bit signed coefficients. The setting for the coefficient structure is generally set as Inferred except in the x0 and 4x5 MHz cases, where it is set to Non-Symmetric for better resource balancing and speed advantage. The optimization goal is always left at the default setting of Area. The data buffer type and coefficient buffer type are left at the default setting of Automatic. All filters in the design use the and nd control options. Table 3 through Table 9 list the FI compiler settings for x5, x0, x5, x0 x5 x0, x5, x0, and 4x5 MHz configurations. Table 3: FI Compiler Settings for x5 MHz Configuration Parameter Channel Filter st Halfband nd Halfband 3 rd Halfband 4 th Halfband Coefficients h_chan h_duc h_duc h3_duc h3_duc Filter Type Single_ate Interpolation Interpolatio n Interpolatio n Interpolation ate Change Type Integer Integer Integer Integer Integer Interpolation ate Value Number of Channels Effective Input Sample Period Coefficient Structure Inferred Inferred Inferred Inferred Inferred Number of Paths Output Width Optimization Goal Area Area Area Area Area Table 4: FI Compiler Settings for x0 MHz Configuration Parameter Channel Filter st Halfband nd Halfband 3 rd Halfband Coefficients h_chan h_duc h_duc h3_duc Filter Type Single_ate Interpolation Interpolation Interpolation ate Change Type Integer Integer Integer Integer Interpolation ate Value Number of Channels Effective Input Sample Period 6 6 Coefficient Structure Inferred Inferred Inferred Inferred Number of Paths XAPP3 (v.0) October 9,

34 Transmit Downlink Design & Implementation Table 4: FI Compiler Settings for x0 MHz Configuration (Cont d) Parameter Channel Filter st Halfband nd Halfband 3 rd Halfband Output Width Optimization Goal Area Area Area Area Table 5: FI Compiler Settings for x5 MHz Configuration Parameter Channel Filter st Halfband nd Halfband esampler Coefficients h_chan h_duc h_duc h_frac Filter Type Single_ate Interpolation Interpolation Fixed_Fractional ate Change Type Integer Integer Integer Integer Interpolation ate Value 4 Decimation ate Value 3 Number of Channels Effective Input Sample Period Coefficient Structure Inferred Inferred Inferred Inferred Number of Paths Output Width Optimization Goal Area Area Area Area Table 6: FI Compiler Settings for x0 MHz Configuration Parameter Channel Filter st Halfband nd Halfband Coefficients h_chan h_duc h_duc Filter Type Single_ate Interpolation Interpolation ate Change Type Integer Integer Integer Interpolation ate Value Number of Channels Effective Input Sample Period Coefficient Structure Inferred Inferred Inferred Number of Paths Output Width Optimization Goal Area Area Area XAPP3 (v.0) October 9,

35 Transmit Downlink Design & Implementation Table 7: FI Compiler Settings for x5 MHz Configuration Parameter Channel Filter st Halfband nd Halfband 3 rd Halfband 4 th Halfband Coefficients h_chan h_duc h_duc h_duc h3_duc Filter Type Single_ate Interpolation Interpolation Interpolation Interpolation ate Change Type Integer Integer Integer Integer Integer Interpolation ate Value Number of Channels 4 4 Effective Input 6 3 Sample Period Coefficient Structure Inferred Inferred Inferred Inferred Inferred Number of Paths Output Width Optimization Goal Area Area Area Area Area Table 8: FI Compiler Settings for x0 MHz Configuration Parameter Channel Filter st Halfband nd Halfband 3 rd Halfband 4 th Halfband Coefficients h_chan h_duc h_duc h_duc h3_duc Filter Type Single_ate Interpolation Interpolatio Interpolation Interpolation n ate Change Integer Integer Integer Integer Integer Type Interpolation ate Value Number of 4 4 Channels Effective Input 6 3 Sample Period Coefficient Inferred Inferred Inferred Inferred Inferred Structure Number of Paths Output Width Optimization Goal Area Area Area Area Area XAPP3 (v.0) October 9,

36 Transmit Downlink Design & Implementation Table 9: FI Compiler Settings for 4x5 MHz Configuration Parameter Channel Filter st Halfband nd Halfband 3 rd Halfband 4 th Halfband Coefficients h_chan h_duc h_duc h_duc h_duc Filter Type Single_ate Interpolation Interpolation Interpolation Interpolation ate Change Type Interpolation ate Value Number of Channels Effective Input Sample Period Coefficient Structure Multi-Carrier Mixing and Combining Four-Carrier Mixer Integer Integer Integer Integer Integer Non- Symmetric Inferred Inferred Inferred Inferred Number of Paths Output Width Optimization Goal Area Area Area Area Area Figure 35 shows the System Generator block diagram of the four-carrier mixer and combiner. The input data sampling rate is 30.7 and there are eight channel data (I and Q from 4 carriers) coming in from the last FI compiler. With a MHz FPGA clock and the input data throughput of = 45.76, data enters the mixer module in a buy mode. 8 valid TDM samples come in during clock cycles. The data is stored in a FIFO and is read out and mixed with the cosine and sine waveform generated from the raster_dds_4ch block. It requires two DSP48Es for this mixer and combining operation, one for the in-phase output and another for the quadrature output. Because there are still four empty cycles left, one cycle is used for the symmetric round operation by the same DSP48E and no extra logic is required. The final TDM block assembles the resultant I and Q channel data in a TDM format to feed into the next FI compiler. XAPP3 (v.0) October 9,

37 Transmit Downlink Design & Implementation X-ef Target - Figure 35 dout data we empty [empty ] Goto coeff dout_i [FIFO _re] From re %full op_addr 3 reset reset_4 full MAC_I reset reset_gen [_4 ] Goto Data FIFO _i _q dout dout vin if x <8 & ~empty cnt vout vout vin d z - q en egister out en x Counter count from 0~ [a:b] MSB [empty ] From a ~a & ~b b Expression d z - q egister vin cnt cos_sin sin_cos data coeff dout_q TDM reset vout _early raster_dds_4ch [FIFO_re] Goto op_addr vout MAC_Q [_4] From d z - q egister 3 z -7 d z - q egister 4 Figure 35: System Generator Block Diagram of Mixer & Combiner for 4x5 MHz Configuration The top-level System Generator block diagram of the four-carrier DDS is shown in Figure 36. The center frequencies for four carriers are [-7.5, -.5,.5, 7.5] MHz and sampling frequency (Fs) is 30.7 MHz. Because gcd(.5m, 30.7M) = 0k, a raster of 0 khz is required and the total number of elements stored to form a whole sinusoidal wave is Fs/0k = 536. Because 536 is a multiple of 4, minimally a quarter cosine wave is enough to generate the rest of the data sample on a unit circle utilizing the trigonometric relationship. However, with the minimal granularity of the Block Memory size at 04x8K, a half cosine wave can be stored with only block memory with 8-bit output precision. This will also result in less logic usage to generate the full waveform. The sine wave can also be generated from mapping and inverting the correspong cosine wave samples. The dual port AM in Figure 36 was initialized by the vector cos_lut, which is generated from the following script (which is located in the mask of the DUC_4x5 module in the duc_lib.mdl file): % gcd(.5m, 30.7M) = 0k - need raster of 0 khz = 0.0 MHz f = [-7.5, -.5,.5, 7.5]; Fs = 30.7; num_el = Fs/0*0^3; % Total number of element to form a whole sinu wave n = [0: num_el-]; offset = 0.0; % offset by 0 khz to avoid +/- cos_lut = cos(*pi*(offset+n*0.0)/fs); step = mod(f/0*0^3, num_el); % Only need to store quarter wave, % but since each BAM is 04x8, we store half wave (w/o extra resource) % cos(theta) = cos(-theta), sin(theta) = -sin(-theta) % if between 768~535 -> mapped to 767~0 accorgly n = [0: num_el/-]; cos_lut = cos(*pi*(offset+n*0.0)/fs); Note: Another applied technique is that + and - are avoided in this Look-Up Table (LUT). This is done by offsetting the starting sampling point by half of the raster; for example, 0 khz. This way, samples 768 to 535 are symmetric to samples 767 to 0 in absolute magnitude, and a full 8 bit precision can be utilized (Fix 8.7 format instead of Fix 8.6 format which dedicates one bit to represent +). XAPP3 (v.0) October 9,

38 Transmit Downlink Design & Implementation X-ef Target - Figure 36 3 reset en out Counter d z - q mapped from 0~pi to 0~pi sel half wave storage cnt vin reset cnt en base_addr valid step_terminal _count step terminal counter to calculate correspong phase for each channel (between 0~pi ) base_addr cos_addr cos_addr _map base_addr sin_addr cos_addr sin_addr d0z - d Mux 5 sel d0z addra a wea addrb b web A B cos_sin sin_cos sin_addr _map d Mux Dual Port AM z - d z - q 3 vout _early d z - q create vout early signal to trigger the FIFO read operation (sync up the timing between cos /sin and data ) Figure 36: System Generator Block Diagram of asterized DDS (Half Wave Storage Most of the other logic in the rasterized DDS, such as step_terminal_count block (shown in Figure 37) is to generate the baseline address to perform the sine and cosine LUT mapping. The step size (generated from the fixed frequencies [-7.5, -.5,.5, 7.5] is stored in the OM, and an accumulating process is performed based on the step size. When the count reaches above 536; for example, 30.7M/0k, the output is wrapped back to the start producing a modulo (count, 536) operation. X-ef Target - Figure 37 pick the right step size for each channel each step constant stays for clks once the count is over 536 (= 30.7M/0k) wrap the counter result back to the start cnt 3 en [a:b] bit addr z - OM d z - q a b en z - a + b AddSub this loop takes clks overall In Out data _wrap z -9 Delay d z - en q base_addr [a:b] a LSB b ~a & b enable once every clks d z - q reset z - d z - q valid latency for this module = 4 Two-Carrier Mixer Figure 37: System Generator Diagram of Step Terminal Count Block (4x5 MHz Configuration) Figure 38 shows the System Generator block diagram of the dual carrier mixer and combiner. The implementations for the x5 and x0 MHz configurations are similar, so only the x5 MHz implementation is explained. For the x5 MHz configuration, the input data sampling rate is 5.36 and there are 4- channel data (I and Q from two carriers) coming in from the last FI compiler. With a MHz FPGA clock, every six clocks an input data sample enters the mixer module. XAPP3 (v.0) October 9,

39 Transmit Downlink Design & Implementation Four valid TDM data inputs are presented in 4 clock cycles and the data pattern is uniform. The sine and cosine waveforms are generated and TDM ed from the raster_dds_ch block to mix with the input samples. Because it takes four operations/clock cycles to mix and combine data from each carrier for I or Q channel, only a single Multiply-Accumulate (MAC) is required for 4 clock cycles total. No extra logic is needed for symmetric roung. The output from the mixing and combining module is in the TDM format. X-ef Target - Figure 38 3 chin addra a A data scheduling - ensure data and coeff are repeated twice in 4 clks, since real and imag are calculated using the same MAC vin wea sel valid addr addrb B z -7 d0z - ch_index enable mux_sel enb Data AM Delay z - Delay d Mux5 4 reset reset reset_4 reset _gen addr op_cnt cnt cos_sin sel d0z - data coeff dout dout vin reset sin_cos vout z - Delay 4 d Mux op_addr reset vout vout raster_dds_ch MAC z -8 Delay 3 z -0 Delay 6 Figure 38: System Generator Block Diagram of Mixer & Combiner for x5 MHz Configuration Figure 39 shows the top-level System Generator block diagram of the x5 MHz DDS. The center frequencies for two carriers are [-.5,.5] MHz and sampling frequency (Fs) is 5.36 MHz. Because gcd(.5m, 5.36M) = 0k, a raster of 0 khz is required and the total number of element stored to form a whole sinusoidal wave is Fs/0k = 768. In this case, a full cosine wave can be stored with only block memory with 8 bit output precision. The sine wave is generated from mapping and inverting the right cosine wave samples. A similar technique to what was used in the 4x5 MHz configuration is applied to avoid + and - storage in the LUT. This is done by offsetting the starting sampling point by half of the raster, e.g. 0 khz. This results in a full 8 bit precision to be utilized instead of dedicating one bit to represent +. The dual port AM in Figure 39 was initialized by the vector cos_lut, which is generated from the following script (the script can be found in the mask of the DUC_x5 module in the duc_lib.mdl file). % gcd(.5m, 5.36M) = 0k - need raster of 0 khz = 0.0 MHz f = [-.5,.5]; Fs = 5.36; num_el = Fs/0*0^3; % Total number of element to form a whole sinu wave % store full wave since it consists less than 04 elements n = [0: num_el-]; offset = 0.0; % offset by 0 khz to avoid +/- cos_lut = cos(*pi*(offset+n*0.0)/fs); step = mod(f/0*0^3, num_el); XAPP3 (v.0) October 9,

40 Transmit Downlink Design & Implementation X-ef Target - Figure 39 3 reset en out Counter d z - q sel full wave storage cnt vin reset cnt en base_addr valid step_terminal _count step terminal counter to calculate correspong phase for each channel (between 0~pi) d z - q cos_addr base_addr sin_addr sin_addr sin_addr _map d0z - d Mux 5 sel 0 0 addra a A wea addrb b B web Dual Port AM cos_sin sin_cos d0z - d Mux z -3 Delay d z - q 3 vout Figure 39: System Generator Block Diagram of asterized DDS (Full Wave Storage) Figure 40 shows that the step_terminal_count block System Generator diagram for the x5 MHz configuration is very similar to the Four-Carrier Mixer section. It is used to generate the baseline address to perform the sine and cosine LUT mapping. In the x5 MHz case, the step size generated from the fixed frequencies [-.5,.5] is stored in the OM, and an accumulating process is performed based on the step size. Whenever the count reaches above 768, e.g., 5.36M/0k, the output is wrapped back to the start. This is equivalent to a modulo (count, 768) operation. The x0 MHz case is identical to the four carrier configuration with the exception of time delay elements. X-ef Target - Figure 40 pick the right step size for each channel each step constant stays for clks once the count is over 768 (= 5.7M/0k) wrap the counter result back to the start cnt 3 en [a:b] MSB addr z - OM d z - q a b en z - a + b AddSub this loop takes 4 clks overall In Out data _wrap z - Delay d z - en q base_addr [a:b] a LSB ~a & b b enable once every clks d z - q reset z -3 d z - q valid latency for this module = 4 Figure 40: System Generator Diagram of Step Terminal Count Block (x5 MHz Configuration) XAPP3 (v.0) October 9,

41 Transmit Downlink Design & Implementation ate and Data Format Conversion For rate and data format conversion: Ports of the DUC module operate on the MHz system clock rate domain. Ports of the CF module (except for ce_3_out) operate on the.88 sample rate. The DUC output data format is Fix 6.5 (or Fix 6.4) which is different from the Fix 6.0 the CF module required. Figure 4 shows how a rate and data format conversion block is used to integrate these two modules. a rate and data format conversion block is used as shown in Figure 4: X-ef Target - Figure 4 _i reinterpret d z - q egister 3 z - dout _i _q reinterpret d z - q egister 3 z - dout _q 3 vin d z - q en egister 3 z - 3 vout 4 _ eset Generator Figure 4: System Generator Block Diagram of ate and Data Format Conversion Block 3 rdy 4 _3 CF Implementation The PC-CF module used in this reference design is a slightly modified version of what is described in [ef 4]. In [ef 4], the system clock rate must be set to four times the sample rate. For example, a sample rate of 76.8, the clock rate is equal to 307. MHz. In this reference design, the system clock rate is MHz, three times the sample rate of.88. Some modification is required to generate the three clocks per sample PC-CF module. Because much of the original design operates at the sample rate, the modifications are needed for only a few sections of the design. There is a GUI to select the PC-CF from one of two settings: The single-carrier setting which uses three CPGs for both iterations. The multi-carrier setting which uses six CPGs for the fi iteration and three CPGs for the second iteration. The carrier and bandwidth selection on the top-level (Figure 9) dictates the architecture used in the PC-CF. Figure 4 shows the CF module. XAPP3 (v.0) October 9,

42 Transmit Downlink Design & Implementation X-ef Target - Figure 4 Figure 4: System Generator GUI of PC-CF Module Figure 43 shows System Generator block diagram of the PC-CF design. For further implementation details, refer to [ef 4]. A link to the document is available in eferences, page 87. It contains two iterations of the PC-CF algorithm. For single carrier configurations (x5, x0, x5 and x0), each of the iterations is identical. The input and output data streams are quantized to 6 bits and are represented in two s complement number format. All interface signals operate at the sample rate (.88 ) with the exception of the ce_3_out signal which operates at the system clock rate. For multi-carrier configurations (x5, x0, and 4x5), as described in Crest Factor eduction Architecture, six CPGs are required in the st iteration. The major difference compared to the single carrier case is in the cancellation pulses (c_pulses) module, that extra logic is required to process the pulse cancellation in parallel. Table 0 lists the resource utilization for the 3 CPG and 6 CPG versions of the PC-CF design. Table 0: esource Utilization Summary for PC-CF Design Configuration DSP48s AMB36k AMB8k FFs LUTs Slices Single carrier setting (3 CPGs for each iteration) Multi-carrier setting (6 CPGs for st iteration; 3 CPGs for nd iteration) Figure 44 and Figure 45 show the 3 CPG and 6 CPG versions of System Generator diagram of c_pulses module and the System Generator Diagram of Cancellation Pulses (c_pulses) Module, 6 CPGs version, respectively. XAPP3 (v.0) October 9,

43 Transmit Downlink Design & Implementation For further implementation details, refer to [ef 4]. A link to the document is available in eferences, page 87. X-ef Target - Figure 43 data _i_in data_i_in data _q_in data_q_in data_i_out CEProbe 4 ce_3_out 3 data _sync data_sync 4 threshold threshold 5 alloc _spacing alloc_spacing data_q_out 7 filter _numtaps filter _numtaps 8 filter _ram_addr filter _ram_addr 9 filter _ram_data filter _ram_data data_i_in 0 filter _ram_we reset filter _ram_we reset PC_CF Iteration pc_cfr _6CPGs data_valid data_q_in data_sync data_i_out data _i_out threshold 6 alloc _spacing alloc_spacing filter _numtaps data_q_out data _q_out filter _ram_addr filter _ram_data filter _ram_we data_valid 3 data _valid reset PC_CF Iteration pc_cfr _3CPGs Figure 43: System Generator Block Diagram of PC-CF Design X-ef Target - Figure 44 6 filter _ram _addr 7 filter _ram _data wr_addr wr_data coef_re 8 wr_en filter _ram _we coef_im peak _scale_i peak_scale_i cpg_0_addr cpg addr cpg_0_addr cpg addr cpg_addr rd_addr filter _ram peak _scale_q peak_scale_q cpg addr cpg_0_peak_i cpg addr cpg_0_peak_i cpg_peak_i ar ai sum_re pulse _sum_i 3 peak _indicator peak_indicator cpg peak_i cpg peak_i cpg peak_i cpg peak_i cpg_peak_q z -3 z -3 br bi sync sum_im pulse _sum_q 5 filter _numtaps numtaps cpg_0_peak_q cpg_0_peak_q cmplx _mac cpg peak_q cpg peak_q 4 alloc_spacing cpg_sync z -3 alloc _spacing cpg peak_q cpg peak_q cpg_allocator cpg _multiplexing Figure 44: System Generator Diagram of Cancellation Pulses (c_pulses) Module, 3 CPGs version XAPP3 (v.0) October 9,

44 eceive Uplink Design & Implementation X-ef Target - Figure 45 6 filter _ram_addr 7 filter _ram_data wr_addr wr_data coef_re0 coef _im0 8 wr_en filter _ram_we rd_addr0 coef_re cpg_0_addr cpg_0_addr cpg_addr_0 peak_scale_i cpg addr cpg addr rd_addr coef _im peak _scale_i cpg addr cpg addr filter _ram cpg_3_addr cpg_3_addr cpg_addr_345 cpg_4_addr cpg_4_addr ar0 peak _scale_q peak_scale_q cpg_5_addr cpg_0_peak_i cpg peak_i cpg_5_addr cpg_0_peak_i cpg peak_i cpg_peak_i0 z -3 ai0 br0 bi0 sum_re pulse _sum _i 3 peak _indicator peak_indicator cpg peak_i cpg_3_peak_i cpg_4_peak_i cpg peak_i cpg_3_peak_i cpg_4_peak_i cpg_peak_i345 z -3 ar ai br sum_im 5 filter _numtaps numtaps cpg_5_peak_i cpg_0_peak_q cpg peak_q cpg_5_peak_i cpg_0_peak_q cpg peak_q cpg_peak_q0 z -3 bi sync cmplx _mac pulse _sum_q cpg peak_q cpg peak_q cpg_peak_q345 z -3 cpg_3_peak_q cpg_3_peak_q 4 alloc_spacing cpg_4_peak_q cpg_4_peak_q alloc _spacing cpg_5_peak_q cpg_5_peak_q cpg_sync z -3 cpg_allocator cpg _multiplexing Figure 45: System Generator Diagram of Cancellation Pulses (c_pulses) Module, 6 CPGs version eceive Uplink Design & Implementation Performance equirements The following subsections describe the performance requirements for the eceive Uplink design and implementation. eference Sensitivity Level Section 7. of the 3GPP T (and TS 36.04) [ef ] describe the reference sensitivity level requirements for the E-UTA BS. The reference sensitivity level specifies the minimum mean power received at the antenna connector to meet some performance criteria. For the LTE uplink, the reference sensitivity level is defined over a bandwidth correspong to 5 resource blocks, where each resource block occupies subcarriers that are spaced 5 khz apart. Therefore, the measurement bandwidth for the reference sensitivity level is 5 5 khz = 4.5 MHz. Table, lists the reference sensitivity level for the E-UTA BS. The numbers in the table are based on a receiver noise figure of 5 db, signal-to-noise ratio (SN) operating point equal to 95% relative of nominal throughput with db implementation margin and 90% bandwidth efficiency from [ef ]. The FC A-3 reference channel is based on 5 resource blocks of QPSK, ate-/3 turbo coded data with DFT-OFDM symbols per subframe. For bandwidths greater than 5 MHz, multiple chunks of the 5 resource block FC A-3 are applied [ef ]. Table : E-UTA BS eference Sensitivity Level (From 3GPP T 36.04, Table 7.-) Channel Bandwidth (MHz) eference Measurement Channel eference Sensitivity Level (dbm) 5 FC A-3 in Annex A FC A-3 in Annex A FC A-3 in Annex A FC A-3 in Annex A XAPP3 (v.0) October 9,

45 eceive Uplink Design & Implementation Adjacent Channel Selectivity The following information is taken from section 7.4. of [ef ] (see also section 7.5 of [ef ]): Adjacent channel selectivity (ACS) is a measure of the receiver ability to receive a wanted signal at its assigned channel frequency in the presence of an adjacent channel signal at a given frequency offset. For UTA, the ACS is defined by stating a required BE performance of 0.00 at a specified data rate, wanted signal mean power and interfering signal mean power. From 3GPP TS 5.04 [ef 7], an ACS value of 46 db is used for the UTA FDD BS, assuming a noise figure of 5 db for the BS receiver. For E-UTA, two different types of interference signals are used to specify ACS: A wideband interferer consisting of a 5-MHz E-UTA signal A narrowband interferer consisting of a single resource block from a 5 MHz E-UTA signal. Table (from Table of 3GPP T [ef ]) lists the ACS requirements for the wideband interferer. Table 3 lists the requirements for the narrowband interferer. Note: The wanted signal power is set to a level that is 6 db higher than the reference sensitivity level. As pointed out in T , this does not mean that 6 db degradation is allowed. It is simply a selected test parameter to make the interference impact measurable. As with the reference sensitivity level, the wanted signal mean power levels are normalized to a bandwidth of 5 resource blocks (4.5 MHz). Table : ACS equirement with Wideband Interferer (from Table of [ef ]) Channel Bandwidth (MHz) Wanted Signal Mean Power (dbm) Interfering Signal Mean Power (dbm) Frequency Offset from Band Edge (MHz) 5 EFSENS EFSENS EFSENS EFSENS Table 3: ACS equirement with Narrowband Interferer (from Tables 7.5-, of [ef ]) Channel Bandwidth (MHz) Wanted Signal Mean Power (dbm) Interfering Signal Mean Power (dbm) Frequency Offset from Band Edge (MHz) 5 EFSENS m*80 m = 0,,, 3, 4, 9, 4, 9, 4 0 EFSENS m*80 m = 0,,, 3, 4, 9, 4, 9, 4 5 EFSENS m*80 m = 0,,, 3, 4, 9, 4, 9, 4 0 EFSENS m*80 m = 0,,, 3, 4, 9, 4, 9, 4 For all BW = 5, 0, 5, or 0 MHz, the wideband interference signal is a 5-MHz E-UTA signal that is centered.5 MHz from the victim carriers band edge. For example, if BW = 0 MHz, then the center frequency of the interfering signal would be at.5 MHz. From Table, EFSENS = -0.6 dbm measured in a 4.5-MHz bandwidth. Therefore, the wanted signal power is equal to -95.6, -9.6, -90.8, or dbm for channel bandwidths of 5, 0, 5, and 0 MHz, respectively. XAPP3 (v.0) October 9,

46 eceive Uplink Design & Implementation At the stated signal powers, the interfering signal mean power is -5 dbm for all cases. Using BW = 5 MHz, the interferer is -5 (-95.6) = 43.6 db higher than the wanted signal. Because the reference bandwidth is 4.5 MHz, the ACS for all channel bandwidths (5, 0, 5, 0 MHz) is the same (~44 db). For the narrowband interferer, the wanted signal mean power of dbm per 5 resource blocks translates into dbm per resource block. The mean power of the narrowband interfering signal is -49 dbm and occupies a single resource block. This implies that the spectral level of the narrowband interferer is ~6 db higher than the spectral level of the wanted signal. However, the total mean power of the narrowband interferer is only -49 (-95.6) = 46.6 db higher than the wanted signal. With the narrowband interference it is sufficient to base the filter requirements on the total power levels rather than the relative spectral levels. Blocking Characteristics The blocking performance is specified as a measure of the receiver ability to receive a wanted signal in the presence of an unwanted interferer. The interference signal is a 5-MHz E-UTA signal for in-band blocking and a continuous wave (CW) signal for out-of-band blocking. Table 4 lists the in-band blocking requirements for all operating bands. Table 4: In-Band Blocking equirements (from Tables 7.6-, of 3GPP T 36.04) Channel Bandwidth (MHz) Wanted Signal Mean Power (dbm) For in-band blocking, the center frequency of the interfering signal is specified as being between (F UL_low -0) MHz and (F UL_high +0) MHz. For example, the E-UTA operating band has F UL_low = 90 MHz and F UL_high = 980 MHz. Therefore, the in-band interferer lies between 900 MHz and 000 MHz. Out-of-band interferers lie outside of the range defined for the in-band interferers. The mean power of the CW interferer for the out-of-band blocking is -5 dbm. There is a blocking requirement for co-location with GSM, UTA, and E-UTA operating in different frequency bands. The CW interference in this case is +6 dbm. In both cases, it is assumed that the out-of-band interference is sufficiently attenuated by analog filters in the receiver front-end to mitigate the impact on the digital filter requirements. The in-band blocking requirements are similar to the wideband ACS requirements, except the interfering signal is in the second adjacent channel (relative to 5 MHz bandwidth) and its power is -43 dbm compared to only -5 dbm (9 db higher). Therefore, the spectral level of the 5-MHz E-UTA interferer is ~53 db higher than the spectral level of the wanted signal. Intermodulation Characteristics Interfering Signal Mean Power (dbm) Frequency Offset from Band Edge (MHz) 5 EFSENS EFSENS EFSENS EFSENS The following description of intermodulation characteristics is from section 7.6 of the 3GPP T [ef ] (see also section 7.8 of 3GPP TS [ef ]): The intermodulation performance requirement of the E-UTA system is specified as a measure of the capability of the receiver to receive a wanted signal on its assigned channel frequency in the presence of two interfering signals which have a specific frequency XAPP3 (v.0) October 9,

47 eceive Uplink Design & Implementation relationship to the wanted signal. There are two types of intermodulation requirements: wideband and narrowband: The wideband intermodulation pairs a 5-MHz E-UTA interferer at some offset frequency with a CW interferer at a different offset frequency. Table 5 lists the wideband intermodulation requirements. The narrowband intermodulation pairs resource block of a 5-MHz E-UTA signal at some offset frequency with a CW interferer at a different offset frequency. Table 6 lists the narrowband intermodulation requirements. Table 5: Wideband Intermodulation equirements (from Tables 7.8-, of [ef ] Channel Bandwidth (MHz) Wanted Signal Mean Power (dbm) Interfering Signal Mean Power (dbm) 5 EFSENS EFSENS EFSENS EFSENS Frequency Offset from Band Edge (MHz) Type of Interfering Signal CW 5 MHz E-UTA CW 5 MHz E-UTA CW 5 MHz E-UTA CW 5 MHz E-UTA Table 6: Narrowband Intermodulation equirements (from Table of [ef ]) Channel Bandwidth (MHz) Wanted Signal Mean Power (dbm) Interfering Signal Mean Power (dbm) 5 EFSENS EFSENS EFSENS EFSENS Frequency Offset from Band Edge (khz) Type of Interfering Signal CW B, E-UTA CW B, E-UTA CW B, E-UTA CW B, E-UTA Summary of equirements for ACS, Blocking, and Intermodulation Table 7 summarizes the ACS, blocking and intermodulation requirements based on information presented in the previous subsections. The interference relative mean power is the ratio of the interference mean power to that of the wanted signal in db. Table 7: Summary of ACS, Blocking, and Intermodulation equirements Interference equirement Interfering Signal Interference elative Mean Power Minimum Frequency Offset from Band Edge Wideband ACS 5-MHz E-UTA 44.5 MHz Narrowband ACS B, E-UTA khz In-Band Blocking 5-MHz E-UTA MHz XAPP3 (v.0) October 9,

48 eceive Uplink Design & Implementation Table 7: Summary of ACS, Blocking, and Intermodulation equirements (Cont d) Interference equirement Interfering Signal Interference elative Mean Power Minimum Frequency Offset from Band Edge Wideband Intermodulation CW 5-MHz E-UTA MHz 7.5 MHz Narrowband Intermodulation CW B, E-UTA [345, 360] khz [780, 060] khz Filter equirements This section derives the receiver digital filter requirements from the ACS, blocking, and intermodulation requirements. From the reference sensitivity level section, the minimum mean power received at the antenna connector is -0.6 dbm per 4.5 MHz of bandwidth. Assuming a standard noise temperature of T 0 = 90 K, the noise power at the receiver front end is given by N = κt 0 W watts, where κ = Boltzmann s constant = W/K-Hz. The total noise power in a bandwidth of 4.5 MHz is dbm. Therefore, the signal-to-noise ratio (SN) within the 4.5 MHz bandwidth is equal to 5.9 db. The ACS, blocking, and intermodulation measurements are defined at a level of EFSENS + 6 db. Therefore, the inchannel SN is equal to.9 db. At a minimum, it would be desirable to attenuate the interference signals to be below the thermal noise level. If the attenuated interference is at the same level as the thermal noise, it is expected that the SN will be degraded by 3 db. For comparison, a 3 db degradation is allowed when testing adjacent channel rejection for WiMAX [ef 8] [ef 9]. This level of performance would require a stopband attenuation of = ~65 db. Adg 5 db of margin to this number gives the required 80 db of stopband attenuation that is listed in Table, page 8. Digital Down-Converter Architecture This section describes each of the modules shown in Figure, page 7. Fs/4 Mixer + Halfband Decimator The Fs/4 mixer is used to frequency translate the spectrum of the real input signal centered at one fourth the sample rate to 0 Hz. The input signal is assumed to occupy a bandwidth of 5-MHz, 0-MHz, 5-MHz, or 0 MHz. If the input signal bandwidth contains multiple carriers, the Fs/4 mixer centers the entire bandwidth at 0 Hz regardless of the carrier configuration. For example, if there are four 5-MHz carriers within a 0-MHz bandwidth, the output of the Fs/4 mixer will have a spectrum with two carriers to the left of 0 Hz and two carriers to the right of 0 Hz. The Fs/4 mixer output signal is complex. An Fs/4 mixer has the property that the exp(-jωt) term used to multiply the input signal reduces to exp(-jnπ/) = (, -j, -, j,, -j, -, j, ). Therefore, the frequency translation can be accomplished with some simple two s complement and MUX circuitry. If the input signal is represented by x(n): the I channel output takes the form x(n) [, 0, -, 0,, 0, -, 0, ] the Q channel output takes the form x(n) [0, -, 0,, 0, -, 0,, ]. The fact that every other sample is zero on each channel can be exploited to reduce filtering complexity. In particular, for a decimate-by- filter, one polyphase arm can be eliminated from XAPP3 (v.0) October 9,

49 eceive Uplink Design & Implementation each channel. If a halfband decimator is used, only one non-trivial filter arm is needed to filter the entire complex input signal. The output of a polyphase decimate-by- filter can be written as where: y n) = y ( n) + y ( ( 0 n ) X-ef Target - Figure 46 y L / 0 ( n) = h0 ( k) x0( n k) k = 0 Equation 4 y L / ( n) = h ( k) x ( n k) k = 0 h 0 (k) = h(k) are the even filter coefficients h (k) = h(k+) are the odd coefficients x 0 (n) = x(n) are the even data samples x (n) = x(n-) are the odd data samples L is the filter length Equation 5 For the Fs/4 mixer I channel output, the odd samples are zero and the even samples are the even samples of the Fs/4 mixer input modulated by a ± sequence. The Q channel output has even samples that are zero and odd samples that are equal to the odd samples of the Fs/4 mixer input modulated by a (±) sequence. Therefore, The I channel filter output is equal to ±x 0 (n) filtered with h 0 (k) The Q channel filter output is equal to (±x(n)) delayed by (floor(l/)-)/ samples. Table 8 lists the filter parameters for the halfband filter that follows the Fs/4 mixer. The filter is designed to accommodate the widest bandwidth of 0 MHz and is used for all configurations. Table 8: Filter Parameters for Halfband Decimator that Follows Fs/4 Mixer Filter Fs () Decimation Filtering Fpass (MHz) Fstop (MHz) Apass Astop # Taps HB # The general structure of the decimation filtering mirrors the interpolation filtering used in the transmit downlink. The input sample rate to the decimation filtering module is 6.44 (see Figure, page 7). The decimation filtering for the 5-MHz, 0-MHz, and 0-MHz bandwidth configurations is implemented using a cascade of halfband filters. For the 5-MHz configuration, a rate 3/4 fractional resampler is also needed. The multi-carrier configurations are handled in a similar manner, except a second stage of mixing is needed to frequency translate each carrier down to 0 Hz. Filters were designed using the Filter Design and Analysis Tool (FDATool) in MATLAB. XAPP3 (v.0) October 9,

50 eceive Uplink Design & Implementation x5 MHz Configuration Figure 46 shows the decimation filtering chain for the x5 MHz configuration. Each filter is a halfband decimation filter with parameters as listed in Table 9, page 50. The equiripple halfband lowpass input parameters (in FDATool) are Fs, Fpass, and Apass. The parameter Fstop is implied by the parameters Fs and Fpass. Astop is measured from the filter magnitude response. The number of taps is the length of the smallest filter that satisfies the requirements specified by the input parameters. Although the occupied bandwidth of the channel is only 90% of the total channel bandwidth, the passband cutoff frequency was set to protect the entire 5-MHz band. This was done to improve the system-level performance of the receive uplink in the presence of interferers. If the passband cutoff frequency is set to.5 MHz instead of.50 MHz, it is possible for a potentially strong interferer to alias down into the transition band of the channel filter (the stopband of the channel filter is set to.50 MHz for the x5 MHz configuration). X-ef Target - Figure HB # HB # 5.36 HB # 7.68 ( taps) (5 taps) (7 taps) Figure 46: Decimation Filter Structure for x5 MHz Configuration X Table 9: Filter Parameters for x5 MHz Configuration Filter Fs () Fpass (MHz) Fstop (MHz) Apass Astop # Taps HB # HB # HB # x0 MHz Configuration Figure 47 shows the decimation filtering chain for the x0 MHz configuration. Table 30 lists the filter parameters. After normalizing to the filter sample rates, the passband cutoff frequencies are identical to the frequencies listed in Table 9. Given this and the fact that the same passband ripple was specified, the filter coefficients are identical to the ones used in the correspong filters for the x5 MHz configuration. The throughput requirement for each filter is doubled because the sample rates at each stage are doubled. X-ef Target - Figure HB # 30.7 HB # 5.36 (5 taps) (7 taps) X3_47_0008 Figure 47: Decimation Filter Structure for x0 MHz Configuration XAPP3 (v.0) October 9,

51 eceive Uplink Design & Implementation Table 30: Filter Parameters for x0 MHz Configuration Filter Fs () x5 MHz Configuration Fpass (MHz) Fstop (MHz) Apass Astop Figure 48 shows the decimation filtering chain for the x5 MHz configuration. The filter parameters are listed in Table 3. # Taps HB # HB # A fractional resampler is required to convert from the 30.7 rate to the 3.04 rate. The filter was designed using the lowpass equiripple design methodology in FDATool. The filter sample rate is based on the interpolated rate of = 9.6. Unlike the halfband filters, the resampler stopband cutoff frequency is explicitly specified. The value of 5.54 MHz was chosen to protect the entire 5-MHz band from aliasing after the implicit decimation by 4. X-ef Target - Figure HB # (x5) 30.7 Fractional esampler P/Q = 3/ (9 taps) (45 taps) Figure 48: Decimation Filter Structure for x5 MHz Configuration Table 3: Filter Parameters for x5 MHz Configuration Filter Fs () x0 MHz Configuration Fpass (MHz) Fstop (MHz) Apass Astop X3_48_0008 Figure 49 shows the decimation filtering for the x0 MHz configuration. Table 3 lists the filter parameters. After normalizing to the sample rate, the filter coefficients are identical to those in the correspong filter for the x0 MHz and x5 MHz configurations. # Taps HB # (x5) esampler X-ef Target - Figure HB # 30.7 (7 taps) Figure 49: Decimation Filter Structure for x0 MHz Configuration Table 3: Filter Parameters for x0 MHz Configuration Filter Fs () Fpass (MHz) Fstop (MHz) X Apass Astop # Taps HB # XAPP3 (v.0) October 9,

52 eceive Uplink Design & Implementation x5 MHz Configuration Figure 50 shows the decimation filtering chain for the x5 MHz configuration. Table 33 lists the filter parameters. The multi-carrier input signal has a total allocated bandwidth of 0 MHz and the initial filtering is based on this total bandwidth. The fi two halfband filters are the same as those used in the x0 MHz case. The coefficients for the final halfband filter are the same as those used in the second halfband filter (both are labeled HB#). The difference is that they operate at different sample rates and accommodate a different number of channels. At some point in the digital down conversion chain, it becomes necessary to further split the two carriers by frequency translating each one to 0 Hz before applying further decimation filtering and eventually channel filtering. A tradeoff exists in determining the best placement of the second stage (multi-carrier) mixer: Placing the mixer close to the IF results in each subsequent halfband filter has lower complexity because the ratio of sample rate to passband frequency is high. However, each filter that follows the multi-carrier mixer must now handle multiple complex channels. Placing the multi-carrier mixer at the lowest possible sample rate has the advantage that fewer filters in the chain need to handle multiple complex channels. In this case, most of the filters operate on the composite multi-carrier signal (one complex channel). However, because the multi-carrier signal occupies a greater bandwidth than a single carrier, at some point the normalized transition band of the filter becomes so small that the filter complexity can increase dramatically. Taking these factors into account results in a placement of the multi-carrier mixer as shown in Figure 50. X-ef Target - Figure 50 Complex Channels 6.44 HB # 30.7 HB # 5.36 Carrier Mixer 5.36 HB # 7.68 (5 taps) (7 taps) (7 taps) X3_50_0008 Figure 50: Decimation Filter Structure for x5 MHz Configuration Table 33: Filter Parameters for x5 MHz Configuration Filter Fs () x0 MHz Configuration Fpass (MHz) Fstop (MHz) Apass Astop # Taps HB # HB # HB # Figure 5 shows the decimation filtering chain for the x0 MHz configuration. Table 34 lists the filter parameters. XAPP3 (v.0) October 9,

53 eceive Uplink Design & Implementation The multi-carrier input signal has a total allocated bandwidth of 0 MHz. The fi halfband filter is the same as those used in the x0 MHz case. The coefficients for the final halfband filter are the same as the ones used in the fi halfband filter (both are labeled HB#). X-ef Target - Figure 5 Complex Channels 6.44 HB # 30.7 Carrier Mixer 30.7 HB # 5.36 (7 taps) (7 taps) Figure 5: Decimation Filter Structure for x0 MHz Configuration X Table 34: Filter Parameters for x0 MHz Configuration Filter Fs () 4x5 MHz Configuration Fpass (MHz) Fstop (MHz) Apass Astop # Taps HB # HB # Figure 5 shows the decimation filtering chain for the 4x5 MHz configuration. Table 35 lists the filter parameters. The multi-carrier input signal has a total allocated bandwidth of 0 MHz. The fi halfband filter is the same as the one used in the x0 MHz case. The coefficients for the final halfband filter are the same as the ones used in the fi halfband filter (both are labeled HB#) because the normalized parameters are equivalent. X-ef Target - Figure 5 4 Complex Channels 4 Complex Channels 6.44 HB # Carrier Mixer 30.7 HB # 5.36 HB # 7.68 (7 taps) (5 taps) (7 taps) Figure 5: Decimation Filter Structure for 4x5 MHz Configuration X3_5_0008 Table 35: Filter Parameters for 4x5 MHz Configuration Filter Channel Filter Fs () Fpass (MHz) Fstop (MHz) Apass Astop # Taps HB # HB # HB # After decimation filtering, a single-rate channel filter is applied to remove any interference that might exist in the region between the allocated channel bandwidth and the Nyquist frequency. For the case of 3GPP LTE, the occupied channel bandwidth is 90% of the total channel bandwidth. This determines the passband cutoff frequency. XAPP3 (v.0) October 9,

54 eceive Uplink Design & Implementation The stopband frequency is set to match the channel bandwidth (Fstop = BW/). The peak-to-peak passband ripple (Apass) and stopband attenuation (Astop) were set to meet the performance requirements summarized in Table, page 8. Table 36 lists the filter parameters for the channel filter. Table 36: Filter Parameters for the Channel Filter BW (MHz) Fs () Fpass (MHz) Fstop (MHz) Apass Astop # Taps The filter coefficients are the same for each configuration because the normalized parameters are identical. Figure 53 shows the magnitude response of the channel filter. After 8-bit quantization of the coefficients, the stopband rejection is 80 db and the peak-to-peak passband ripple is 0.05 db. Obtaining the stopband rejection of 80 db requires that the coefficients be scaled such that the peak of the impulse response is equal to the maximum positive 8-bit signed number (307/307). This results in a filter passband gain of.637. If unity passband gain is maintained, the impulse response peak is 0.68 and the stopband rejection degrades to ~77 db. X-ef Target - Figure Magnitude esponse of Channel Filter Double Precision Quantized (8 bits) db Filter Quantization Frequency (MHz) Figure 53: Magnitude esponse of Channel Filter This section summarizes the characteristics of the filters after quantizing the coefficients to 8 bits. Table 37 lists the decimation filter characteristics after 8-bit quantization. In the Virtex-5 FPGA family, each dedicated hardware multiplier (DSP48E) can perform a signed 8-bit by 5-bit multiply. For the DDC reference design, the quantization was limited to 8 bits by 8 bits to XAPP3 (v.0) October 9,

55 eceive Uplink Design & Implementation remain consistent with previous architectures. This allows the user the flexibility of increasing either the data path quantization or the coefficient quantization. The System Performance section demonstrates that this level of quantization is sufficient to meet the adjacent channel, blocking, and intermodulation performance requirements. Table 37: Decimation Filter Characteristics after 8-Bit Quantization Filter Multi-Carrier Mixing This section describes the architecture of the multi-carrier mixing that is embedded in the decimation filter chains for the x5, x0, and 4x5 MHz configurations. The multi-carrier mixing is needed to frequency translate each carrier of interest down to 0 Hz before further decimation and channel filtering. The mixer used in the 4x5 MHz configuration is described followed by a description of the mixer architectures for the x5 and x0 MHz configurations. Hardware implementation details are covered in Hardware Verification, page 86. 4x5 Multi-Carrier Mixing Fs () Fpass (MHz) Fstop (MHz) Apass Astop # Taps HB # < HB # < HB # < HB # < HB # (x5) < esampler (x5) Channel In the 4x5 MHz case, the input to the mixer is a single complex signal sampled at The mixer multiplies the input signal by exp(-jω 0 t), exp(-jω t), exp(-jω t), and exp(-jω 3 t) to produce four complex output signals, where the ω k represent the carrier center frequencies. Letting x(n) represent the input signal, the real (I channel) and imaginary (Q channel) components of the output signals are given by Equation 6 and Equation 7: X-ef Target - Figure 54 y y Ik Qk ( n) = x ( n)cos( ω n) + x ( n)sin( ω n) I k ( n) = x ( n)cos( ω n) x ( n)sin( ω n) Q k Q I k k Equation 6 A Direct Digital Synthesizer (DDS) is used to generate the sine and cosine waveforms. Equation 7 For 3GPP LTE, the carrier center frequencies are located on a 00 KHz raster. This feature can be exploited to reduce computational complexity while simultaneously provig better system level performance. In particular, the rasterized DDS is shown to have ideal SFD and requires no further noise shaping methods such as dithering. In a rasterized DDS, a finite set of discrete frequencies can be generated, where each frequency is a multiple of the raster size. For example, at a sample rate of 30.7, a 0 khz raster can be supported by storing one full cycle of cosine wave that is discretized to 307 samples. If only 536 samples is stored to cover one full cycle, then the raster size is 0 khz. XAPP3 (v.0) October 9,

56 eceive Uplink Design & Implementation The number of samples stored to cover a full cycle must be an integer. Given this constraint, and to minimize hardware, a 0 khz raster is used to cover the 00 khz raster requirement. In particular, addressing the cosine OM to access every fifth location will give a 00 khz cosine wave. The output of the rasterized DDS has a noise floor that is governed by the quantization of the sine and cosine waves, but as previously mentioned, the SFD is ideal. This is because the cosine samples that are stored and accessed line up exactly with the ideal sampling times for the rasterized frequencies. Figure 55 gives an example plot of the DDS output spectrum. The cosine wave is quantized to 8 bits, but the effective number of bits is only 7, because the cosine wave is scaled to give a maximum output of 0.5. The measured output signal-to-noise ratio is approximately 04 db which is consistent with the predicted value of 7 bits 6 db/bit = 0 db. X-ef Target - Figure 55 0 PSD of DDS Output Signal db Frequency (MHz) x5 Multi-Carrier Configuration Figure 55: Example DDS Output Spectrum In the x5 MHz configuration, a similar multi-carrier mixer is used. In this case, the mixer input is a complex signal sampled at Only 768 samples of one full cosine wave are needed to support a 0 KHz raster. The mixer sample rate is The mixer from the x5 MHz configuration was reused to implement the mixer for the x0 MHz configuration. The main difference is that now the 768 samples of one full cosine wave provide a 40 khz raster. While this is not a factor of 00 khz, the default carrier center frequencies for this case are ±5.0 MHz which is a multiple of 40 khz. Therefore, the same mixer is used but operates at a different sample frequency. XAPP3 (v.0) October 9,

57 eceive Uplink Design & Implementation System Performance This section describes the methodology used to test the receive uplink portion of the digital front end and provides some simulation results. Methodology and Assumptions The performance of the receive uplink is based on simulation results that were obtained from internally developed MATLAB code. All results are based on processing one 0 ms frame worth of Physical Uplink Shared Channel (PUSCH) data. In this reference design, frame structure type is used. See section 4. of GPP TS 36. V8.0.0 (007-09)[ef 0], for further description of the frame structure. Figure 56 shows a block diagram of the uplink simulation software. The code contains a simplified baseband signal generator that creates random modulation symbols from a QAM alphabet (4-QAM, 6-QAM, or 64-QAM). The random modulation symbols are then transform precoded using the equation listed in section of 3GPP TS 36. V8.0.0 (007-09) [ef 0]. X-ef Target - Figure 56 andom Symbol Generator Transform Precoder SF-FDMA Signal Generator DUC Model + Noise + Interference Performance Analysis Inverse Transform Precoder SC-FDMA Signal eceiver DDC Model Figure 56: Block Diagram of eceive Uplink Simulation Software X3_55_0008 The transform precog process performs an Msc-point DFT on contiguous blocks of modulation symbols, where Msc is the number of subcarriers per SC-FDMA symbol. The transform precoder is followed by the SC-FDMA signal generator. The SC-FDMA signal generator produces OFDM symbols based on the equation from section 5.6 of 3GPP TS 36.[ef 0]. In particular, it performs the IFFT? and generates the cyclic extension. Table 38 lists the parameters used for the baseband signal generation. Table 38: SC-FDMA Parameters for Uplink Bandwidth (MHz) Sample ate () FFT Size Number of Subcarriers After baseband signal generation, the data passes through a DUC model. The DUC model contains a channel filter followed by a cascade of interpolation filters to get to a sample rate of.88. For multi-carrier cases, the DUC model also performs frequency translation before combining the different carriers. After digital up-conversion, noise and interference is added to the signal to model the channel. The type of interference added is specified through a top-level parameter. The code supports XAPP3 (v.0) October 9,

58 eceive Uplink Design & Implementation five types of interference: wideband adjacent channel, narrowband adjacent channel, in-band blocker, wideband intermodulation and narrowband intermodulation. When noise is turned on, the noise level is set to achieve an in-channel SN of.9 db as explained in the Filter equirements, page 48. After adg interference and noise, the real part of the signal is taken and quantized to 4 bits to drive a bit-true model of the DDC. The DDC output signal drives an SC-FDMA signal receive module that performs the inverse operation of the SC-FDMA signal generator block. In particular, it removes the cyclic extension from the signal and then performs an FFT on each OFDM symbol. After the FFT, the SC-FDMA symbols are processed by the inverse transform precoder (inverse DFT) to recover the received data modulation symbols. The recovered data symbols are compared to the known data symbols at the transform precoder input to generate an error vector magnitude (EVM) or relative constellation error (CE) metric. For the DDC performance results, EVM and CE are calculated the same, except one is presented as a percentage and the other is presented in db. Two methods of EVM calculation were considered for the receive uplink. The simpler method is based on comparing the received modulation symbols to the transmitted modulation symbols over the entire frame. The second method is based on calculating EVM over each - subcarrier by -subframe block and then averaging. For the data presented here, the results between the two methods are nearly identical (around 0.0% difference). One method of measuring system-level performance is carried out by adg interference in the presence of AWGN at some SN. The degradation in EVM that occurs after adg the interference indicates the degradation in the in-channel SN. If the degradation is small, the interference level can be increased until the in-channel SN degrades by 3 db. This gives an indication of how much margin is provided over the requirements for a given level of degradation. Simulation esults The simulation results presented focus on the 4x5 MHz configuration because it represents the wo case scenario. In particular, the multiple 5-MHz carriers act as additional interference sources relative to each carrier of interest. Five performance tests are performed: Wideband ACS, Narrowband ACS, In-Band Blocking, Wideband Intermod, and Narrowband Intermod. In addition, the case of no interference with and without AWGN are examined to establish the baseline performance. No Noise and No Interference This section examines the performance of the receive uplink in the absence of both interference and noise. Figure 57 shows a plot of the power spectral density at the DDC input. The noise floor level of -80 db is consistent with the input quantization of 4 bits. The one-sided spectrum is shown to highlight that the input signal is real. The plot on the negative side of the frequency domain is XAPP3 (v.0) October 9,

59 eceive Uplink Design & Implementation the reflection of the image on the positive side. The multi-carrier waveform is centered at 30.7 which is one fourth the sample rate of.88. X-ef Target - Figure 57 0 PSD of DDC Input Signal db -50 Figure 57: PSD of DDC Input with No Noise and No Interference Figure 58 shows a plot of the signal constellation at the transmit precoder input overlayed with the constellation at the inverse transform precoder output. In all cases, the test signal is QPSK as specified in [ef ] and [ef ]. Table 39 lists the EVM and CE for each carrier. The EVM values are within the % requirement that specified in Table, page 8. Table 39: SC-FDMA Parameters for Uplink Bandwidth (MHz) Frequency (MHz) Sample ate () FFT Size Number of Subcarriers XAPP3 (v.0) October 9,

60 eceive Uplink Design & Implementation X-ef Target - Figure 58 Figure 58: Transmitted and eceived Constellation with No Noise and No Interference Noise Only In this section, the performance of the receive uplink is examined in the presence of AWGN but in the absence of other interference. Figure 59 shows a plot of the power spectral density at the DDC input. The noise level is set to achieve an in-channel SN of.9 db. XAPP3 (v.0) October 9,

61 eceive Uplink Design & Implementation X-ef Target - Figure 59 0 PSD of DDC Input Signal db Frequency (MHz) Figure 59: PSD of DDC Input for Noise Only Case Figure 60 shows a plot of the signal constellation at the transmit precoder input overlaid with the constellation at the inverse transform precoder output. X-ef Target - Figure 60 Figure 60: Transmitted and eceived Constellation for Noise Only Case XAPP3 (v.0) October 9,

62 eceive Uplink Design & Implementation Table 40 lists the EVM and CE for each carrier. The EVM values are consistent with the inchannel SN setting of.9 db. Table 40: Performance Data for Noise Only Case In-Channel SN Wideband ACS Interference elative Power EVM (%) CE.9 -Inf 5.4, 5.3, 5.3, , -.9, -.9, -.9 The wideband ACS test measures the performance of the receive uplink in the presence of a wideband adjacent channel as described in Adjacent Channel Selectivity, page 45. Figure 6 illustrates the input spectrum for this test. Table 4 lists the performance results. The minimum interference level is 44 db higher than each channel of interest. At this level, there is virtually no degradation in performance. The next step in the test is to increase the interference power level until some predetermined level of degradation (for example 3 db) is seen. The second row in Table 4 shows that the DDC can handle an additional 6 db of interference power at the cost of.6 db in CE degradation. X-ef Target - Figure 6 0 PSD of DDC Input Signal db Figure 6: PSD of DDC Input for Wideband ACS Test Table 4: Performance Data for Wideband ACS Test In-Channel SN Frequency (MHz) Interference elative Power EVM (%) CE , 5.3, 5.4, , -.9, -.9, , 33.4, 33.7, , -9.5, -9.5, -9.3 XAPP3 (v.0) October 9,

63 eceive Uplink Design & Implementation Narrowband ACS The narrowband ACS test measures the performance of the receive uplink in the presence of a narrowband adjacent channel as described in Adjacent Channel Selectivity, page 45. Figure 6 illustrates the input spectrum for this test. Table 4 lists the performance results. The minimum interference level is 47 db higher than each channel of interest. At this level, there is virtually no degradation in performance. Less than 3 db of degradation is seen at an interference level as high as = 7 db. X-ef Target - Figure 6 0 PSD of DDC Input Signal db -50 Figure 6: PSD of DDC Input for Narrowband ACS Test Table 4: Performance Data for Narrowband ACS Test In-Channel SN Frequency (MHz) Interference elative Power EVM (%) CE , 5.3, 5.4, , -.9, -.9, , 35.0, 35.5, , -9., -9.0, -9. XAPP3 (v.0) October 9,

64 eceive Uplink Design & Implementation In-Band Blocking The in-band blocking test measures the performance of the receive uplink in the presence of a blocker as described in the Blocking Characteristics section. Figure 63 illustrates the input spectrum for this test. Table 43 lists the performance results. The minimum interference level is 53 db higher than each channel of interest. At this level, there is approximately 0. db degradation in performance. Less than 3 db of degradation is seen at an interference level as high as = 7 db. X-ef Target - Figure 63 0 PSD of DDC Input Signal db -50 Figure 63: PSD of DDC Input for In-Band Blocking Test Table 43: Performance Data for In-Band Blocking Test In-Channel SN Frequency (MHz) Interference elative Power EVM (%) CE , 5.5, 5.5, , -.9, -.9, , 35., 35.4, , -9., -9.0, -9.0 XAPP3 (v.0) October 9,

65 eceive Uplink Design & Implementation Wideband Intermod The wideband intermod test measures the performance of the receive uplink in the presence of interference from wideband intermodulation as described in the Intermodulation Characteristics, page 46. The input spectrum for this test is illustrated in Figure 64 and the performance results are listed in Table 44. The minimum interference level is 44 db higher than each channel of interest. At this level, there is virtually no degradation in performance. Less than 3 db of degradation is seen at an interference level as high as 44 + = 66 db. X-ef Target - Figure 64 0 PSD of DDC Input Signal db -50 Figure 64: PSD of DDC Input for Wideband Intermod Test Table 44: Performance Data for Wideband Intermod Test In-Channel SN Frequency (MHz) Interference elative Power EVM (%) CE , 5.4, 5.4, , -.9, -.9, , 35.3, 34.9, , -9., -9., -9. XAPP3 (v.0) October 9,

66 eceive Uplink Design & Implementation Narrowband Intermod The narrowband intermod test measures the performance of the receive uplink in the presence of interference from narrowband intermodulation as described in the Intermodulation Characteristics section. The input spectrum for this test is illustrated in Figure 65 and the performance results are listed in Table 45. The minimum interference level is 44 db higher than each channel of interest. At this level, there is virtually no degradation in performance. Less than 3 db of degradation is seen at an interference level as high as 44 + = 66 db. X-ef Target - Figure 65 0 PSD of DDC Input Signal db -50 Figure 65: PSD of DDC Input for Narrowband Intermod Test Table 45: Performance Data for Narrowband Intermod Test In-Channel SN Frequency (MHz) Interference elative Power EVM (%) CE , 5.4, 5.4, , -.9, -.9, , 34.7, 35.0, , -9., -9., -9. XAPP3 (v.0) October 9,

67 eceive Uplink Design & Implementation Implementation The DDC was implemented using Xilinx System Generator version 0.. with a heavy reliance on the FI Compiler v4.0 [ef ]. The top-level DDC architecture uses a configurable subsystem to select from one of seven unique architectures that are stored in a Simulink library (see reference [ef ] for a description of using configurable subsystems in System Generator designs). The configuration choice is selected by right clicking on the top-level component and scrolling down to the Block Choice menu item as illustrated in Figure 66. X-ef Target - Figure 66 Figure 66: System Generator Block Diagram of DDC Top Level The seven architectures are based on the structures described in the Digital Up Converter Architecture section. For example, the System Generator block diagram for the x5 MHz configuration is shown in Figure 67. As a second example, the System Generator block diagram for the 4x5 MHz configuration is shown in Figure 68. X-ef Target - Figure 67 di n Fix _4_3 dou t Fix_7_6 di n dout Fix_7_6 dout Fix _7_6 dout Fi x_7_6 dout Fix_8_ 7 dout nd nd nd nd nd nd rdy rdy rdy rdy rdy rdy chan_out UFi x 0 3 chan Fs_4 _Mixer HB3 HB HB Channel _Filter 3 Figure 67: System Generator Block Diagram of DDC for x5 MHz Configuration XAPP3 (v.0) October 9,

68 eceive Uplink Design & Implementation X-ef Target - Figure 68 nd Fix_4_3 Fix_7_6 dout nd rdy rs t Fs_4_Mixer nd Fi x_7_6 dout rdy UFix 0 chan _out HB Fi x_7_6 dout_i nd Fi x_7_6 d out_q chan_i n rdy _i _q nd Fix_7_6 do ut rdy Fi x_7_6 dout nd rdy rs t HB_ 8CH Fix_8_7 di n nd dout rdy UFi x_3_0 chan_out Channel _ Filter dout rdy 3 chan 4C_Mix er HB_x4CH 3 Figure 68: System Generator Block Diagram of DDC for 4x5 MHz Configuration In most cases, the data flow from one module to the next is handled with a single TDM data signal along with an output data ready (rdy) that is used as an enable, or new data (nd), for the next downstream module. The main exception to this is in the 4x5 MHz configuration where two TDM streams are used at the output of the multi-carrier mixer in order to simplify the enabling of the subsequent filter stages. In particular, the output of the 4-carrier mixer is at a sample rate of 30.7 per complex channel. Given there are four carriers, each with an I and Q channel, the sample rate of a single TDM signal would be 45.76, which would require a non-uniform enable pattern (high for two clocks, low for one clock). This leads to a buy enable pattern at the output of the next filter stage. To keep the enables uniform, it is simpler in this case to use two TDM signals each at a sample rate of.88 and then recombine into a single TDM signal after decimating by. The data path quantization at the output of each module is maintained at 7 bits except the final stage where it grows to 8 bits. Symmetric roung is used in all cases with the exception of the fractional resampler in the x5 MHz configuration where a simple round is used to save some hardware (one DSP48E). The remainder of this section describes the implementation of each module in more detail with an emphasis on the handcrafted portions of the design. Because FI Compiler v4.0 was used, the description of the filter designs is reduced to a listing of GUI parameter settings. Fs/4 Mixer + Halfband Decimator The fi stage mixer and halfband decimator are contained in the Fs_4_Mixer module. This module is common to all seven DDC configurations. The System Generator block diagram of the design is shown in Figure 69. X-ef Target - Figure 69 Modulate EvenOddDemux Delay nd 3 Fi x_4_ 3 d z - q nd rs t do ut rdy Fi x _5 _3 nd d o ut_o dd dout_even Fix_5_3 Fix_5_3 nd di n Fi x_7_ 6 dout Fi x_7_ 6 dout _q _i do ut Fix_7_6 dout rs t rdy nd rdy nd HB4 rdy rdy rs t TDM Figure 69: System Generator Block Diagram of Fs_4_Mixer XAPP3 (v.0) October 9,

69 eceive Uplink Design & Implementation The input to the Fs_4_Mixer design is a real signal with 4 bits of precision and a sample rate of.88. The combination of the Modulate and EvenOddDemux blocks produces the ±x 0 (n) and (±x (n)) sequences described in the Digital Up Converter Architecture section. The modulated even samples, ±x 0 (n), are filtered by the halfband decimation filter labeled HB4. The delayed modulated odd samples are time division multiplexed with the filtered modulated even samples into a single output stream at a sample rate of.88 (3 clocks per sample). As with all filters in the design, the HB4 filter is implemented using the FI Compiler 4.0. As shown in Figure 70, the HB4 module consists of a single FI Compiler 4.0 instance followed by some conditioning of the output signal quantization. In particular, the signal is compressed by one MSB to remove unnecessary headroom. The quantization and scaling of the signal is such that a full scale input sine wave with 4 bits of precision is mapped to a half scale sine wave with 7 bits of precision. This initial gain of 0.5 provides protection from overflow in the downstream decimation filters that have unity passband gain and the channel filter that has a gain of.637. X-ef Target - Figure 70 nd Fix_5_3 nd dout rfd Fix_8_0 Fix_8_6 Fix _ 7_6 reinterpret cast emove MSB to reduce excessive head room. dout 3 rs t rdy rdy FI Compiler 4.0 Figure 70: System Generator Block Diagram of HB4 Module Figure 7 shows screen shots of the Filter Compiler 4.0 GUI with settings for the HB4 module. For this particular filter, the coefficients are the even coefficients of the HB4 halfband filter and are contained in the vector h0_hb4. For all filters in the DDC design, the number of filter coefficients is set to (constant coefficient filters). In this design, the filter is a single channel and single rate filter with 6 clocks per input sample. The filter architecture is specified to exploit coefficient symmetry and to use a systolic multiply accumulate structure. In all cases, the DDC filters use 8-bit signed coefficients that are specified in an integer format. Further descriptions of the GUI parameters are given in the FI Compiler 4.0 documentation [ef ]. XAPP3 (v.0) October 9,

70 eceive Uplink Design & Implementation X-ef Target - Figure 7 Figure 7: Screen Shots of FI Compiler 4.0 GUI Decimation and Channel Filtering This section summarizes the Filter Compiler 4.0 settings for each filter used in each of the seven configurations. In all cases, the number of coefficient sets is equal to one and the reloadable coefficient option is disabled. Also, all filter architectures are based on the systolic multiply accumulate structure with 8-bit signed coefficients. In most cases, the optimization goal is left at the default setting of Area ; the two exceptions being all filters in the x5 MHz configuration and the channel filter in the 4x5 MHz configuration. Also, the data buffer type and coefficient buffer type are left at the default setting of Automatic in all cases except for the 4x5 MHz channel filter where they are set to Block. Finally, all filters in the design use the and nd control options. Table 46: FI Compiler Settings for x5 MHz Configuration Parameter st Halfband nd Halfband 3 rd Halfband Channel Filter Coefficients h_hb3 h_hb h_hb h_channel_filter Filter Type Decimation Decimation Decimation Single_ate ate Change Type Integer Integer Integer Integer Decimation ate Value XAPP3 (v.0) October 9,