The EVN DBBC Project. G. Tuccari Istituto di Radioastronomia Noto, Italy. Digital Backend Workshop - Bonn, Germany

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1 The EVN DBBC Project G. Tuccari Istituto di Radioastronomia Noto, Italy

2 EVN DBBC Working Group S. Pogrebenko, S. Parsley JIVE-Dwingeloo, The Netherlansds W. Alef MPI-Radiastronomie-Bonn, Germany Y. Xiang Shanghai Observatory, China R. Millenar Astron-Westerbork, The Netherlands J. Ritakari Metsahovi Observatory, Finland H. Hinterregger Haystack Observatory-MIT, USA G. Balodis VIRAC, Latvia P. Burgess Jodrell Bank Observatory, U.K. G. Tuccari, S. Buttaccio, G. Nicotra IRA-Noto, Italy

3 DBBC Project overview The main goal is to replace the existing terminal with a complete compact system to be used with any VSI compliant recorder or data transport Four complete prototypes are to be deployed and tested in four EVN radiotelescopes The cost is limited making use of commercial components (no custom device) Hardware programmability is the main feature in order to optimize the architecture to the needed performance Maximum Input and Output data rates are the limitation and are set so to satisfy the present and near future necessities

4 DBBC Project overview (cont.) The new development is fully compatible with the existing terminals and correlators The new set of BBCs is fully up-gradable and ready to process in a future larger bandwidth with modified correlators Introduction in the stations will be soft Upgrade or improvements should be mostly only software Upgrade should also be possible in hardware replacing compatible pin-to-pin processing modules

5 DBBC General Features Four IF Input in the range or MHz Four polarizations or bands available for a single group of output data channel selection GHz fixed frequency sampling clock Channel bandwidth ranging between 250KHz to 16 MHz (prel.) Tuning step 10KHz (preliminary, any lower step is possible) Station based fringe counter-rotation Multiple architecture using fully re-configurable FPGA Core Modules Modular realization for cascaded processing Field System support

6 DBBC General Features (cont.) Data out as single or double VSI interface Total power measurement capability Continuous Tsys measurement capability Pseudo noise and tones injection Digital to analog converter monitor output Digital AGC Optional gigabit data transfer Optional autocorrelation function for improving band shape

7 DBBC General Schematic View H-Maser Synthesizer Rx 1..4 IF Gain/Band Control A/D DEMUX CORE MODULES COLLECTOR VSI-H Interfaces Linux PC Board+PCI MK5B/ Net FS PC

8 DBBC General Schematic View with Optional Modules 10G IF 10G 10G Rx 1..4 A/D TX Gain/Band Stream 1..4 Stream 1..4 RX RFI TX Control (opt) (opt.) (opt.) (opt.) H-Maser Synthesizer Stream G RX (opt.) DEMUX CORE MODULES COLLECTOR VSI-H Interfaces MK5B/ Net Linux PC Board FS PC

9 System Components Analog to digital converter environment 1024 MHz Synthesizer Demultiplexer 2:8 Core Module Board FPGAs Core Configurations PCI interface VSI-H/E Linux PC Board: System Management Software Field System Integration Optional Modules: 10 Gb/s serial link RFI Mitigation

10 Analog to digital converter environment Conversion Clock 1024 MHz MAX108 AD converter Front-end power level control Bandwidth / MHz selection/filtering Total power measurement AD temperature stabilization LVPECL level data bus Dedicated interface through PCI 1024 MHz Synthesizer

11 A/D Board Schematic View RX IF H-Maser 5/10 MHz MHz or MHz Anti-image Analog Filter 1024 MHz Synthesizer Power Level Control Clk 1024 MHz sine wave Total Power AD CONVERTER Temperature Control 2X8bit Data LVPECL differential Clk 512 MHz LVPECL differential 1PPS Interface

12 2:8 Bus Demultiplexer 4X8bit Data LVPECL differential 2:4 2X8bit Data LVPECL differential Clk 512 MHz LVPECL differential 2:4 2:4 8X8bit Data LVPECL differential Clk 256 MHz LVPECL differential Clk 128 MHz LVPECL differential

13 DBBC Core Module A single module able to process more channels More modules can be arranged in cascade External buses: HIS/HSIR, HSO, HSC, HSM HSI Input data bus, is propagated with HSIR HSO Output data bus, is shared for multiple IF access HSC Control/Configuration bus HSM Monitor bus HSX cross internal data bus

14 DBBC Core Modules Cascade Architecture Stream IF1 HSI HSI HSI HSI CORE CORE CORE CORE To Collector and VSI interface HSO HSO HSO HSO HSO HSO HSO HSO Stream IF2 CORE CORE CORE CORE Stream IF3 Stream IF4 HSI HSI HSI HSI

15 DBBC CORE Module Features Different configuration can be supported: (example) SSB down converter Wide band parallel FIR Polyphase FIR / FFT A module able to handle: Maximum Input bandwidth Gbit/s Maximum Output bandwidth Gbit/s Control/Configuration bus through a common PCI

16 DBBC CORE Module Features (cont.) Different modules with different number of gates are supported for different functionalities Std. Single Core Module up to a maximum of 32 Mgates A module with 24 Mgates can handle up to 8 channels as 4 independent narrow band LSB&USB (preliminary evaluation) A module with 24 Mgates can handle up to 4 wide band channels (ex. 1X512, 2x256, 4x128 MHz) (preliminary evaluation)

17 Core Module Board HIS/HSIR Cascade-able Input Bus HSO Shared Output bus HSC Control / Configuration bus 32bit HSM Monitor bus to DA converter 12 MHz HSX Internal data bus Maximum 4 FPGA VirII-1152pin, Internal to FPGA interface Sandwich cascade method

18 Core Module Schematic View HSI HSIR VirII VirII HSC/HSM HSX VirII VirII HSO

20 Digital Down Converter Configuration SSB conversion between high data rate sampled IF band and lower data rate base band LO as a Numerically Controlled Oscillator Mixer as Complex as Look Up Table multiplier Low-pass band filter Finite Impulse Response (FIR) filters cascade Decimation because of the high ratio between IF and output data rate performed with multirate/multistage FIR

21 Digital Down Converter Configuration Digital Total Power measurement at IF level Digital Total Power measurement at base-band level Rescaling at each processing stage Narrow bandwidth: 16, 8, 4, 2, 1, 0.5, 0.25 MHz Wide bandwidth: 512, 256, 128, 64, 32 MHz

22 Narrow Band SSB Core Schematic View Input Band direct or folded Complex Mixer / SSB 1st FIR Gain / Total Power 2nd FIR Shape FIR LSB USB NCO Each channel is independent in tuning and bandwidth More channels per core depending on the bandwidth

23 SSB Mixer Phasing Method Sine Input signal Cosine I Q -45 phase shifter +45 phase shifter + _ S LSB USB

24 Parallel Pre-computed Oscillator (PPO) Pre-computed Initial Phase t0 t1 t2 t LTU0 LTU1 LTU2 LTU3 Sine0 Cosine0 Sine1 Cosine1 Sine2 Cosine2 Sine3 Cosine3 t7 + LTU7 Sine7 Cosine7 Clock Phase Increment

25 VSI Interface Two units are used Data clock 32 or 64 MHz Input has to be compatible with differential positive logic VSI E compatibility

26 Linux PC Board: System Management Software Standard commercial PC board including HD Configuration files for each FPGA stored on HD Software interface for FPGA configuration Software interface for servicing FPGAs (I/O registers access) Software interface for A/D level control Software interface for VSI interface (DOT clock and mode selection)

27 Software Management Structure Field System PC Ethernet AD AD PCI-X PC Board + PCI HD VSI FPGA Module FPGA Module FPGA Module

28 Overall Narrow Band Example 50MHz base/16mhz bwd rd Stage First Stage nd Stage Overall

29 Overall Narrow Band Example 210MHz base/16mhz bwd rd Stage First Stage nd Stage Overall

30 Overall Narrow Band Example 450MHz base/16mhz bwd rd Stage First Stage nd Stage Overall

31 Time Schedule Months Detailed Project Definition Programmable Logic Evaluation Overall Schematic Drawings FPGA Schematic Drawings FPGA Simulation FPGA Implementation and Testing Auxiliary Functionality Prototype Boards Realization Firmware and Communication Soft. On Field Testing

PoS(11th EVN Symposium)073

PoS(11th EVN Symposium)073 Gino Tuccari, Salvo Buttaccio INAF Istituto di Radioastronomia, Contrada Renna Bassa, I-96017 Noto, Italy E-mail: g.tuccari@ira.inaf.it, Michael Wunderlich, David A. Graham, Alessandra Bertarini, Alan