Skewed CMOS: Noise-Tolerant High-Performance Low-Power Static Circuit Family

Transcription

1 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 10, NO. 4, AUGUST Skewed CMOS: Noise-Tolerant High-Performance Low-Power Static Circuit Family Alexandre Solomatnikov, Student Member, IEEE, Dinesh Somasekhar, Naran Sirisantana, Student Member, IEEE, and Kaushik Roy, Fellow, IEEE Abstract In this paper, we present a noise-tolerant high-performance static circuit family suitable for low-voltage operation called skewed logic. Skewed logic circuits in comparison with Domino logic have better scalability and they are more suitable for low voltage applications because of better noise margins. Skewed logic and its variations have been compared with Domino logic in terms of delay, power, and dynamic noise margin. A design methodology for skewed CMOS pipelined circuits has been developed. To demonstrate applicability of proposed logic style 0.35 m 5.56 ns CMOS bit multiplier has been designed using skewed logic circuits and fabricated through MOSIS. Measurement results show that the multiplier only consumed power of 195 mw due to low clock load. Index Terms Clocks, CMOS digital integrated circuits, design methodology, electromagnetic coupling, integrated circuit noise, synchronization. I. INTRODUCTION WITH advances in CMOS device technology both performance and power consumption of integrated circuits have improved dramatically. In very high performance designs, dynamic circuits like Domino ([1], [2]) are used due to their high speed. However, with continuing scaling of supply voltage and transistor threshold voltage it is more difficult to use Domino circuits because of their noise margin dependence on the threshold voltage variation [14]. This problem can be solved by using skewed logic circuits [3], [4]. Skewed circuits are fully complementary static logic circuits. The sizes of PMOS and NMOS transistors are adjusted to enable one of the transitions to be faster than the other. Changing the driving capabilities of PMOS and NMOS transistor networks is referred to as skewing. The same result can be achieved by using different supply voltages or transistors with different threshold voltages to speed up one of the transitions. In the last case the sizes of transistors need not be increased and hence the input capacitance and area are smaller at the expense of multiple power/ground lines or more complex technology process. Skewed logic gates have performance comparable to that of dynamic circuits, whereas the noise tolerance of skewed logic Manuscript received September 16, 2000; revised March 20, This work was sponsored in part by Semiconductor Research Corporation, GRANT 98-HJ-638) and in part by Intel Corporation. A. Solomatnikov is with the Department of Electrical Engineering, Stanford University, Stanford, CA USA ( sols@stanford.edu). D. Somasekhar is with the Circuits Research Laboratory, Intel Corporation, Portland, OR USA ( dinesh.somasekhar@intel.com). N. Sirisantana and K. Roy are with the Department of Electrical and Computer Engineering, Purdue University, West Lafayette, IN USA ( sirisant@ecn.purdue.edu; kaushik@ecn.purdue.edu). Digital Object Identifier /TVLSI is better because it has no floating nodes. The floating node in a Domino gate can be eliminated using a keeper device. However, the keeper cannot restore the correct state of the gate if a false transition occurs due to input glitch. Skewed logic allows a tradeoff between the delay of the gate and its noise margins. Because of higher noise tolerance skewed logic is better than Domino logic for high performance low voltage/low power applications. Similar to dynamic circuits skewed logic falls in the category of precharge-evaluate logic families. Fast transition is used for evaluation while slow transition can be used for precharge. The rest of the paper is organized as follows: Section II describes operation of skewed logic. Section III discusses pipelining with skewed logic. Two variations of skewed logic are described in Section IV. Section V compares the energy-delay results for static CMOS, Domino and different kinds of skewed logic. Section VI discusses a dynamic noise margin model and compares static CMOS, Domino, and skewed logic in terms of dynamic noise margin. Section VII describes a test chip with a skewed CMOS multiplier. II. SKEWED LOGIC Circuit topology of skewed logic gate is the same as that of classical static CMOS logic. Fig. 1(a) shows a NAND-NOR-NAND gates series connection. To speed up high-to-low transition, the sizes of NMOS transistors of the first NAND gate are increased and the sizes of PMOS transistors of pull-up network are decreased. For fast low-to-high transition the transistor widths of the NOR gate are changed in the opposite direction. The ratio of the worst case driving capabilities of pull-down and pull-up networks is called the skew. In order to achieve performance comparable to Domino circuits, the skewed gates should operate in two phases: precharge and evaluation. During precharge, all nodes are precharged to the initial state. During evaluation, the circuit performs useful work and only fast transitions can occur. To ensure that, the gate skewed for fast high-to-low transition should be followed by gate skewed for fast low-to-high transition and vice versa. An example of such a connection is shown in Fig. 1(a). Circuits shown in Fig. 1(b) and (c) should be used if fast precharge from the clock is necessary. Precharge of pipelined skewed circuits is further discussed in Section III. Skewing of a gate affects its performance in two ways: the trip point and the driving capabilities of the transistor networks change. Fig. 2 shows the dependence of the trip point for an inverter on the skew. We used models for 0.25 m CMOS technology with of approximately 0.5 V for both NMOS and /02$ IEEE

2 470 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 10, NO. 4, AUGUST 2002 Fig. 1. Circuit topology and gate connection. (a) Example of skewed logic circuit. (b) Skewed NAND gate with fast precharge to Vdd. (c) Skewed NAND gate with fast precharge to ground. Fig. 2. Inverter trip-point dependence on the skew. Fig. 3. NAND gate-delay dependence on the skew. PMOS transistors with 2.5 V supply voltage ( ). The skew of 1 corresponds to the case when the ratio between PMOS and NMOS transistor sizes is equal to 2. Delay dependence of both fast and slow transitions on the skew is shown in Fig. 3 for a NAND gate that is skewed for fast falling transition. Skew of 1 corresponds to the case where the gate has equal worst case high-to-low and low-to-high delays in the standard static CMOS logic mode, in which the worst-case low-to-high transition of NAND gate has a single PMOS device activated. However, the delays shown in Fig. 3 correspond to a NAND gate operated in a precharge/evaluate fashion when the precharge transition has every PMOS transistor activated. Because of that the precharge delay of the skewed NAND gate is less than the worst-case delay of rising transition of static CMOS gate. III. PIPELINING WITH SKEWED LOGIC A pipeline with skewed CMOS circuits can be synthesized following the same procedure as in Domino logic [5]. Fig. 4 shows a basic pipeline structure. The logic of each pipeline stage is divided into two blocks separated by latches. During the first half of the cycle, when the clock is high, logic block 1 is evaluating while latch A holds data. At the same time, logic block 2 is Fig. 4. Basic pipeline structure. being precharged and latch B is transparent. During the second half of the cycle the situation is just the opposite. This technique allows propagation of data without waiting for the precharge of the next stage. In such a pipeline, precharge, and evaluation delays of each logic block should be less than a half cycle. In the case of Domino or noise tolerant precharge (NTP) circuits (NTP circuit is shown in Fig. 1(b) with dashed inverter) [6], [7] it is easy to achieve short precharge delay because each gate is connected to the clock signal. However, in the more general case of skewed logic, which as a class of circuits includes NTP circuits, not all gates should be connected to the clock. Fig. 5 shows a logic block structure for skewed logic. In this figure the fast transition directions are designated by arrows. The gates connected to the clock have structure similar to the NTP circuits. Topology of gate 1 and 7 is shown in Fig. 1(c).

3 SOLOMATNIKOV et al.: SKEWED CMOS: NOISE-TOLERANT HIGH-PERFORMANCE LOW-POWER STATIC CIRCUIT FAMILY 471 Fig. 5. Logic block structure. Fig. 7. Multi-V skewed circuit. Fig. 6. Waveforms for circuit in Fig. 4. Circuit structure of gate 4 is shown in Fig. 1(b) without dashed inverter. In this example, we assume that the fast (evaluation) transition delay of all gates is and that the slow (precharge) transition is three times longer (3 ). We assume also that the delay from the clock ( ) of the gate connected to the clock is no greater than 3. The sizing for such skew is shown in Fig. 1. Waveforms on the outputs of the gates are shown in Fig. 6. Precharge of first, fourth, and seventh gates starts immediately after the falling edge of the clock. Hence, the precharge delay is less than half cycle. Such a technique reduces the number of gates connected to the clock in the skewed logic circuit in comparison with Domino and NTP circuits. Therefore, skewed circuits have lower clock capacitance and lower clock power consumption. Moreover, they draw a lower peak current from the power supply. Also reduction in the number of gates connected to the clock can improve the circuit performance: gates, which are not connected to the clock, are faster than those connected to the clock because they have fewer inputs and fewer transistors connected in series. Another advantage is the precharge process being more evenly distributed over time. Unlike Domino or NTP, not all skewed gates are precharged simultaneously after clock edge. This can be seen from the above example (Figs. 5 and 6). In the beginning of the precharge half cycle only three out of nine gates are precharged. The second gate is precharged only after the precharge of the first gate is completed and so on. Distributed precharge process further reduces peak current and it simplifies physical design. IV. MULTI AND MULTI SKEWED CIRCUITS Gate trip point and transistor network driving capability can be changed by using lower threshold voltage ( ) devices in the MOS network which supports faster transition while the higher devices can be used elsewhere. For example, the gate skewed for fast high-to-low transition should have low- NMOS transistors and high- PMOS transistors. Gate properties are affected at the cost of an increased process complexity. The same effects may be realized by using separate power supply and ground lines for the gates as shown in Fig. 7. Gates with fast low to high transition are connected to -high and -high while gates with fast high to low transition are connected to -low and -low. Gate trip point remains the same for single gate but changes relatively between any two connected gates since such gates must be connected to different power/ground lines. Output voltage swing is reduced in comparison with single power supply case without reduction of gatesource voltage of transistors in the fast network. Although gate speed is improved without increase of transistor sizes and input capacitance, the improvement is obtained at the expense of noise margin as well as increase of leakage power consumption when the gate is in the precharge state. At the same time dynamic power consumption is reduced because of smaller input capacitance and output voltage swing. V. ENERGY-DELAY COMPARISONS In order to evaluate different circuits families, delay, and energy per transition are measured. Various points are obtained by changing the overall gate size. Static CMOS gates have optimum (in terms of energy-delay product) ratio of about 1.5 between PMOS and NMOS transistor sizes [3]. Domino gates have a fixed keeper transistor size to pull-down network transistor size ratio of 1/6. This ratio is chosen for dynamic logic because very little change in delay or power is observed with smaller ratios. Fig. 8 compares the energy per transition, which includes precharge energy, versus delay for two cascaded two input NAND circuits forming AND-OR structure. This structure drives another NAND gate of the same size as a load. The plot for static CMOS gates is obtained at the optimum sizing. Similar plots are obtained for Domino gates, which consist of a dynamic inverter followed by a skewed (skew ratio 4) static inverter for both Domino gates with and without footer [8], [13]. However, footless Domino requires additional clock generation with addi-

4 472 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 10, NO. 4, AUGUST 2002 Fig. 8. AND-OR energy versus delay. Fig. 10. Leakage current versus skew at room temperature. Fig. 9. Total and short circuit energy versus skew. Fig. 11. Multi-V AND-OR energy versus delay. tional power overhead that cannot be taken into account in this simulation. The curves for skewed gates show fast gate delay versus energy dissipation. They are obtained by varying the skew of the gates while keeping the sum of transistor widths constant. Three curves at different total widths are plotted with the skew being varied from 1 to 5. Substantial improvement in delay is obtained without compromising the energy per transition. Skewing reduces short circuit power of the gate. To simulate and measure short circuit power we used a method similar to the method described in [9]. Fig. 9 shows that short circuit energy per transition (evaluation-precharge) of the same cascaded NAND gates reduces by about 40% when skew changes from 1to5. As shown in Fig. 10 leakage current increases with skew in the precharge state and decreases in the other state. The average leakage current will depend on the probability of each state of the gate. In general, precharge state is more likely to occur because the gate may not switch during evaluation phase. The simulation results for AND-OR multi- gates are shown in Fig. 11. One curve (solid line) shows the dependence of energy-delay on supply voltage difference ( ) with base of 2.5 V for the case when the transistor sizes are constant (skew is equal to 1). The results for simple skewed circuit with skew of 1 and for multi- circuit with equal to zero coincide. Second type of curves (dashed lines) for multi- gates show the dependencies on transistor size skewing with skew varying from 1 to 5 for constant voltage differentials between the supply lines when overall transistor sizes and total area remain the same. The curve for multi- gates with and the curve for the skewed gate at coincide. Increasing gives linear gains in both energy per transition and delay because of decrease of output voltage swing of the gate. Up to 30% delay and energy reduction is possible. In contrast the increase of reduces the drive of the MOSFET which is responsible for the precharge transition. Consequently, the speed degradation is greater for slow transition than the improvement for fast transition.

5 SOLOMATNIKOV et al.: SKEWED CMOS: NOISE-TOLERANT HIGH-PERFORMANCE LOW-POWER STATIC CIRCUIT FAMILY 473 Fig. 13. Coupling noise in circuits. Fig. 12. Multi-V AND-OR energy versus delay. In the precharge state multi- gates have higher leakage current because gate-source voltage is not equal to zero. Another drawback is the reduction in noise margin. Similar to multi- circuits two types of curves are plotted for multi- gates in Fig. 12. Solid line depicts dependence of delay and energy on the difference between the threshold voltages of fast and slow transistor networks. Dashed lines show the dependencies on transistor size skewing with skew varying from 1 to 5 for constant voltage differences in threshold voltages. The curve for multi- gates with and the curve for the skewed gate at coincide. Transistor threshold reduction results in the same delay improvement as supply voltage difference. However, power consumption of the multi- gate does not differ much form simple skewed gate because output voltage swing does not change. Multi- circuits have the same disadvantages as multigates, i.e., high leakage power in the precharged state and reduced noise margin, although their noise margin is better than that of multi-. VI. DYNAMIC NOISE MARGIN Because of high gain of complementary CMOS circuits static noise margin of skewed circuits the point where the gain is unity is close to the input trip point voltage. The dependency of the trip point of an inverter on the skew is shown in Fig. 2. Such a dependency provides a tradeoff between the noise margin and fast transition time as the skew changes. For high-performance precharge-evaluate circuit, static noise margin may not be the only metric for measuring the gate robustness. Static noise margins are important for rejecting voltage offset created on the output nodes due to leakage and noise on power supply lines. However, it does not adequately address the problem of capacitive coupling noise [3], [10]. In order to evaluate coupling noise we used dynamic noise margin model proposed in [3], [10]. In this section we present a circuit structure that is used to evaluate the robustness of a gate. Fig. 13 shows the circuit structure with coupling noise. An aggressor gate forces a transition from high to low on its Fig. 14. Peak noise voltage on the victim and affected nodes. output. This transition is coupled from the aggressor to a victim node driven by gate. The output of gate must be high for a noise problem to occur. The strength of the noise spike at the victim node is dependent on coupling coefficient. The amplitude of the spike also depends on the rise or the fall time of the aggressor and the drive strength of gate. The noise voltage induced at the output of victim gate by itself does not cause a failure until it is propagated across affected gate. If the output voltage of rises above the noise threshold determined by static noise margin of succeeding gate,we assume that a failure in functionality occurs. We evaluate the dynamic noise margin of standard static CMOS circuits, Domino, skewed multi- and multigates for simple inverters. The same HSPICE models for 0.25 m CMOS technology with 2.5 V supply voltage were used for simulation. The peak voltage of coupling noise on the victim node is shown in the left part of Fig. 14. The left chart shows maximum voltage of coupling spike for high-to-low transition. In the case of Domino logic the left chart shows an effect of coupling to

6 474 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 10, NO. 4, AUGUST 2002 the dynamic node. For skewed gates this corresponds to gates which are skewed for fast falling transition. Peak voltages versus coupling coefficient are obtained under assumption that the total victim capacitance is constant at 25 ff. Domino, skewed, multi-, and multi- gates are assumed to be precharged when the aggressor transition occurs. A skew of four is imposed on the skewed gates and Domino output inverter, whereas keeper is sized to have a size of a sixth of the pull-down network of Domino gates. Supply voltage difference for multi- gates is equal to 0.4 V. In multi- gates high- NMOS and PMOS transistors have threshold voltages equal to 0.54 V and 0.52 V, respectively while threshold voltages of low- transistors are 0.14 V and 0.12 V. All gates have similar average transistor size of 2.0 m. Left chart in Fig. 14 also shows the static noise margins of the respective affected gate as thin horizontal lines. Static noise margins for Domino and skewed gates on the left chart coincide. All voltages are expressed with reference to the victim node voltage in steady state. It is clear that a stronger drive provided on the victim node decreases the strength of the spike for static gates. Very high values of ff are required before the trip voltage of the affected gate is crossed. The left chart shows that Domino exhibits slightly higher peak voltage than the skewed gates primarily because the victim node is very weakly driven by a keeper device. A coupling capacitance of 22 ff is needed for the static noise margin to be exceeded for Domino, while must exceed 26 ff for the case of skewed logic. The peak noise voltages at the output of the affected gate are shown in the right chart of Fig. 14. Simulation conditions are identical to those in previous figure. The static noise margins of the respective succeeding gate ( in Fig. 13) are shown as thin horizontal lines. Static CMOS gates clearly offer very high degree of noise tolerance. A failure occurs only when ff. values greater than 28 ff cause a failure on the input of affected Domino gate in the case of low-to-high noise spike on the affected node. In comparison skewed gates need ff to cause a failure. The higher performance and lower power consumption of multi- gates are obtained at the expense of reduced noise margins: ff causes a failure. Reduction of threshold voltage in multi- gates also decreases dynamic noise margin of the gate but dynamic noise margin of multi- gate is better than that of multi- gates: ff can cause a failure. The results for multi- gates show that skewed logic gates can be robust even in the case of lowered threshold voltage. Fig. 15. Block diagram of the multiplier. VII. SKEWED LOGIC MULTIPLIER TEST CHIP In order to check applicability of skewed logic circuits, we designed and fabricated through MOSIS a test chip with bit multiplier using design rules for 0.35 m CMOS technology with 3.3 V supply voltage. The multiplier, which block diagram is shown in Fig. 15, consists of a Booth encoder, a Wallace tree and the final adder. The latency of multiplier is one cycle. Fig. 16. Test-chip photo. During the first half cycle the Booth encoder produces partial products and Wallace tree sums the partial products. Final summation is performed in the second half cycle by the final carry select adder. Test-chip photo is shown in Fig. 16. Measured

7 SOLOMATNIKOV et al.: SKEWED CMOS: NOISE-TOLERANT HIGH-PERFORMANCE LOW-POWER STATIC CIRCUIT FAMILY 475 TABLE I MULTIPLIER MEASUREMENT RESULTS results are summarized in Table I. All data are presented for highest possible clock rate. Cells connected to the clock are designated in Fig. 15 by arrows. Out of 386 logic cells only 116 are connected to the clock. This confirms that skewed circuits have lower clock load and power dissipation than Domino circuits. [9] A. Alvandpour, P. Larsson-Edefors, and C. Svensson, Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuits, in Proc. IEEE Int. Symp. Low Power Electronics and Design, Monterey, CA, Aug. 1998, pp [10] D. Somasekhar, S. H. Choi, K. Roy, Y. Ye, and V. De, Dynamic noise analysis in precharge-evaluate circuits, in Proc. Design Automation Conf. 00, Anaheim, CA, June 2000, pp [11] A. Solomatnikov, D. Somasekhar, and K. Roy, Skewed CMOS: Noise-immune high-performance low-power static circuit family, in Proc. Eur. Solid-State Circuits Conf. (ESSCIRC 00), Stockholm, Sweden, Sept. 2000, pp [12] T. Ghani, K. Mistry, P. Packan, S. Thompson, M. Stettler, S. Tyagi, and M. Bohr, Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors, in Proc Symp. VLSI Technology Dig. Tech. Papers, Honolulu, HI, June 2000, pp [13] D. Harris, Skew-Tolerant Circuit Design. New York: Morgan Kaufmann, [14] M. Bohr, MOS transistors: Scaling and performance trends, Semiconductor Int., vol. 18, no. 6, p. 75, 76, 78, 80, June VIII. CONCLUSION This paper describes a new noise tolerant high-performance low-power skewed static logic circuit family and its variations. Skewed circuits have better noise tolerance than Domino circuits while the performance of skewed logic is approximately comparable to that of Domino. Another advantage of skewed logic is reduced clock capacitance, clock power dissipation, and reduced peak current of power supply/ground lines. These characteristics make skewed CMOS very promising for high performance low-power/low-voltage design. Alex Solomatnikov (S 02) received the B.S. and M.S. degrees from the Moscow Institute of Physics and Technology, Moscow, Russia, in 1997 and 1998, respectively. He is currently working toward the Ph.D. degree in the Department of Electrical Engineering, Stanford University, Stanford, CA. From August 1999 to September 2000, he was with the Electrical and Computer Engineering Department of Purdue University, West Lafayette, IN, where he received the Birck Graduate Fellowship. From 1997 to 1999, he was with Moscow Center of SPARC Technologies, Russia, where he was involved in the design of low-voltage CMOS circuits, design of cache memory for VLIW microprocessor, and memory compiler design. His current research interests are VLSI design, microprocessor design, and reconfigurable computer architectures. ACKNOWLEDGMENT The authors would like to thank L. Parvizi for helping with layout design. This work was done while the authors were at Purdue University. REFERENCES [1] R. H. Krambeck et al., High-speed compact circuits with CMOS, IEEE J. Solid-State Circuits, vol. SSC-17, pp , June [2] N. F. Goncalves and H. J. Mari, NORA: A race-free dynamic CMOS technique for pipelined logic structure, IEEE J. Solid-State Circuits, vol. SSC-18, pp , June [3] D. Somasekhar, Power and Dynamic Noise Considerations in High Performance CMOS VLSI Design, Ph.D., Purdue University, West Lafayette, IN, [4] T. Thorp, G. Yee, and C. Sechen, Monotonic static CMSO and dual V technology, in Proc. IEEE Int. Symp. Low Power Electronics and Design, San Diego, CA, June 1999, pp [5] D. W. Dobberpuhl et al., 200-MHz 64-bit dual-issue CMOS microprocessor, Digital Tech. J., vol. 4, no. 4, pp. 1 19, [6] F. Murabayashi et al., 2.5 V CMOS circuit design technique for a 200 MHz superscalar RISC processor, IEEE J. Solid-State Circuits, vol. 31, pp , July [7] H. Yamada et al., A 13.3 ns double-precision floating-point ALU and multiplier, in Proc. IEEE Int. Conf. Computer Design: VLSI in Computers and Processors, Austin, TX, Oct [8] D. Harris and M. Horowitz, Skew-tolerant domino circuits, IEEE J. Solid-State Circuits, vol. 32, pp , Nov Dinesh Somasekhar received the B.S. degree in electronics (with honors) from Maharaja Sarajirao University of Baroda, India, in 1989, the M.S. degree in electrical communication engineering from the Indian Institute of Science, Bangalore, India, in 1991, and the Ph.D. degree from the Department of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, in He is now with Circuits Research Laboratory, Intel Corporation, Portland, OR. His research interests include low-power high-performance integrated circuit design, leakage reduction techniques for CMOS VLSI, arithmetic unit architectures, and asynchronous design methodologies. VLSI design. Naran Sirisantana (S 99) received the B.Eng. degree in electrical engineering (first-class honors) from Chulalongkorn University, Bangkok, Thailand, in 1998 and the M.S. degree in electrical engineering from Purdue University, West Lafayette, IN, in He is currently working toward the Ph.D. degree in electrical engineering at Purdue University. He is a Hewlett-Packard SRC Research Fellow. He has interned at Intronics Co., Ltd., Bangkok, and at Intel Corporation, Portland, OR. His research interest is in the area of low-power high-performance

8 476 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 10, NO. 4, AUGUST 2002 Kaushik Roy (S 83 M 90 SM 95 F 02) received the B.Tech. degree in electronics and electrical communications engineering from the Indian Institute of Technology, Kharagpur, India, in 1983 and the Ph.D. degree from the Electrical and Computer Engineering Department, University of Illinois at Urbana-Champaign, in He was with the Semiconductor Process and Design Center of Texas Instruments, Dallas, TX, where he worked on field-programmable gate arrays (FPGA) architecture development and low-power circuit design. He joined the Electrical and Computer Engineering Faculty at Purdue University, West Lafayette, IN, in 1993, where he is currently a Purdue University Faculty Scholar Professor. He has published more than 200 papers in refereed journals and conferences, holds five patents, and is coauthor of Low Power CMOS VLSI Design (New York: Wiley, 2000). His research interests include VLSI design/cad with particular emphasis in low-power electronics for portable computing and wireless communications, VLSI testing, and verification and reconfigurable computing. Dr. Roy received the National Science Foundation Career Development Award in 1995, the IBM Faculty Partnership Award, the ATT/Lucent Foundation Award, the Best Paper Awards at the 1997 International Test Conference and 2000 International Symposium on Quality of IC Design. He is on the editorial board of IEEE DESIGN AND TEST, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, and IEEE TRANSACTIONS ON VLSI SYSTEMS. He was guest editor for a Special Issue on Low-Power VLSI in the IEEE DESIGN AND TEST (1994) and in the IEEE TRANSACTIONS ON VLSI SYSTEMS (June 2000).