9 Static Induction Devices

Transcription

1 9 Static Induction Devices Bogdan M. Wilamowski, Ph.D. Alabama Microelectronics Science and Technology Center, Auburn University, Alabama, USA Summary Introduction Theory of Static Induction Devices Characteristics of Static Induction Transistor Biolar Mode Oeration of SI devices (BSIT Emitters for Static Induction Devices Static Induction Diode Lateral Punch-through Transistor Static Induction Transistor Logic BJT Saturation Protected by SIT Static Induction MOS Transistor Sace Charge Limiting Load (SCLL Power MOS Transistors Static Induction Thyristor Gate Turn Off Thyristor References Summary Several devices from the static induction family such as: static induction transistor (SIT, static induction diode (SID, static induction thyristor, lateral unch-through transistor (LPTT, static induction transistor logic (SITL, static induction MOS transistor (SIMOS, and sace charge limiting load (SCLL are described. The theory of oeration of static induction devices is given for both a current controlled by a otential barrier and a current controlled by sace charge. The new concet of a unch-through emitter (PTE, which oerates with majority carrier transort, is resented. 9.1 Introduction Static induction devices were invented in 1975 by J. Nishizawa [1] and for many years Jaan was the only country where static induction family devices were successfully fabricated. Static induction transistor can be considered as a short channel junction field effect transistor (JFET device oerating in re-unch-through region. The number of devices in this family is growing with time. The SIT can oerate with the ower over 1 kw at 1 khz; above 15 W at 3 GHz. [2]. These devices may oerate uto THz frequencies [3, 4]. Static induction transistor logic had 1 times smaller switching energy than its I 2 L cometitor [5, 6]. Static induction thyristor has many advantages over the traditional silicon controlled rectifier (SCR, and SID exhibits high switching seed, large reverse voltage, and low forward voltage dros [7]. 9.2 Theory of Static Induction Devices The cross section of the SIT is shown in Fig. 9.1, while its characteristics are shown in Fig An induced electrostatically otential barrier controls the current in static induction devices. The derivations of formulas will be done for an n-channel device, but the obtained results, with a little modification can also be alied to -channel devices. For a small electrical field existing in the vicinity of the otential barrier, the drift and diffusion current can be aroximated by J n = qn(xµ n dϕ(x dx + qd n dn(x dx (9.1 Coyright 7, 1, Elsevier Inc. All rights reserved. 133

2 134 B. M. Wilamowski source Eq. (9.3 reduces to J n = x 2 qd n N S x 1 ex ( ϕ(x/v T dx (9.5 drain FIGURE 9.1 Cross section of the static induction transistor. I 1 DS [ma] 6 6 VGS 8 Note that the above equations derived for SIT can also be used to find current in any devices controlled by a otential barrier, such as a biolar transistor, MOS transistor oeration in subthreshold mode, or in a Schottky diode. 9.3 Characteristics of Static Induction Transistor Samles of the otential distribution in the SI devices are shown in Fig. 9.3 [7]. The vicinity of the otential barrier can be aroximated using arabolic formulas (Fig. 9.4 along and across the channel [8, 9] [ ϕ(x = 1 (2 x ] 2 L 1 ( V DS FIGURE 9.2 Characteristics of the early SIT design [1]. where D n = µ n V T and V T = kt /q. By multilying both sides of the equation by ex ( ϕ(x/v T and rearranging ( J n ex ϕ(x [ ( d = qd n n(x ex ϕ(x ] V T dx V T [V] ( Integrating from x 1 to x 2 one can obtain J n = qd n n(x 2 ex ( ϕ(x 2 /V T n(x1 ex ( ϕ(x 1 /V T x 2 With the following boundary conditions x 1 ex ( ϕ(x/v T dx (9.3 ϕ(x 1 = ; n(x 1 = N S ϕ(x 2 = V D ; n(x 2 = N D ( FIGURE 9.3 Potential distribution in SIT: view from the source side and view from the drain side.

3 9 Static Induction Devices 135 L Φ 2Φ FIGURE 9.4 Potential distribution in the vicinity of the barrier aroximated by arabolic shaes. [ ϕ(y = 1 (2 y ] 2 W 1 W Φ (9.7 where L is the channel length and v sat 1 11 µm/s is the carrier saturation velocity. In ractical devices, the current voltage relationshi is described by an exonential relationshi, Eq. (9.9, for small currents, a quadratic relationshi, Eq. (9.11, and finally for large voltages by an almost linear relationshi, Eq. (9.12. Static induction transistor characteristics drawn in linear and logarithmic scales are shown in Figs. 9.5 and 9.6, resectively. I DS [ma] Integrating Eq. (9.5 first along the channel and then across the channel, yields a very simle formula for drain currents in n-channel SITs I D = qd N S Z W ( L ex (9.8 V T V G = 18 where is the otential barrier height in reference to the source otential, N S is the electron concentration at the source, W/L ratio describes the shae of the otential saddle in vicinity of the barrier, and Z is the length of the source stri. Since barrier height can be a linear function of and drain voltages; therefore, [V] V DS I D = qd N S Z W L ex( a ( V GS + bv DS + /VT (9.9 FIGURE 9.5 Characteristics of the SIT drawn in a linear scale. The above equation describes characteristics of SIT for small current range. For large current levels, the device current is controlled by the sace charge of moving carriers. In the onedimensional case, the otential distribution is described by the Poisson equation: d 2 ϕ = ρ(x = I DS dx 2 ε Si ε Av(x (9.1 I DS [A] V G = 15 where A is the effective device cross section and v(x is carrier velocity. For a small electrical field v(x = µe(x and the solution of Eq. (9.1 is I DS = 9 8 V 2 DS µε Siε A L 3 (9.11 and for a large electrical field v(x = const and Eq. (9.1 results in: I DS = 2V DS v sat ε Si ε A L 2 ( V DS [V] FIGURE 9.6 Characteristics of the SIT drawn in a logarithmic scale.

4 136 B. M. Wilamowski 9.4 Biolar Mode Oeration of SI devices (BSIT I DS [µa] The biolar mode of oeration of SIT was first reorted in 1976 by Nishizawa and Wilamowski [5, 6]. Several comlex theories for the biolar mode of oeration were develoed [1 14], but actually the simle formula given by Eq. (9.5 works well not only for the tyical mode of the SIT oeration, but also for the biolar mode of the SIT oeration. Furthermore, the same formula works very well for the classical biolar transistors. Tyical characteristics of the SI transistor oerating in normal and in biolar modes are shown in Figs. 9.7 and 9.8. A otential barrier controls the current in the SIT and it is given by 1 5 I G =5µA 4µA 3µA µa 1µA 5µA 2µA I G = qd n N S J n = x 2 ( ex ϕ(x V T dx x 1 ( V DS [V] FIGURE 9.8 Small size SIT transistor characteristics, oerating in both the normal and biolar modes, I D = f (V DS with I G as a arameter. where ϕ(x is the rofile of the otential barrier along the channel. For examle, in the case of nn biolar transistors, the otential distribution across the base in reference to emitter otential at the reference imurity level N E = N S is described by: I DS [µa] 1 5 ϕ(x = V T ln V GS =.75V ( 2 ( N B (xn S ni 2 ex V BE V T V GS =.7V V GS =.65V.6V 4.5V.4V.3V V.5V 1V 2V 3V V DS [V] (9.14 FIGURE 9.7 Small size SIT transistor characteristics, oerating in both the normal and biolar modes, I D = f (V DS with V GS as a arameter. After inserting Eq. (9.14 into Eq. (9.13, one can obtain the well-known equation for electron current injected into the base J n = qd nni 2 x 2 ex N B (xdx x 1 ( VBE V T (9.15 If Eq. (9.13 is valid for SIT and BJT, then one may assume that it is also valid for the biolar mode of oeration of the SIT transistor. This is a well-known equation for the collector current in the biolar transistor, but this time it was derived using the concet of the current flow through the otential barrier. 9.5 Emitters for Static Induction Devices One of the disadvantages of the SIT is the relatively flat shae of the otential barrier (Fig. 9.9a. This leads to slow, diffusionbased transort of carriers in the vicinity of the otential barrier. The carrier transit time can be estimated using the formula: t transit = l2 eff D (9.16 where l eff is the effective length of the channel and D = µv T is the diffusion constant. In the case of a traditional SIT transistor, this channel length is about 2 µm while in the case of SIT transistors with sharer barriers (Fig. 9.9b the channel length is reduced to about.2 µm. The corresonding transient times are 2 ns and s, resectively.

5 9 Static Induction Devices FIGURE 9.9 Potential distributions in SIT: traditional and with shar otential barrier. Potential distributions shown in Fig. 9.3 are valid for SIT with an emitter made of a traditional n junction. A much narrower otential barrier can be obtained when other tye of emitter is being used. There are two well-known emitters: (1 n junction (Fig. 9.1a and (2 Schottky junction (Fig. 9.1b. For silicon devices, n junctions have a forward voltage dro of.7.8 V, while Schottky emitters have.2.3 V only. Since the Schottky diode is a majority carrier device, the carrier storage effect is negligible. Another interesting emitter structure is shown in Fig. 9.1c. This emitter has all the advantages of the Schottky diode, with majority carrier injection, even though it is fabricated out of n junctions. The concet of static induction devices can be used indeendently of the tye of emitter shown in Fig With Schottky tye and unch-through tye emitters, the otential barrier is much narrower and this results in faster resonse time and larger current gain in the biolar mode of oeration. 9.6 Static Induction Diode The biolar mode of oeration of SIT can also be used to obtain diodes with low forward voltage dro and negligible carrier storage effect [1, 11, 13, 15]. A static induction 25 (c FIGURE 9.1 Various structures of emitters: n junction including heterostructure with SiGe materials; Schottky junction; and (c unch-through emitter (in normal oeration condition the region is deleted from carriers. diode (SID can be obtained by shorting a to the emitter of the SIT [16, 17]. Such diode has all the advantages of the SIT such as thermal stability and short switching time. The cross section of such diode is shown in Fig The quality of the SID can be further imroved with more sohisticated emitters (Figs. 9.1b and c. The SI diode with Schottky emitter was described by Wilamowski in 1983 [18] (Fig A similar structure was later ublished by Baliga [19]. 9.7 Lateral Punch-through Transistor Fabrications of SI transistors usually require very sohisticated technology. It is much simler to fabricate a lateral unchthrough transistor, which oerates on the same rincile and has similar characteristics [] (Fig The cross section of the LPTT is shown in Fig Static Induction Transistor Logic The static induction transistor logic (SITL was roosed by Nishizawa and Wilamowski [5, 6]. This logic circuit has almost 1 times better ower-delay roduct than its I 2 L cometitor. Such drastic imrovement of the ower-delay roduct is ossible because the SITL structure has a significantly smaller junction arasitic caacitance and also the voltage swing

6 138 B. M. Wilamowski SIT SIT Schottky cathode FIGURE 9.11 section. emitter cathode Static induction diode: circuit diagram and cross is reduced. Figs and 9.16 illustrate the concet of SITL. Measured characteristics of n-channel transistor of the static induction logic are shown in Fig BJT Saturation Protected by SIT The SI transistor can also be used instead of a Schottky diode to rotect a biolar junction transistor against saturation [21]. This leads to faster switching time. The concet is shown in Figs and Note that this aroach is advantageous to the solution with Schottky diode, since it does not require additional area on a chi and it does not introduce additional caacitance between the base and the collector. The base collector caacitance is always enlarged by the Miller effect and this leads to slower switching in the case of the solution with the Schottky diode. 9.1 Static Induction MOS Transistor The unch-through transistor with MOS-controlled was described in 1983 [22, 23]. In the structure in Fig. 9.a current (c cathode FIGURE 9.12 Schottky diode with enlarged breakdown voltages: circuit diagram; and (c two cross section of ossible imlementation. Drain Drain Gate Emitter Gate Drain + + n+ Gate Emitter Gate Drain FIGURE 9.13 Structures of the lateral unch-through transistors: simle and with sharer otential barrier. can flow in a similar fashion as in the lateral unch-through transistor []. In this mode of oeration, carriers are moving far from the surface with a velocity close to the saturation velocity. The real advantage of such structure is the very low caacitance.

7 9 Static Induction Devices 139 I D [ma] T=298K T=4K I D 1mA 2 1 V G =V 2V 4V 6V 8V 1V 12V 14V 16V V GS V to.8v with.1v ste V DS 1V [V] FIGURE 9.17 Measured characteristics of n-channel transistor of the logic circuit of Fig V DS FIGURE 9.14 Characteristics of lateral unch-through transistor. C Schottky C B n+ FIGURE 9.15 Cross section of SIT logic. B SIT E E FIGURE 9.18 Protection of biolar transistor against dee saturation: using Schottky diode and using SIT. suly current B E C out1 out2 out3 in FIGURE 9.19 Cross sections of biolar transistors rotected against dee saturation using SIT. FIGURE 9.16 Diagrams of SIT logic. Another imlementation of static induction MOS transistor (SIMOS is shown in Fig The buried + layer is connected to the substrate, which has a large negative otential. As a result, the otential barrier is high and the emitter drain current cannot flow. The unch-through current may start to flow when the ositive voltage is alied to the and in this way the otential barrier is lowered. The -imlant layer is deleted and due to the high horizontal electrical field under the there is no charge accumulation under this. Such a transistor has several advantages over the traditional MOS transistor. 1. The caacitance is very small, since there is no accumulation layer under the. 2. Carriers are moving with a velocity close to saturation velocity. 3. Much lower substrate doing and the existing deletion layer lead to much smaller drain caacitance.

8 14 B. M. Wilamowski + imlant deletion + Emitter deletion Drain Emitter Drain Gate + deletion n n Emitter n Drain FIGURE 9. MOS controlled unch-through transistor: transistor in the unch-through mode for the negative otential and transistor in the on-state for the ositive otential. FIGURE 9.21 to view. Emitter Drain Static induction MOS structure: cross section and The device oerates in a similar fashion as MOS transistor in subthreshold conditions, but this rocess occurs at much higher current levels. Such biolar mode of oeration may have many advantages in VLSI alications Sace Charge Limiting Load (SCLL FIGURE 9.22 Sace charge limiting load (SCLL. Using the concet of the sace charge limited current flow it is ossible to fabricate very large resistors on a very small area. Moreover these resistors have a very small arasitic caacitance. For examle, a 5 k resistor requires only several square µm when 2 µm feature size technology is used [7]. Deending on the value of the electrical field, the device current is described by the following two equations. For a small electrical field v(x = µe(x For a large electrical field v(x = const I DS = 9 8 V 2 DS µε Siε A L 3 (9.17 I DS = 2V DS v sat ε Si ε A L 2 (9.18 Moreover these resistors, which are based on the sace charge limit flow, have a very small arasitic caacitance Power MOS Transistors Power MOS transistors are being used for fast switching ower sulies and for switching ower converters. They can be driven with relatively small ower and switching frequencies could be very high. High switching frequencies lead to comact circuit imlementations with small inductors and small caacitances. Basically only two technologies, DMOS and VMOS, are used for ower MOS devices as shown in Figs and 9.24.

9 9 Static Induction Devices 141 source source FIGURE 9.23 oly FIGURE 9.24 drain Cross section of the VMOS transistor. source drain oly Cross section of the DMOS transistor. A more oular structure is the DMOS shown in Fig This structure also uses the SIT concet. Note that for large drain voltages the n-region is deleted from carriers and statically induced electrical field in the vicinity of the virtual drain is significantly reduced. As a result this transistor may withstand much larger drain voltages and also the effect of channel length modulation is significantly reduced. The later effect leads to larger outut resistances of the transistor. Therefore, the drain current is less sensitive to drain voltage variations. The structure in Fig can be considered as a comosition of the MOS transistor and the SIT transistor as is shown in Fig The major disadvantage of ower MOS transistors is relatively large drain series resistance and much smaller transconductance in comarison to biolar transistors. Both of these arameters can be imroved dramatically by a simle change of the tye of drain. In the case of n-channel device from n-tye to -tye drain. This way the integrated structure is being built where its equivalent diagram consists MOS transistor integrated with biolar transistor. Such structure has β times larger transconductance (β is the current gain of biolar transistor and much smaller series resistance due to the conductivity modulation effect caused by holes injected into lightly doed drain region. Such device is known as insulated biolar transistors (IGBT shown in Fig Their main disadvantage is large switching time limited rimarily by oor switching erformance of biolar transistor. Another difficulty is related to a ossible latch-u action of four layer n + structure. This undesired effect could be suressed by using heavily doed + region in the base of NPN structure, which leads to significant reduction of the current gain of this arasitic transistor. The gain of other PNP transistor must be ket large so the transconductance of the entire device is large too. The IGBT transistor has breakdown voltages u to 15 V, turn-off times are in range.1.5 µs. They may oerate with currents above 1 A with a forward voltage dro about 3 V. oly source drain oly D C SIT PNP G MOS G NPN R P S E FIGURE 9.25 of Fig Equivalent diagram with MOS and SIT of the structure FIGURE 9.26 Insulated biolar transistor (IGBT: cross section and equivalent diagram.

10 142 B. M. Wilamowski 9.13 Static Induction Thyristor There are several secial semiconductor devices dedicated to high ower alications. The most oular is thyristor known also as silicon control rectifier (SCR. This device has a four layer structure Fig. 9.27a and it can be considered as two transistors nn and n connected as shown in Fig. 9.27b. In normal mode of oeration ( has ositive otential only one junction is reverse-biased and it can be reresented by caacitance C. A sike of voltage can therefore get through caacitor C and it can trigger SCR. This behavior is not accetable in ractical alication and therefore a different device structure is being used as is shown in Fig Note that by shorting to cathode by resistor R it is much more difficult to trigger the nn transistor by sike of voltage. This way raid change of voltages is not able to trigger thyristor. Therefore this structure has very large dv/dt arameter. When NPN transistor is relaced with SI transistor arameters of a thyristor can be significantly imroved. For examle, with breaking voltage in the range of 5 kv and current of 6 A the switching on time can be as short as 1 ns and dv/dt arameter can be as large as 5 kv/s [15, 24]. Most of the SCRs sold in the market comrise an integrated structure comosed of two or more thyristors. This structure cathode Silicon control rectifier: cross section and equiva- FIGURE 9.27 lent diagram. + C n nn + cathode FIGURE 9.28 Silicon control rectifier with larger dv/dt arameter: cross section and equivalent diagram. C n R nn + cathode FIGURE 9.29 Integrated structure of silicon control rectifier: cross section and equivalent diagram. FIGURE 9.3 cathode + n SIT GTO SIT: cross section and equivalent diagram. has both large dv/dt and di/dt arameters. This structure consists of internal thyristor which significantly amlifies the signal. One can notice that the classical thyristor as shown in Fig can be turned off by the voltage while integrated SCR shown in Fig can be only turned off by reducing current to zero. Most of the SCRs sold in the market have an integrated structure comosed of two or more thyristors. This structure has both large dv/dt and di/dt arameters Gate Turn Off Thyristor For the dc oeration it is imortant to have a thyristor which can be turned off by the voltage. Such thyristor has a structure similar to the one shown in Fig It is imortant, however, to have significantly different current gains β for n and nn transistors. The current gain of nn transistor should be as large as ossible and the current gain of n transistor should be small. The roduct of β nn and β n should be larger than one. This can be easily imlemented using SI structure as shown in Fig References 1. Nishizawa J., Terasaki T., and Shibata J., Field-Effect Transistor versus Analog Transistor (Static Induction Transistor, IEEE Trans. on Electron Devices, vol. 22, No. 4, , Aril 1975.

11 9 Static Induction Devices Tatsude M., Yamanaka E., and Nishizawa J., High-Frequency High-Power Static Induction Transistor, IEEE Industry Alication Magazine,. 4 45, March/Aril Nishizawa J., Plotka P., and Kurabayashi T., Ballistic and Tunneling GaAs Static Induction Transistors: Nano-Devices for THz Electronics, IEEE Trans. on Electron Devices, vol. 49, No. 7, , Nishizawa J., Suto K., and Kurabayashi T., Recent Advance in Tetrahertz Wave and Material Basis, Russian Physics Journal, vol. 46, No. 6, , Nishizawa J. and Wilamowski B. M., Integrated Logic State Induction Transistor Logic, International Solid State Circuit Conference, Philadelhia USA, , Nishizawa J. and Wilamowski B. M., Static Induction Logic A Simle Structure with Very Low Switching Energy and Very High Packing Density, International Conference on Solid State Devices, Tokyo, Jaan, , 1976 and Journal of Jaanese Soc. Al. Physics, vol. 16, No. 1, , Wilamowski B. M., High Seed, High Voltage, and Energy Efficient Static Induction Devices, 12 Symosium of Static Induction Devices SSID 99, (invited seech Tokyo, Jaan, , Aril 23, Plotka P. and Wilamowski B. M., Interretation of Exonential Tye Drain Characteristics of the SIT, Solid-State Electronics, vol. 23, , Plotka P. and Wilamowski B. M., Temerature Proerties of the Static Induction Transistor, Solid-State Electronics, vol. 24, , Kim C. W., Kimura M., Yano K., Tanaka, A., and Sukegawa, T., Biolar-Mode Static Induction Transistor: Exeriment and Two- Dimensional Analysis, IEEE Trans. on Electron Devices, vol. 37, No. 9,. 7 75, Setember Nakamura Y., Tadano H., Takigawa M., Igarashi I., and Nishizawa J., Exerimental Study on Current Gain of BSIT, IEEE Trans. on Electron Devices, vol. 33, No. 6, , June Nishizawa J., Ohmi T., and Chen H. L., Analysis of Static Characteristics of a Biolar-Mode SIT (BSIT, IEEE Trans. on Electron Devices, vol. 29, No. 8, , August Yano K., Henmi I., Kasuga M., and Shimizu A., High-Power Rectifier Using the BSIT Oeration, IEEE Trans. on Electron Devices, vol. 45, No. 2, , February Yano K., Masahito M., Moroshima H., Morita J., Kasuga M., and Shimizu A., Rectifier Characteristics Based on Biolar-Mode SIT Oeration, IEEE Electron Device Letters, vol. 15, No. 9, , Setember Hironaka R., Watanabe M., Hotta E., and Okino A. Performance of Pulsed Power Generator using High Voltage Static Induction Thyristor, IEEE Trans. on Plasma Science, vol. 28, No. 5, ,. 16. Yano K., Honarkhah S., and Salama A., Lateral SOI Static Induction Rectifiers, Proc. of 1 Int. Sym. on Power Semiconductor Devices, Osaka, , Yano K., Hattori N., Yamamoto Y., and Kasuga M., Imacts of Channel Imlantation on Performance of Static Shielding Diodes and Static Induction Rectifiers, Proc. of 1 Int. Sym. on Power Semiconductor Devices, Osaka, , Wilamowski B. M., Schottky Diodes with High Breakdown voltage, Solid-State Electronics, vol. 26, No. 5, , Baliga B. J., The Pinch Rectifier: A Low Forward-Dro, High-Seed Power Diode, IEEE Electron Device Letters, vol. 5, , Wilamowski B. M. and Jaeger R. C., The Lateral Punch-Through Transistor, IEEE Electron Device Letters, vol. 3, No. 1, , Wilamowski B. M., Mattson R. H., and Staszak Z. J., The SIT saturation rotected biolar transistor, IEEE Electron Device Letters, vol. 5, , Wilamowski B. M., The Punch-Through Transistor with MOS Controlled Gate, Phys. Status Solidi, vol. 79, , Wilamowski B. M., Jaeger R. C., and Fordemwalt J. N., Buried MOS Transistor with Punch-Through, Solid State Electronics, vol. 27, No. 8/9, , Shimizu N., Sekiya T., Iida K., Imanishi Y., Kimura M., and Nishizawa J., Over 55kV/us, dv/dt turnoff characteristics of 4kV- Static Induction Thyristor for Pulsed Power Alications, Proc. of 4 Int. Sym. on Power Semiconductor Devices, Kitakyushu, Jaan, , 4.

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