4/17/01. Design Seminar. Agilent EEsof Customer Education and Applications. MESFET Power Amplifier Design: Small Signal Approach

Transcription

1 Design Seminar Agilent EEsof Customer Education and Applications MESFET Power Amplifier Design: Small Signal Approach 1

2 About the Author Al Sweet PhD, Cornell University Design Engineering: RF/microwave circuits Consultant to the industry since Author: MMIC and MIC Amplifier and Oscillator Design, Artech House, Page 2 BIOGRAHPICAL SKETCH Al Sweet is a consultant to industry in the area of RF and Microwave circuit design. He began consulting in 1979, after working for MA/COM, Varian Associates, and the Watkins-Johnson Company after completing his PhD degree at Cornell University in Between 1992 and 1997 Al worked full time for Rockwell and Wireless Data Corp (where he was Vice President of Engineering), but returned to Consulting in Today he is very active as a design consultant in all facets of RF and Microwave circuit design, and his clients include many of the leading wireless companies in Silicon Valley and around the World. In 1990 Al published an industry standard text/reference book MMIC and MIC Amplifier and Oscillator Design (Artech House, 1990) in which he describes design as a methodical process from specification definition to circuit fabrication. Al is married and has seven grown children. His hobbies include amateur radio, many forms of music (he plays guitar and enjoys listening to music CD s), reading, and travel. He and his wife Fran and their dog Pacey (a 90 pound Doberman) live in a turn of the century Craftsman house in Alameda California. 2

3 Basic engineering problem: How to design a Power Amplifier without a large signal device model? Many device manufacturers do not supply large signal device models for their devices. Most often the only design data supplied is the device small signal S-parameters and static IV curves. This data is sufficient to perform a first order power amplifier design using the load line method first described by Steve Cripps. Page 3 Power amplifiers are inherently large signal components because their behavior as power saturation is approached is nonlinear by nature. However, in many cases, designers have only a set of measured small signal S parameters as a starting point for representing the active device in circuit simulations. Since these S parameters are only applicable to small signal levels, it is not clear how the design is to be accomplished in terms of maximizing RF power output and linearity at large signal levels. A first order design may be done by following a method first described by Steve Cripps, in which the device s static IV curves are used to determine a large signal load line impedance (RL), which is used as the goal impedance to be presented to the device s drain terminals by the output matching circuit. By following this method, the designer may optimize the output circuit for maximum RF power output and at the same time optimize the input circuit for best input match and maximum gain. In general the output match will be poor, because it is intentionally mismatched inorder to achieve maximum RF power generation (I.e. the output match is optimized on RL rather than the device's S22). 3

4 Limitations of this technique Optimizes for max Psat only Only effective for class A and AB operation No estimated intermod levels: IMR3, IMR5, IP3 No estimated harmonic levels No estimated ACPR (for digital modulations) Page 4 The small signal design technique has its limitations. The output circuit is optimized for maximum saturated RF power, but not necessarily maximum linear power. This means that there is no way to directly calculate the 1 db compressed power output. Also, there is no way to directly calculate the amplifier s two tone intermodulation behavior as described by the parameters IMR3, IMR5, IP3, and IP5. In order to estimate these important parameters, the designer must rely either on measurements or rules of thumb. Two important rules of thumb that apply to MESFET amplifier design are: P-1dB is approximately 1 db less than Psat. IP3 is approximately 10 to 12 db greater than P-1dB. 4

5 Topics Solving for Max Power using Small Signal Techniques Design Flow (step-by-step) Specifications Choosing a device Calculating load line resistance from IV curves Matching Networks Distributed vs Lumped Simulations: Gain, input match, and output match Extracting Package Parasitics Maximize Power: matching to the load line resistance Amplifier stability as measured by the K factor Page 5 This slide presents a table of contents for the rest of the seminar. 5

6 Basic Design Process Flow Device choice: cascaded requirement Matching topology: freq & BW Bias Circuit: Class A & pwr supply requirement s Optimize: S11 and S21 Recalculate S11 and S21 & check K >1 (wideband) Add Stability Elements (if necessary) Optimize: Output Match to R load Extract pkg parasitics from S-parms Construct load line R from I-V curves Result: Max Power Output Page 6 DESIGN PROCESS STEPS: Device choice based on the requirements of the cascaded chain of amplifier stages. Be sure that the entire chain goes smoothly into saturation together. No one stage should start to saturate first. Choose a matching topology based on frequency, bandwidth, cost goals, and experience. Choose a bias circuit based on class of operation and power supply requirements. MESFETS require negative gate voltage, which must be provided with the biasing circuit. For highly linear operation, class A operation is recommended. In class A operation, the DC drain current will be 1/2 of the device s Imax. Optimize the input circuit for gain and input match. Determine RL for the device s static IV curves. Extract the package parasitic elements, they will be part of the overall output matching circuit. Optimize the output circuit for best match to RL (this condition will maximize RF power output). If necessary, add circuit elements to insure wideband unconditional stability. 6

7 Small Signal Design Process Represented Graphically Input match for maximum Gain RF IN Input Match Output Match RF OUT Output match for maximum Power Same output matching circuit R L Package Model Output Match RF OUT Page 7 GRAPHICAL REPRESENTATION OF THE SMALL SIGNAL DESIGN PROCESS: Use the device s small signal S-parameters to simulate and optimize gain and input match. Use the device s IV curves to determine RL which serves as a target for the output matching circuit in order to present RL to the device s internal drain terminals, in order to maximize RF power output. This technique is based on a theorem from basic network theory that states that if a network provides a good match to a complex load, then the network s output impedance is equal to the complex conjugate of the load impedance. In our case, the load impedance is RL, which is pure real, so the impedance presented by the optimized output circuit to the device s drain terminals is the complex conjugate of RL which is also RL, since the imaginary part of the load impedance is zero. 7

8 Calculating MESFET load line (RL) for Max RF power from its IV curves Current Load Line Class A Operation for best linearity Imax Imax/2 Bias Point RL = 2(Vb-Vs) / Imax Pout = Imax (Vb-Vs) / 4 Pdc=Vb Imax / 2 Eff = (Vb-Vs) / 2Vb Vs = 2.0 Volts (Approx) Imax = 1.2 Idss (Approx) Knee voltage Vs Vb Voltage Bias (2Vb-Vs) Voltage Potential Breakdown Region Page 8 The proper output impedance for maximum RF power generation can be determined either from measurements, or from a graphical construction using the device s static IV characteristics. A maximum power output load line may be graphically constructed upon the device s static IV characteristics It is this load line resistance, RL, that must be presented by the output matching circuit to the device s output terminals. For maximum linearity it is very important to choose a load line specifically for class A, which is the most linear class of operation. By maximizing its linearity an amplifier is made best suited for operation with digital modulations such as CDMA or TDMA. 8

9 Calculation of Load line Resistance From Bias Voltage and Power Output RL vs Pout for class A Operation RL in ohms R L = (Vb - Vs) 2 2 * Pout RL= 64 / (2*Pout) Vb-Vs = 8 Vb-Vs = Pout in watts RL= 9/ (2*Pout) Page 9 A plot of RL=SQR(Vb-Vs)/2Pout, which in class A operation calculates RL as a function of power output, with bias conditions (i.e. Vb-Vs) as a parameter. Based on the IV graphical construction, a simple calculation of RL in terms of power output is shown Notice that the bias voltage is a parameter of this calculation. Based on only the output power requirement and the anticipated drain-to-source voltage, RL can be calculated directly Load pull experiments have shown that in addition to a pure real load line resistance, it is also necessary when matching to take into account a small reactive component, represented by a capacitor, Cds, in parallel with RL. The value of Cds has been found from experiments to be approximately.10 pf per mm of total gate width. 9

10 Calculation of Minimum Breakdown Voltage vs RL Vb = +10 V (fixed) Vbr G-D MINIMUM (Vbr) gd FOR VARIABLE RL Vbr(gd) > (2PoRL) + Vb +Vpinch-off RL in OHMS Vbr = ( 8RL ) Vbr = ( 4RL ) Po = 1 WATT Po = 2 WATTS Po = 4 WATTS Vbr = ( 2RL ) Page 10 BREAKDOWN VOLTAGE HAS A KEY ROLE IN DETERMINING A GaAs MESFET DEVICE S BIAS VOLTAGE AND OUTPUT POWER LIMITATIONS BASED ON RELIABILITY CONSIDERATIONS. Device reliability is a very important part of every power amplifier design effort. Avalanche breakdown between device contacts is the primary source of non-thermal device failures. How breakdown voltage relates to bias conditions and RF signal levels is the topic of this discussion. We now consider the conditions and considerations that must apply to gain an understanding of this important topic. Class A GaAs MESFET power amplifiers are designed to present an optimum load line resistance to the device s drain-to-source terminals in order to achieve maximum power output for a given set of bias conditions. This load line resistance can easily be determined graphically from the static IV curve construction. What if a non-optimum load resistance is presented to the device s output terminals? If the load resistance is less than the optimum value, the peak RF output voltage will be reduced, decreasing the risk of breakdown failure. However, if the load resistance is greater than the optimum value, the peak RF voltage is increased, which increases the risk of failure. The above plot relates RL, power output, and breakdown. 10

11 Specification Summary with Simulation Applicability SPEC VALUE Small Signal Simulation Large Signal Simulation Freq Gain Match K Psat Plin IP3 Harmonics ACPR 0.9 to 2 GHz db :1 > to +45 dbm +25 to +40 dbm +45 to +60 dbm 30 to 50 dbc 45 to 60 dbc yes yes yes yes yes no no no no yes yes yes yes yes yes yes yes yes Page 11 SPECIFICATION TYPICAL VALUES S.S. SIMULATIONS L.S. SIMULATIONS DIGITAL MOD SIMULATIONS FREQUENCY.90 TO 2.0 GHz YES YES GAIN db YES YES IN/OUT MATCH :1 YES YES STABILITY, K >1.0 YES YES LOAD LINE MATCH 1-10 OHMS YES YES DC VOLTAGE 5 TO 15 VOLTS YES YES DC CURRENT 1 TO 5 AMPS YES YES Pout, SATUARTED 30 TO 45 dbm YES YES Pout, LINEAR 25 TO 40 dbm YES IMR3 30 TO 50 dbc YES IMR5 40 TO 60 dbc YES IP3 45 TO 60 dbm YES IP5 45 TO 60 dbm YES IP3 - P-1dB 12 TO 18 db YES 2nd, 3rd HARM 30 TO 50 dbc YES ACPR 45 TO 60 dbc YES 11

12 Device Data Sheet: Fujitsu FLL351ME Calculate RL from IV curves Page 12 DEVICE CHOICE: We choose the Fujitsu FLL351ME device because it is capable of providing +35 dbm power output with up to 11 db gain. This device is a candidate for the output stage of many types of cellular and PCS infrastructure amplifiers. Notice that the device s static IV curves are provided on this page of the data sheet. 12

13 Device Data Sheet: S-parameters Values at 1.8 GHz Page 13 This page of the FLL351ME s data sheet provides the device s small signal S- parameters which must be read into the simulator in order to calculate gain, match, and stability factor K. 13

14 Device Data Sheet: S-parameters Enter S-parameters into simulator (S2P file) to calculate gain and match: Page 14 This page of the FLL351ME s data sheet provides the device s small signal S- parameters which must be read into the simulator in order to calculate gain, match, and stability factor K. 14

15 Data Sheet - Matching Topology Recommended evaluation circuit for achieving Gain and RF power Page 15 Fujitsu recommends an evaluation circuit for the FLL351ME, which is pictured above. This circuit is a distributed topology, and is printed on a printed circuit board with a dielectric constant of 9.7 and a thickness of.65 mm. This circuit serves the purpose of providing device users with a matching circuit that is capable of demonstrating the gain and power output capabilities of the device at one frequency (2.3 GHz). We will use this circuit as the starting point in applying the small signal design process. 15

16 FLL351ME Load Line Calculation: RL in Class A Operation Derived from the IV Curves: FLL351ME Vbias = 10 volts Vs = 1.8 volts Idss = 1.2 A RL = 2 (10-1.8) (1.2 * 1.2) = 11.4 Ohms Page 16 The above calculation is based on applying the equation for RL to the measured IV parameters of the Fujitsu FLL351ME device which are shown on the data sheet. 16

17 Device Output Circuit: Model Includes Package Elements Internal drain terminals L S R S R L CDS L S R S To Output Matching Network Package Model Page 17 MODEL FOR THE MESFET S OUTPUT CIRCUIT: In optimizing the output circuit to provide exactly RL at the MESFET s internal drain terminals, it is very important to include all other device output circuit elements as a part of the output matching network. The device s Cds and all drain and source package parasitic elements must be included as a part of the total output matching circuit. The package parasitic elements are obtained by extracting them from the device s small signal S parameters. If the device is not packaged, but is in bare chip form (either hybrid or MMIC construction), the package elements can be ignored, simplifying the output matching circuits. Of course any bond wires must still be included as circuit elements. 17

18 Lumped Element Matching Topology Most useful at Low Frequencies V GS V DS RF In FET RF Out Input Matching Output Matching Page 18 LUMPED MATCHING CIRCUIT TOPOLOGY: Matching circuits perform two functions: Matching circuits transform the 50 Ohm source and load impedances to the proper impedance to match the gate and drain of the MESFET for high gain and maximum RF power output. Matching circuits contain reactive elements, and therefore are frequency selective. Matching circuits also determine an amplifier s center frequency and bandwidth. The lumped element matching circuit shown above is most useful at low frequencies where the small size of lumped capacitors and wound inductors have an important over the larger wavelength dependent distributed circuits. This particular lumped matching circuit has a low pass topology. High pass topologies can also be used, as can hybrids between the two. If necessary to achieve a good match over the required bandwidth, additional sections may be added. In general it is advisable to minimize the number of sections, to reduce both circuit complexity and parts cost. Bias is provided by a choke inductor and a bypass capacitor place in both the gate and drain circuits. Input and output are DC blocked with series capacitors. 18

19 Distributed Element Matching Topology Most useful at High Frequencies V gs V ds RF In λ/4 λ/4 FET RF Out Page 19 DISTRIBUTED ELEMENT MATCHING: The above matching circuit is topologically identical to the previously discussed lumped matching circuit. In the distributed circuit, inductors have been replaced with long, narrow microstrip lines. Shunt capacitors have been replaced by short, wide microstrip lines. Bias chokes are replaced with 1/4 wavelength microstrip lines. Distributed matching circuits are most useful at higher frequencies because their element lengths are scaled with frequency, which means that similar circuits become progressively smaller at higher frequencies. Low frequency distributed circuits may be too large to be practical. 19

20 Evaluation Circuit: Fujitsu FLL351ME Fujitsu s Distributed Topology (ADS layout): DC block cap DC block cap mesfet RF in RF out choke choke Page 20 This circuit is shown on page 358 of Fujitsu s 1997 Microwave Semiconductor Databook. The PCB is 26 mils thick, with a relative dielectric constant of 9.7. Blocking capacitors at the input and the output have been added. Choke inductors for gate and drain biasing have also been added. We will next simulated the performance of this circuit. 20

21 Simulation Setup: FLL351ME First pass using Fujitsu s data sheet evaluation circuit: NOTE: S2P file from data sheet IN OUT G bias TRLs D bias Page 21 The complete single ended FLL351ME amplifier can be simulated by ADS. The results will be a calculation of small signal gain, input and output match, isolation, and the stability factor K. The ADS optimizer can be used to optimize circuit elements to improve performance if this is necessary. 21

22 Measurement Equations Inserted on the schematic for use with optimization (if desired). Required for optimizer GOAL. Stability factor equation is built into the ADS system K=(1-sqS11-sqS22+sqD)/2S12S21 where: D=(S11S22-S12S21) Page 22 The complete single ended amplifier can be simulated by ADS. The results will be the calculation of small signal gain, input and output match, isolation, and the stability factor K. The ADS optimizer can be used to optimize circuit elements to improve performance if this is necessary. 22

23 Initial Simulation Results Gain (m1), Input match (m2), Output match (m2) db NOTE: Reverse Isolation (S12) also shown in blue. Freq in GHz Next consider match for power Page 23 Small signal gain, input match, and output match performance looks quite good. Gain is over 10.0 db, and the input and output match, while not too bad at 1.8 GHz are actually peaked in performance at a slightly higher in frequency where the Fujitsu design example is centered. It is expected that output match will be poor when it is adjusted to match RL, for maximum power generation. It is clearly seen from the plot that at frequencies higher than 1.8 GHz, where the design is centered, the output match is degrading while the input match is improving. This is a result of optimizing the output match for maximum power. 23

24 Device Output Matching Options for obtaining Package Parasitics: Obtain from the device s manufacturer Measure the package parasitics EM package modeling Extract from device S-parameters Page 24 As preparation for optimizing the output circuit for maximum RF power generation, it is necessary to determine the device s package parasitic elements. These elements must be determined because they are a part of the total output matching network. If the package cannot be obtained from the device supplier, they must be either measured ( a very difficult procedure), or calculated (requiring a full EM simulation), or extracted from the device s small signal S parameters. By far the most straight forward technique is extraction, whose procedure will be described in the next few slides. 24

25 Equivalent Circuit: Packaged MESFET Extracting the Package Parasitics Package parasitic elements Intrinsic device model elements Page 25 The equivalent circuit of a packaged MESFET device is composed of a set of intrinsic device elements plus a set of package parasitic elements. The equivalent circuit shown in this slide shown the boundary between the two types of circuit elements. 25

26 Setup: Extracting Package Parasitics (1 of 2) Measured S-params port1 port2 Optimization Results: port3 port4 Intrinsic device model Page 26 EXTRACTING PACKAGE PARASITIC ELEMENTS FROM THE MEASURED SMALL SIGNAL S-PARAMETERS. An important consideration in designing power amplifiers using packaged GaAs MESFET devices is to accurately determine the package parasitic elements, which affect all simulations, because these elements are a part of both the complete input and output matching circuits. This is a critical consideration in the output matching circuit because this circuit matches to the device s load resistance, RL and not the measured S-parameters, which contain the package parasitic elements. The load line resistance, RL, which is the impedance which the output matching network must present to the device, is transformed by these parasitic elements. Therefore, the package elements become an important part of the overall output matching circuit. All successful design efforts must include the effects of these package elements. The ADS circuit schematic is based on the ADS example amodeib_pri under mw_ckts. 26

27 Setup: Extracting Package Parasitics (2 of 2) Meas Eqn deltas used in Goal Expressions Page 27 EXTRACTING PACKAGE PARASITIC ELEMENTS FROM THE MEASURED SMALL SIGNAL S-PARAMETERS. An important consideration in designing power amplifiers using packaged GaAs MESFET devices is to accurately determine the package parasitic elements, which affect all simulations, because these elements are a part of both the complete input and output matching circuits. This is a critical consideration in the output matching circuit because this circuit matches to the device s load resistance, RL and not the measured S-parameters, which contain the package parasitic elements. The load line resistance, RL, which is the impedance which the output matching network must present to the device, is transformed by these parasitic elements. Therefore, the package elements become an important part of the overall output matching circuit. All successful design efforts must include the effects of these package elements. The ADS circuit schematic is based on the ADS example amodeib_pri under mw_ckts. 27

28 Measured vs Modeled Results Measured S parameters (red) Optimized equivalent circuit (blue) Optimized Equivalent Circuit Measured Spar Page 28 The package parasitic elements are modeled simply as a series RL circuit in series with the gate, the drain, and the source ports. This equivalent circuit can be analyzed by using Agilent/EESOF ADS to simulate the model s schematic diagram. By using the ADS optimizer, simulated S-parameters of the model can be adjusted to come arbitrarily close to the measured small signal S-parameters of a given device. All circuit elements designated as variables of the optimization process will be iteratively varied in order to home in on close agreement between the equivalent circuit and the measured S- parameters. To facilitate a fast and accurate optimization, it is very important to begin the process with as many of the device s equivalent circuit elements set close to their realistic values. The non-package elements of the device s equivalent circuit may be calculated by applying the device s total gate width, W, in mm, to the a set of approximate, scaleable, small signal GaAs MESFET model elements based on class A operation at IDSS/2, and Vds of 8.0 Volts. This set of device parameters is: Cgs = 1.0 pf/mm Rin = 4.1 Ohms - mm Cds =.20 pf/mm Cgd =.04 pf/mm Rds = 184 Ohms - mm Gm =.082 S/mm 28

29 Simulation Setup: Output Match to RL for Max RF Power Simulation to determine the Output circuit s Match to RL using Fujitsu s evaluation circuit: Drain Parasitics MLIN MLIN S11 Source Parasitics FET Output: R L = 11.4 ohms Cds = 1 pf S-param port Z = 50 ohms (num=1) Page 29 SIMULATING THE AMPLIFIER S POWER PERFORMANCE BASED ON A MEASURED SMALL SIGNAL S-PARAMETER DEVICE MODEL AND THE DEVICE S IV CURVE. If a designer has only measured small signal S-parameters as a device model (along with a measure static IV characteristic) available as a starting point for a power amplifier design project, it is imperative that he/she initially optimize and fix the element values of the output matching circuit at the values necessary to achieve the best possible match to RL (the load line resistance for maximum power generation). The element values in the input matching circuit can then be optimized to improve gain or input match without affecting power output. Prior to optimization, the output circuit must be modeled as completely as possible, and then optimized for the best match to R L at the operating frequency. Extracted drain and source package parasitic elements must be included in this model these elements determine much or all of the series matching inductance. Also, it is very important to include all component parasitic elements in the ADS schematic. Parasitic elements associated with vias, smt capacitors, smt resistors, and inductors are examples. Be sure to contact the component s manufacturer to determine the exact value of each parasitic. Remember that a simulation is only as accurate as the completeness of its model 29

30 Output Match to RL S11 of: -8 db is not good enough... Page 30 The output match is resonant at the correct frequency, however the value of the match is marginal. This indicates a match which is not properly adjusted to RL which is calculated to be 11 Ohms for the FLL351ME device. 30

31 Schematic for Simulating Z Presented to the Device s Internal Drain Terminals S11 Drain Parasitics MLINs from data sheet Bias Network not included in simulation. No effect on RF Page 31 To determine how far away the matching circuit is from providing the target RL of 11.4 Ohms to the device s drain terminal, the circuit simulation schematic diagram is modified to measure the impedance presented by the total output matching network (terminated in a 50 Ohm load) to the device s drain terminals. Bias circuit effects are ignored as minor in this simulation. 31

32 Load Z Presented to the Drain For Max Power: Drain must see RL=11.4 Ohms (calc from IV curves) At 1.8 GHz, RL is about 19 Ohms vs Ohms calculated from the IV curves on the data sheet. Need to Optimize! Page 32 By simulating the matching impedance presented to the device s drain terminals, we confirm that the real part of the impedance is nearly 20 Ohms, rather than the required 11 Ohms. This means the device is not properly matched for maximum power output. 32

33 Optimize to Improve Match to R L Optimize for Max Power Drain Parasitics MLIN MLIN S11 Source Parasitics FET Output: R L = 11.4 ohms Cds = 1 pf Page 33 OPTIMIZING THE AMPLIFIER S PERFORMANCE BASED ON A MEASURED SMALL SIGNAL S-PARAMETER DEVICE MODEL AND THE DEVICE S IV CURVE. If a designer has only measured small signal S-parameters as a device model (along with a measure static IV characteristic) available as a starting point for a power amplifier design project, it is imperative that he/she initially optimize and fix the element values of the output matching circuit at the values necessary to achieve the best possible match to RL (the load line resistance for maximum power generation). The element values in the input matching circuit can then be optimized to improve gain or input match without affecting power output. Prior to optimization, the output circuit must be modeled as completely as possible, and then optimized for the best match to R L at the operating frequency. Extracted drain and source package parasitic elements must be included in this model these elements determine much or all of the series matching inductance. Also, it is very important to include all component parasitic elements in the ADS schematic. Parasitic elements associated with vias, smt capacitors, smt resistors, and inductors are examples. Be sure to contact the component s manufacturer to determine the exact value of each parasitic. Remember that a simulation is only as accurate as the completeness of its model 33

34 Results: Improved Match to R L After S11 Optimization: -15 db return loss Page 34 By using the ADS optimizer to adjust the output circuit element values for best match to RL=11.4 Ohms, the output match is significantly improved. The return is now approaching -15 db, indicating a good match to RL. 34

35 Load Z after Optimizing R L Match R L close to calculated value: At 1.8 GHz R L = Ohms (real part) Next step: stability... Page 35 By again simulating the impedance presented by the optimized output circuit to the device s drain terminals, we confirm that the real part of the impedance is now very close to 11 Ohms. This means that the device s output is now properly matched for maximum RF power generation. 35

36 Amplifier Stability Factor (K) Simulated Results for the Single Ended FLL351ME Amp Area of low Frequency conditional stability (0<K<1.0) indicates need for adding a stabilization network. Use measurement equation from ADS S-parameter palette Page 36 Next, the ADS simulation is used to evaluate the stability of the amplifier over a wide band of frequencies. We find that the stability of the amplifier is unconditional at the operating frequency, but is reduced to conditionally stable at low frequencies. This is a common result because large power MESFET s have very high transconductance, leading to potentially high gain at low frequencies. This high low frequency gain can cause stability problems, which must be corrected by adding a stabilizing network. 36

37 Add a Shorted Stub/50 Ohm Resistor Stabilization Network to Amplifier Input 1/4 wavelength shorted stub = open circuit at 1.8 GHz and short circuit at low frequencies. Reduced low frequency gain improves stability. Page 37 For unconditional stability, the amplifier s stability factor, K, must be greater than 1.0 for all frequencies. To aid stability a simple network consisting of a 50 Ohm resistor in series with a 1/4 wavelength shorted stub is placed in shunt with the single ended amplifier's input. This network greatly enhances a power amplifier s stability at low frequencies, where stability problems often occur due to the high value of a power MESFET s transconductance. 37

38 K results with the Stabilization Network Plotted Stability Factor K NOTE: When necessary, optimize the stabilization network for K > 1.0 (unconditional stability) over a wide bandwidth by adjusting the shorted stub and the termination resistor. Page 38 By including the 50 Ohm resistor/shorted 1/4 wavelength stub stability network, the low frequency stability of the amplifier is significantly improved. Next we will check the gain and match of the amplifier with the both the optimized output circuit and the stability network in place. 38

39 Final Simulation with the Output Circuit Optimized for Max Power Gain (m1), Input match (m2), Output match (m2) Page 39 This slide shows the final simulation of gain, input match, and output match with the optimized output circuit and the stability network in place. Notice that gain has decreased slightly (about.7 db), and output match is not as good as in the first simulation. Both results are to be expected because optimizing the output circuit for best power match, will mismatch the output relative to the devices small signal S parameters (S22), causing both the gain and the output match to degrade slightly. However, overall, the gain and match performance remains very good, with the new assurance that RF power generation is maximized and overall stability is excellent. 39

40 End of Design Seminar... Page 40 40

41 References Bahl, Inder, Microwave Solid State Circuit Design (Wiley 1988) Vendelin, George, A. Pavio and E. Rohde, Microwave Circuit Design (Wiley 1990) Razavi, R.F. Microelectronics (Prentice Hall 1998) Pozar, Microwave Engineering, 2nd. Ed. (Wiley 1998) Cripps, Stephen, RF Power Amplifiers for Wireless Communication (Artech House 1999) Abrie, Pietr, RF and Microwave Amplifier Design (Artech House 1999) Sweet, Allen A., MIC and MMIC Amplifier and Oscillator Circuit Design (Artech House 1990) Page 41 References Bahl, Inder, Microwave Solid State Circuit Design (Wiley 1988) Vendelin, George, A. Pavio and E. Rohde, Microwave Circuit Design (Wiley 1990) Razavi, R.F. Microelectronics (Prentice Hall 1998) Pozar, Microwave Engineering, 2nd. Ed. (Wiley 1998) Cripps, Stephen, RF Power Amplifiers for Wireless Communication (Artech House 1999) Abrie, Pietr, RF and Microwave Amplifier Design (Artech House 1999) Sweet, Allen A., MIC and MMIC Amplifier and Oscillator Circuit Design (Artech House 1990) 41

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