Design of a 1.6-mW LC-tuned VCO for 2.4GHz in 0.18-um RF CMOS technology

Transcription

1 Stein Erik Weberg RFIC Design Engineer and Bertel-Eivind Flaten R&D Director March, 2002 Turning RF IC technology into successful design Design of a 1.6-mW LC-tuned VCO for 2.4GHz in 0.18-um RF CMOS technology 1

2 Agenda Introduction Software and design flow Oscillator specification for TX/RX Field simulation of inductors Frequency modulation Design/Layout Measurement results Summary Page 2 In this talk we present the specification, design, layout and measurements of a 2.5-GHz low-power LC-tuned oscillator designed in a 0.18um CMOS technology. The design is intended for use in a single-chip Bluetooth-compatible RF Transmitter. But first of all, a few words about Nordic VLSI as a company. 2

3 NORDIC VLSI IS: A Fabless Semiconductor Company Producer of standard off-the-shelf RF components Intellectual Property (IP) supplier with advanced A/D, D/A and RF modules Turn-key developer and supplier of custom components Worldwide company with representatives on all continents A leading Norwegian Technology Company listed on the Norwegian Stock Exchange Page 3 - wafer production, assembly and testing is outsourced - Austria Microsystems, TSMC,... - ASE - Standard RF components -ISM bands, eg. 433 MHz, 868 MHz, 915 MHz, 2,4 GHz -Integration -Easy to use - RF IP for 2,4 GHz transceiver and transmitter - Turnover 2002: 18 M Euro - Number of employees: 100 3

4 HISTORY AND KEY MILESTONES Expretise 2 nd gen. SOC plat. WorldWide Standard component IP modules Oslo IPO ISO 9001 Component supplier ASIC design Founded Started delivery of custom components ISO 9001 certified Listed on the Norwegian stock exchange Established office in Oslo First RF components introduced Data converters IPs introduced Worldwide distribution established SoC platform with analog IPs introduced Page 4 - founded by research scientists from SINTEF and the NTnu - ASIC design house from 83 to tekst står på sliden stort sett Transmitter and transceiver for 2.4 GHz The VCO presented here is part of these components 4

5 WE HAVE A PORTFOLIO OF RF COMPONENTS... RF Roadmap: 2.4GHz 433/868/915MHz nrf2402 TX multich nrf2401 TX/RX, multich nrf903 TX/RX, multich IP Module IP Module 868/915MHz 433MHz nrf401 TX/RX, 2CH nrf902 nrf MHz TX, 915MHz TX nrf403 TX/RX 315/433MHz nrf0433 5V TX/RX nrf402 TX, 2CH GHz Transceiver available as IP for SoC designs 2002 Page 5 yellow -> components in volume production - blue -> components introduced to the market this year - red -> RF IP is a new product from Nordic VLSI this year Typical applications for Nordic VLSI RF standard products: AMR, Automatic Meter Reading Keyless Entry Alarm and Security Systems (f.eks. 2-way car alarm) Home Automation Remote Control Wireless Keyboard & joystick Disse jobber vi for å komme inn i: Wireless Handsfree for mobile phone Wireless microphone and headsets Automotive tyre pressure sensors PDA and RS232 Toys 5

6 Nordic VLSI analog design flow Analog tools RF tools Mentor Graphics' Design Architect Agilent ADS RFIC Designer Agilent ADS Momentum Mentor Graphics' IC Station Anacad Eldo Avant! Star-RCXT Netlist interface Data interface Verification tool Page 6 As any design house, Nordic is equipped with a plurality of advanced design tools, both for analog and digital design. On this slide we focus on how the analog tools are used together. We see that for most analog designs, we use Mentor Graphic s tools for schematic entry, layout and simulation, while Star-RCXT is used for 3-D extraction. All this is quite adequate for analog design, But we also need different simulators for verifying the parameters important for RF design, where we have chosen Agilent s HB simulator as the heart of our system. The schematics drawn in Mentor are converted to netlists that are simulated in ADS using a parallel set of device models. In addition, we use the Momentum simulator to verify the design of passive components. We will come back to how we use Momentum later on, but let s now focus on the real subject of today, namely 6

7 Design goals for transmitter/receiver VCO Low power Acceptable phase noise Monolithic realization: Reduced sensitivity to outside radiation Low-cost/simple assembly Less process variation as bond wires are omitted Realize low-cost FM modulator Page 7 On most of our RF chips we have had two major goals, namely low power and few external pins/components, where few components means that the chip is easy-to-use for the cutomer (who should not need to know much about RF design). This is reflected in all system modules, so we try to make the VCO use as little power as possible, and use no external pins. Even more power is saved if we can avoid using upconversion mixers in the modulator. This can be achieved by using the topology on the next slide. 7

8 Modulator principle V mod Fref PFD/ CP V LF PA Loop filter VCO 1/N Open-loop PLL frequency modulation by applying the data signal at V mod Simple and low-cost modulator realization No spurious components at N*Fref Challenges: VCO phase noise is not filtered by PLL Possible frequency drift during transmission due to leakage currents and PA pulling Page 8 Here, we use an open-loop PLL frequency modulator, where the PLL is allowed to settle to the correct frequency before this switch is opened and the modulation can be applied at a separate modulation input pin of the VCO. During modulation, the capacitance in the loop filter is used to keep the carrier frequency inside the channel. The most emphasized specification parameter for a VCO is usually phase noise. It is a known fact that CMOS oscillators exhibit substantially higher flicker noise upconversion than their bipolar counterparts. Also since, in this case, the VCO close-in phase noise is not cancelled by the PLL, it is a natural consequence to look at the transmitted signal quality vs. phase noise in the VCO. 8

9 Phase noise specification TX 10 log ( L( f) ) High phase noise means degradation of transmitted signal SNR Usually, transmitter VCOs can be quite noisy without degrading system performance Simple (pessimistic) estimate of SNR: f SSB phase noise f flk Typical phase noise spectrum SNR 2 f f 2 1 ( f ) f 2 m 2 L( f 2 m ) df m Page 9 Here we show a typical phase noise spectrum of a free-running CMOS VCO <left>. Note the knee of flicker noise up-conversion where the flicker noise starts to dominate the noise behavior. The power spectral density of frequency noise can be obtained by multiplying this spectrum by f 2. The total frequency noise of the signal can be obtained by integrating over the signal bandwidth <see equation>. Using a simple estimate for the signal power in the frequency domain < where delta-f denotes peak deviation in the FSK modulation>, we write the equation for the signal s SNR. Rearranging this equation, it may be interesting to plot the transmitted signal-to-noise ratio vs. flicker noise knee like in the figure < >. 9

10 Phase noise specification TX (2) SNR=26dB SNR=28dB 10 log ( L ( f )) SNR=30dB f SSB phase noise L(1.0MHz) SNR=32dB SNR=34dB f flk -120 SNR=36dB SNR 2 f2 f1 ( f ) f 2 m 2 L( f 2 m ) df m -122 SNR=38dB SNR=40dB f flk SNR level curves in the f flk - L(1MHz) plane Page 10 This shows that in this case, flicker noise degrades SNR substantially when the flicker noise knee exceeds kHz (which is typical for CMOS designs). We also see that the SNR of the transmitted wave may become less than 30dB even if the VCO satisfies blocking specification. This means that in this case, there is little margin for relaxing the VCO specification for the transmitter compared to a receiver design. We will see next how the blocking specification of the system specifies the needed phase noise if this VCO is to be used in a receiver. 10

11 Phase noise specification RX Received power [dbm] Reference sensitivity Blocking signals... Based on Bluetooth [3] Specification: Blocking specification at 3 MHz offset is the most difficult: Oscillator phase noise offset: 124dBc/Hz Wanted signal Image f [MHz] Page 11 When it comes to RX specification, the over-all system blocking specification applies. The interfering signals are sketched in this figure, resulting in a quite tough phase noise specification for the 3rd adjacent channel. (GSM is tougher) The 124dBc/Hz at 3MHz assumes a needed receiver SNR of 13dB and a blocking margin of about 10dB. This figure corresponds to 115dBc/Hz at 1MHz offset. We all know that one of the main keys to a low-noise LC-VCO design is the design of a good inductor. It is a natural consequence to look at the process technology to see what performance to expect. 11

12 Technology overview M6 M5 M4 M3 M2 M1 Si Substrate Glue Ground Wafer cross-section, substrate not to scale 2.0 um 280 um Thick top metal Low series resistance Smaller parasitic capacitance MiM capacitors, high-q 0.18-µm minimum gate length RF transistors: f T 30GHz True triple-well for good substrate isolation How can this be exploited? Page 12 The technology at hand is a 0.18um gate length, so-called RF CMOS process, which means that the foundry provides ready-touse, qualified models for RF passive and active devices. Unfortunately, the RF passives available are not always optimum when it comes to shape, area or electrical specification, so most RFIC design groups do some sort of modification on the original devices provided by the foundry. As we will see next, we have chosen to develop our own inductor library using Agilent s Momentum simulator for use in VCOs and RF gain stages. 12

13 Inductor simulation using Momentum Physical structure Momentum model RF-mode solver is adequate for most RFIC design, but is limited to planar structures. Thick conductors with small separation are not accurately modeled Use special tricks to simulate thick metal Provides good models for high frequency (harmonics), generally not true for foundry-supplied models Use extracted 2-port S-parameter data directly for HB simulations Page 13 As the process provides a thick top metallization of height ~2um and a minimum separation of 1.5um, the lateral capacitance between adjacent tracks is substantial and must be modeled correctly. As Momentum is a planar field solver and does not automatically take into account the thickness of a conductor, this is accomplished by substituting the thick metal with two overlaying conducting sheets that are connected through a large via. This makes sure that the capacitive coupling between the adjacent tracks is modeled more correctly. The extracted 2-port S-parameter results can be used directly for frequency-domain simulations in ADS, using a touchstoneformatted data file. 13

14 Inductor design for oscillator Relatively small L, high Q A high-q (low loss), differential inductor design is the key to a good, low-power and low-noise oscillator Guidelines: Use thick top metal only, parallel M1- M5 decreases series losses, but increase capacitive and inductive coupling to substrate Use thinnest substrate available Use relatively large center hole for max Q Use exact terminals to achieve accurate results Use wide metal, but not too wide (Resistive/series losses vs. inductive and capacitive substrate coupling) Page 14 We will now show how two different inductor applications lead to very different designs. This simulation was carried out on the inductor above, being very similar to one of the foundry-supplied designs, with some modifications of terminal placement. This inductor turned out to be near-optimum for the oscillator design, as will be seen later. <list guidelines> 14

15 Inductor design for voltage buffer Signal port Grounded port Compact inductors are needed for low-power, high-swing buffer design (efficient gain at RF) Smaller Q, high L (8-10nH, direct trade-off between inductor Q L and current consumption) Often, single-ended inductors are used even if buffer is differential Benefits of multi-layer inductors: Smaller area Higher Q due to smaller E-field at bottom windings (~grounded) and shielding effects of bottom strip Reduced SRF may not be a problem for 2.4GHz designs Page 15 For buffering applications, the requirements are quite different. Often, a high inductance is needed to tune out the load capacitance of the next stage, while Q-factor does not need to be that high. (in fact, if the Q factor can be traded for a larger inductance, this is beneficial as the bandwidth of the buffer increases without increasing power consumption. Anyway, the maximum inductance will be limited by the frequency and the load capacitance) often, buffer inductors are single-ended, i.e. one of the terminals is grounded. This means that parasitic capacitance on this terminal can be neglected. The figure shows one inductor that exploits this by adding a large sheet of metal1 at the bottom that is virtually grounded, due to its relatively small inductance to ground. The top windings are thus shielded from capacitive coupling to the substrate, and the Q-factor will increase to some extent. 15

16 Calculation of inductor key parameters Port 1 Port 2 Y3 Port 1 Port 2 Y1 Y2 Pi-type equivalent circuit for parameter extraction Assume pi-equivalent circuit describes the inductor adequately (low/medium frequencies) Use S-parameter-to-pi-network transformation formula to obtain Y1, Y2 and Y3 Assume that using the lowfrequency value of Y3 gives a good estimate for L: L 1 1 Im{ } ω Y 3 Assuming port 2 grounded, the Q- factor can be estimated as: Im{1/ Y3 ( ωmin )} ωmin Q Re{ Y } + Re{ Y } ω 1 3 Page 16 When trying to evaluate the results of an inductor two-port s- parameter simulation, it is important to have good approximations for the key parameters, such as inductance and Q, so we can get a feeling of the actual performance.. Here, we use a simple pi-network that is widely acknowledged in the industry as a good model for inductor behavior. Then, these two formulas for estimating the inductance and Q factor are deduced from the pi equivalent. The Q factor is computed as the ratio between inductive resistive impedance seen by port 1 when port 2 is grounded. This does not reflect the actual use of the inductor, so the results are somewhat inaccurate. 16

17 Momentum inductor simulation results Q peaks around 3GHz, due to transition between seriesand substrate losses domination L is fairly constant up to 5-6GHz, then it peaks due to the self-resonance of Y3 BUT: Both Q and L are inaccurate descriptions of actual inductor performance, especially at high frequencies use S-parameter data directly Page 17 Here we see the plots of Q and L from the previous page for the VCO inductor. We see that. In the end, this inductor is near-optimum for our oscillator, so we move on to the rest of the resonance tank 17

18 Modulation stability vop V LF V mod von Varactors realized as MOS capacitors with hot gate System spec (BT): ±11% variation in peak deviation allowed Frequency is set by f 0 = 2π 1 LC tot cap_en Resonance tank Deviation can be shown to be f = f 0 1 2π f0 C 2 1+ CmodL( 2π f0 ) mod L Page 18 We designed the frequency modulator as not summing voltages at the loop filter node, but rather summing capacitances inside the resonance tank. <figure> This is done by independently controlling the two voltages that control center frequency and modulation. This has the advantage of the deviation being relatively stable. We re able to show that using a very small varactor that is controlled by the modulation voltage, the frequency deviation is only dependent on L, the modulating capacitance and the frequency <equation>. As the inductance of on-chip inductors is fairly stable, and the channel number is known, the only truly varying parameter is the modulation capacitance itself. Using an MOS-type varactor where gate capacitance is well-controlled, we claim that the modulation index specification can be met. 18

19 Schematic v opb vop vss vdd von v onb Differential design to suppress substrate noise Inductively loaded cascode output buffer to provide good isolation and linearity at high output amplitudes Simple, low-noise current source to minimize noise up-conversion Use both P- and N-type MOSFETs are used to achieve high signal swing and good rise/fall time symmetry, BUT this makes the oscillator more sensitive to supply drift etc. Page 19 We will not delve into the details of designing the rest of the VCO, but it is clear that both correct sizing of the bias current, active transistors and the inductor is extremely important. Equally important is the minimization of series parasitic resistance in the tank, so the layout has to be dense and well balanced. This is exactly what we see in the (center of the) layout where most of the tank capacitance is placed as close as possible to the inductor. 19

20 Layout Highly symmetrical layout Keep resonance loop as tight as possible to reduce losses Local decoupling to minimize noise sensitivity 330 um Page 20 This layout shows the oscillator itself in the middle (note the resonating capacitances close to the inductor), while the output buffer can be seen on the bottom and sides. The buffer inductors shown are from the original foundry-supplied inductor library. Their area has for later designs been reduced to less than half the size using the multi-layer configuration described earlier. 20

21 Noise and tuning characteristic Date: Time: 18:19 TRACE A: -30 db* Ch1 PM PSD Hz A Marker db* Y* = radrms^2/hz LogMag db /div Frequency [GHz] Simulated Measured db* Ch1 Carrier: GHz 1k 10k 100k 1M Start: Hz Stop: 1.1 MHz Control voltage [V] Double-sideband demodulated phase noise Frequency vs. tuning voltage characteristic Page 21 The Measurements showed that the oscillator proved to work well at bias currents as low as mA (room temperature), but at this low bias current the phase noise was several db above the desired spec. The bias conditions that gave the maximum PFN figure-of-merit (next slide) turned out to be 1.3V power supply and 1.2mA current, that is 1.6mW power consumption. At these bias conditions, the measured SSB phase noise at 1MHz offset frequency was 117dBc/Hz. The tuning characteristic showed over 300MHz tuning range with a maximum VCO gain of 440MHz/V. This is not by itself enough to cover all desired channels and process variation, but the switched tank capacitors shown on a previous slide help solve this problem. 21

22 Noise performance comparison by figure of merit Ref P sup [mw] f 0 [GHz] f m [MHz] L{f m } PFN Tiebout [5] This Work Hajimiri [1] De Ranter [6] Wang [7] Hegazi [8] Ham [4] De Muer [9] kt f PFN = 10log P sup f 0 m 2 L( f m ) Page 22 When trying to compare the quality of different oscillators, most people use some sort of figure of merit The one we have used was adopted by Ham and Hajimiri, and it normalizes the measured phase noise with repect to center frequency and power consumption. We see by this table that this design proved to be state-of the art, only beaten by a two-stage ring-type LC configuration. These good reults is of course thanks to a high-quality prcess and good simulation software. Some people may at this point be curious about the dynamic performance of the VCO while modulating. 22

23 Modulation Characteristics TRACE A: Ch1 2FSK Meas Time TRACE A: Ch1 Spectrum 250 khz 0 dbm I-Eye LogMag 50 khz /div 10 db /div -250 khz Start: -1 sym Stop: 1 sym -100 dbm Center: GHz Span: 4 MHz Eye diagram using 1Mbit/s modulation with 150kHz deviation Transmitted spectrum (max hold) Page 23 When the Gaussian-filtered data signal was applied to the data input, the output signals showed good modulation performance, that is, low noise and no noticeable spectral regrowth. This is due to the very linear behavior of the MOS varactor, esp. because the modulating signal does not saturate the varactor. 23

24 Summary 0.18um RF CMOS process allows Q L for 2.0nH inductor Low phase noise also needed for good quality of the transmitted signal Good technology facilitates low power: 1.6mW SSB Phase noise: 1.0MHz MHz FM/GFSK modulation possible Simple modulator, avoids up-conversion mixers Good agreement between measurements and simulations Page 24 To summarize, we have designed a 2.5-GHz CMOS oscillator using a 0.18-um RF-CMOS process. We have shown that flicker noise degrades signal quality by several db, and that this leads to an oscillator specification which is not far from the one seen in receivers. The power consumption is very low, around 1.6mW with yet acceptable phase noise, also for receiver design. The oscillator is also prepared for GFSK modulation and can thus realize a cheap, but also stable modulator without using upconversion mixers. This concludes my presentation. 24

25 References [1] A. Hajimiri and T. H. Lee, Design Issues in CMOS Differential LC Oscillators, IEEE Journal of Solid-State Circuits, vol. 34, pp , May [2] A. Hajimiri and T. H. Lee, The Design of Low Noise Oscillators. Kluwer Academic Publishers, [3] Specification of the Bluetooth System, 1.1 ed., Feb [4] D. Ham and A. Hajimiri, Concepts and Methods in the Optimization of integrated LC VCOs, IEEE Journal of Solid-State Circuits, vol. 36, pp , June [5] M. Tiebout, Low-Power Low-Phase-Noise Differentially Tuned Quadrature VCO Design in Standard CMOS, IEEE Journal of Solid-State Circuits, vol. 36, pp , July [6] C. De Ranter and M. Steyaert, A 0.25µm CMOS 17GHzVCO, inisscc Digest of Technical Papers, pp , Feb [7] H. Wang, A 50GHz VCO in 0.25µm CMOS," in ISSCC Digest of Technical Papers, pp , Feb [8] E. Hegazi, H. Sjöland, and A. Abidi, A filtering Technique to Lower Oscillator Phase Noise, in ISSCC Digest of Technical Papers, pp , Feb [9] B. De Muer, M. Borremans, M. Steyaert, and G.L. Puma, A2-GHz Low-Phase- Noise Integrated LC-VCO Set with Flicker-Noise Upconversion Minimization, IEEE Journal of Solid-State Circuits, vol. 35, pp , July Page 25 25

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