Meeting the challenge for offline SMPS through improved semiconductor current density

Transcription

1 Meeting the challenge for offline SMPS through improved semiconductor current density Jon Mark Hancock Infineon Technologies NA, Inc North First Street San Jose, CA

2 Agenda The semiconductor challenge for offline SMPS Structure and development of HV DMOS transistors Characteristics of super-junction transistors Improving HV diodes- merged PN/Schottky SiC Application example- Interleaved Two Transistor Forward Application example- Bridgeless PFC converter Questions & Answers Page 2

3 Requirements for MOSFET s and Diodes show continuous evolution in expectations Is Is the the good enough? (considering (considering FOM FOM based based on on Ron Ron X Ciss Cissor or Coss) Coss) Page 3 What s most important? (switching (switching loss loss improvement, improvement, or or surge surge current current at at low low line?) line?)

4 High voltage power switches What should the ideal power switch look like? Near zero power losses low static power losses Low on state resistance Attractive thermal coefficients Low thermal impedance low dynamic power losses fast switching speed ease of drive Low energy stored in output capacitance (small area) Freedom from charge recombination losses Lowest possible Area Specific on state resistance benefits both major loss mechanisms - Lower Ron- Smaller chip area But it there a downside? Page 4

5 Choice of Topologies in often dictated by available power devices and voltage ratings versus Vf Topologies Server Phase Shifted Full Bridge Full Bridge Page 5 complexity Current Fed Push-Pull Resonant Reset Forward Flyback Dual Interleaved Half Forward Bridge Converter Half Bridge Two Transistor Forward Single Transistor Forward output power, watts

6 Topology Flyback Characteristics of major SMPS Topologies Useful power level 5 to 150W Switch voltage Vin+(Np/Ns)*Vout Switch power Pin Transformer Utilization Poor/specialized design Duty Cycle <0.5 Out Ripple Frequency F Relative Total Cost Low-moderate 1T Forward 10 to 250W 2 X Vin Pin Fair-good no taps required <0.5 F Low Resonant Reset Forward 10 to 250W HV 500W+ Can be > 2-3X Vin Pin Excellent No taps required <0.7 F Low 2T Forward 100 to 800W Vin Pin Fair-good- no taps <0.5 F Moderate ITTF 500 to 2kW+ Vin Pin/2 Fair-good- no taps <0.5 2 X F High Cuk 10 to 100W Vin/(1-D) Pin N/A (not isolated) <1 F Moderate Push-Pull 50 to 500W 2 X Vin+ Pin/2 Moderate taps req d <1 2 X F Moderate Half Bridge 50 to 500W Vin Pin/2 Good- sec tap req d <1 2 X F Moderate Full Bridge 500 to 2kW Vin Pin/2 Good tap or CD req d <1 2 X F High ZVS Bridge 600 to 5kW Vin Pin/2 Good tap or CD req d High CF IBM PP/CF Power & 150 to 1kW 600 Bridge to 5kW+ Vin X 2, Vin Pin/ Pin/2 Excellent flexible output configurations <1 2 X F High Page 6

7 Where is the main part of RDS[on] in HV MOSFETs? Why is this a problem? R DS[ON] is determined by the epitaxial layer- Source Gate typically 8 mm for 60V MOSFETs, typically mm for 600V MOSFETs R S * AL metalization Poly-Gate SiO 2 n + Page 7 R DS(on) Analysis V V DS 30V DS 600V R S * 7 % R n + 6 % R ch 28 % R a 23 % R epi 29 % R sub 7 % R S * = packaging R S * 0.5% R n % R ch 1.5 % R a 0.5 % R epi 96.5 % R sub 0.5 % n + R n + R ch Drain metalization R a R epi R Sub n - Drain drift region substrate 96.5% of R DS(on) for high voltage standard MOSFET determined by the epitaxial resistance Conventional epi MOSFET p + R on /Area ~ V (BR)DSS 2,4...2,6

8 Key milestones in planar DMOS Power MOSFET switches development timeline 1 st DMOS gen. Lidow, Kinzer 2 nd DMOS gen. Chen & Hu, IEEE 1982 SOTA DMOS Kobayashi ISPSD 2001 Page 8

9 Charge compensation principle developed from RESURF structure Page 9 RESURF principle Appels, IEDM p/n pair Multi-RESURF Coe, US patent 1988 > 2 p/n pairs Compensation device Deboy 1998, di Saggio 2000 > 100,000 p-columns

10 Super Junction MOSFETs use charge compensation principle: Increasing drain voltage forms folded depletion region When the transistor is turning off, the thin depletion region at low voltage follows the structure of the P=columns, resulting in high output capacitance at V DS < 35 V Charge compensation column structure under p-wells in source Source Gate AlSi metalization R S * Poly-Gate R n + n + R ch R a R epi current ID n + R Sub Gate spacer SiO n + 2 p + n - substrate Page 10 Depletion region forms with merging of carriers from doping in n+ region and p+ Drain metalization Drain

11 Visualization of Voltage Potential gradients during turn-off state animation Device concept VDS VDS = = V V Page 11

12 Loss balance example for hard switching- DMOS vs superjunction MOSFET P Intrinsic switching losses at on hard turn-on V max ( A ) = f ( V ) V sw 0 C ds dv P stat Conduction losses 2 (A) = I R (A) rms on Page 12 There is an optimum chip size In each transistor technology for minimum total power dissipation at a given clock frequency

13 Six years later, Super-junction moves from 14 µm to 7.5 µm cell pitch to lower area specific Ron Page 13

14 Coss as a function of VDS for C3 and C5 generation CoolMOS with 380 mω on state resistance Page 14

15 Improved area specific Ron leads to lower output capacitance and switching loss Page 15 P-column form large folded capacitor at low voltage Smaller cell pitch needed to increase doping levels in current path and charge compensation structure High capacitance at low voltage increases energy storage, but also acts as non-linear turn-off snubber Capacitance falls to very low levels at high voltage (over 100V), contributing to low turn-on switching loss

16 Non-linear output capacitance acts as dynamic snubber with low output C eff reduces losses Capacitance [pf] C gs V / 190 mω Standard-MOS Compensation MOS C 100 C ds gd 10 V 0 ds [V] Switching energy will will be be stored in in the the output capacitance and not not dissipated in in the the channel during turn-off transient Page 16

17 New Merged Schottky-PN Structure with Low Ohmic connection P Regions SiC wide bandgap material- typical room temp PN junction potential of 3 V P regions not only reduce voltage gradient at Schottky barrier, but are terminated with low ohmic connection Above junction potential, PN junctions provide PN diode operation thinq! SiC Schottky diode Si pn tandem diode ultrafast Si pn diode 4 2 I [A] Page T=150 C, V DC =400V Time [µs]

18 Forward characteristic with 400µs pulse time at temperatures from -55 C to 175 C Page 18 Bipolar behavior verified 100% testing of V f at 6X rated current

19 Comparing Surge and i 2 t Capability with standard SiC diode 3X Greater I FSM 6X Greater i 2 t value Page 19

20 2 nd Gen SiC Schottky diode - stable avalanche with positive temperature coefficient Page 20

21 Interleaved two transistor Forward Converter and primary switch waveforms, secondary current waveforms Current ripple cancellation eases output capacitor requirements Page 21

22 The ITTF has interesting characteristics for isolated supply stage Basic characteristics Simple, highly efficient topology Output stage and voltage ripple identical to ZVS with current doubler Easy current control scheme No resonance inductor Especially highly efficient at low load, good for redundant PS No use of body diode, better potential MOSFET reliability TTF topology well known from lower power ranges Snubbing optimization and other tweaks indicate further gains are possible Less complex system design = shorter time to market Page 22

23 Selection criteria based on Operating conditions Forward PWM Isolation stage Two Transistor Forward, ITTF Converter Characterisitc Input voltage range 300V DC to 400VDC typical- typical 25 35% range of I 2 x R No body diode conduction Selection based on FOM and balance of conduction losses (I 2 x R) and switching losses (C eff X F clk plus crossover losses) Main selection criteria: V DS[BR] rating R [DS]on Cout effective Energy Related Switching Crossover losses Secondary selection criteria- Gate charge, R Gate, and I D ratings Suggest FOM based on RDS[on] X Cout effective Energy related Optimum component selection based on balancing conduction losses and fixed switching losses over load range, light to full load; applications envelope doesn t have wide worst case range Page 23

24 Application Evaluation: R DS[on], C O[effective], Gate Q g total Page 24

25 Example- 1 kw 130 khz 400V bus Worst case Loss component estimation for IPP60R99CS Peak Switching Current under bulk bus low line (300V) I PEAK _ Sw P Out _ Max = = 3.67A 2 VIn _min D max Estimated conduction losses at peak switching current Estimated Crossover Switching losses (tends to be overestimated for CoolMOS) Estimated switching loss from C OSS (using C O(ER) ) Estimated gate drive loss: ( ) 2 Pd = I R ( T ) = Watt Conduction Peak _ Sw DS[ on] J VIn _max PdSwitching = IPeak _ Sw ( ton + toff ) fs = Watt PdCoss = CO( ER) VIn _ Max fs = Watt 2 Pdgate = QG VGate fs = 0.1 Watt Same calculations for IPP60R199CP transistor: Same crossover loss, Coss related loss is cut in half to ~3/4 watt, conduction loss only rises to ½ watt IBM Power total & losses drop from 3.9 watts to 3.3 watt, Costs are reduced with much smaller chip in the forward transistor. Symposium Net 2005 gain is about 2.4 watts of less dissipation, notching the overall efficiency up about 0.24%. Page 25

26 The ITTF shows efficiency gain at light load especially in the range common with redundant shared supplies 0,95 0,9 1 % better over next best alternative at full load Efficiency 0,85 7 % points better efficiency at 1/3 load ZVS CoolMOS CS ITTF CoolMOS CS ITTF Competitor 0,8 Page 26 0, P in [W]

27 High Efficiency PFC-Stage eliminates bridge rectifier Concept In development ID1 ID2 AC D1 L1 PFC Choke VACIN L2 Q1 IQ1 ID2 D3 D2 Q2 IQ2 C1 Bulk ID1 D4 Main converter including with isolation Page 27

28 First Prototype Power Stage Configuration Page 28

29 Control Implementation with ICE1PCS01 Page 29

30 99% efficiency PFC stage demoboard Output power: 1500W Input Voltage: V Output Voltage: 380 V fsw= 130 khz Semiconductors: CoolMOS TM CS (99mOhm) 600V thinq! TM 2nd Gen. SiC diode ICE1PCS01 as Control IC Page 30

31 Nearly 99% efficiency at 1500W output 100,0 99,5 Efficiency: V full load Efficiency [%] 99,0 98,5 98,0 97,5 97,0 Competitor, 4*500V/0.25 Ohm CoolMOS CS, 2*IPP60R099CS Page 31 96, Pout [W]

32 References Brian Griffith, High Density AC/DC Power Supplies, Intel Technology Symposium, 2002 G. Deboy,M. März, J. Stengl, H. Strack, J. Tihanyi, H. Wever, A new generation of high voltage MOSFETs breaks the limit of silicon, pp , Proc. IEDM 98, San Francisco, Dec M. Saggio, D. Fagone, S. Musumeci, MDmesh : innovative technology for high voltage power MOSFETs, Proc. ISPSD 200, pp , Toulouse May B. Lu, W. Dong, Q. Zhao, F. Lee, "Performance Evaluation of CoolMOS and SiC Diode for Single-Phase Power Factor Correction Applications", APEC 2003 Conference proceedings. L. Hriscu, G. Casaru, Low Loss Snubbing in DC-DC Converters, Proc. Electronica Power Electronics Conference April 2004, San Francisco. Page 32