VHDM & VHDM-L Series. High Speed. Electrical Characterization

Transcription

1 VHDM & VHDM-L Series High Speed Electrical Characterization HDM, VHDM & VHDM-HSD are trademarks or registered trademarks of Teradyne, Inc. Date: 2/14/2003

2 SCOPE 1. The scope of this document is to define the electrical performance of both the VHDM and VHDM- L Series connector products. 2. Parameters measured include reflections, multi-line crosstalk, signal delay and rise time degradation for the 8 row VHDM connector. Although 5 & 6 row are not included in this report, the 8 row servers as a good estimation for overall connector performance 3. Since the VHDM-L Series electrical performance performs like an open pinfield. The most important factors, relative to electrical performance, are signal rise time and signal/ground pattern of contacts. 4. Test equipment used in collecting data includes Tektronix 11801C TDR and Agilent s 8720 VNA. Standard measurement and calibration setups were used. Date: 2/14/2003 Page 2 of 19

3 TEST MEASUREMENT SETUPS: Figure s 1, 2 & 3 show typical TDR test setups. Test Daughter Card Tektronix C Oscilloscope Instrument Controller GPIB HDM 50 Ohm Cable Test Backplane Figure 1: Typical TDR Test Setup Test DaughterCard Tektronix C Oscilloscope Instrument Controller GPIB HDM 50 Ohm Cables Test Backplane Figure 2: Typical TDR Crosstalk Setup Date: 2/14/2003 Page 3 of 19

4 Test DaughterCard Tektronix C Oscilloscope Instrument Controller Calibration Trac e GPIB HDM Test Backplane 50 Ohm Cables Figure 3: Typical Propagation Delay Setup TEST BOARDS & BOARD TEST PATTERNS: Data collected in this report was measured using the test boards shown in Figures 1 & 2 LEFT SIDE (Rows 1-4) Daughterboard Left side silkscreen down Shield side of header Backplane Right side silkscreen (back edge of backplane) Date: 2/14/2003 Page 4 of 19

5 Figure1 RIGHT SIDE (Rows 7-10) Daughterboard Right side silkscreen down Backplane Right side silkscreen (back edge of backplane) Figure 2 Shield side of header The high-speed layers used Rogers 4003, in a standard stripline construction. Standard high-speed layout/routing practices were employed during board design and fabrication. In order to minimize fixture loss, traces to and from the connector were kept to a 2 distance. In addition, cal traces for the 1x and 2x distances were created, to measure the fixture burden. Due to the limitation of the number of usable pins, the board was split into two S/G test patterns, shown in Figure 3. The left side of the pattern gives the ability to drive all lines and look at worst case crosstalk conditions while the right side shows typical performance using a 1:1 S/G configuration Date: 2/14/2003 Page 5 of 19

6 VHDM Backplane Signal Pattern H G COLUMN R O W F E D C B A - Grounded pins - Single ended signals VHDM 8 Row 10 wafer module Figure 3: PCB Pin Test Pattern VHDM SINGLE ENDED CONNECTOR IMPEDANCE: Table 1 shows the first column impedance data, minus test board via effects, for the single ended 1:0 gnd pattern. This column does not have a shield on one side and would be considered the least behaved, electrically VHDM Single ended TDR Impedance Data without via effects, 1:0 Gnd pattern Pin # Rise Time Tr=100 Ps Tr=200 Ps Tr=300 Ps Tr=500 Ps 1.00E E E E-010 A B C End Column D E F G H average Note: All rise times at 10-90% Table 1: Single ended VHDM unshielded column impedance data Date: 2/14/2003 Page 6 of 19

7 Table 2 shows the middle column impedance data, minus test board via effects, for the single ended 1:0 gnd pattern. These columns have shields on both sides of the signals VHDM Single ended TDR Impedance Data without via effects, 1:0 Gnd pattern Pin # Rise Time Tr=100 Ps Tr=200 Ps Tr=300 Ps Tr=500 Ps A B Middle Column G H E G Middle Column H G Middle Column H average Note: All rise times at 10-90% Table 2: Single Ended VHDM Impedance data for columns 2, 3 & 4 Figure 4 shows a typical impedance plot taken from the data above Connector Sma Out PCB Via in PCB via out Date: 2/14/2003 Page 7 of 19

8 Figure 4: Typical Single Ended VHDM TDR plot VHDM DIFFERENTIAL ENDED CONNECTOR IMPEDANCE: Table 3 shows the first column Impedance data, with test board via effects, for the differential 1:0 gnd pattern. This column does not have a shield on one side and would be considered the least behaved, electrically. VHDM Differential TDR Impedance Data with test board via effects, 1:0 Gnd pattern Pin # Rise Time Tr=125 Ps Tr=200 Ps Tr=250 Ps Tr=300 Ps 1.00E E E E-010 A1,B B1,C C1,D End Column D1,E E1,F F1,G G1,H average Note: All rise times at 10-90% Table 3: Differential VHDM unshielded column impedance data Table 4 shows the middle column Impedance data, minus test board via effects, for the differential 1:0 gnd pattern. These columns have shields on both sides of the signals Table 4: Differential VHDM Impedance data for columns 2, 3 & 4 Date: 2/14/2003 Page 8 of 19

9 Tr = 45 ps 10/90% Tr = 200 ps 10/90% Fi gure 5: Typical Differential Impedance plot VHDM SINGLE 1/1 S/G CONNECTOR IMPEDANCE: Table 5 shows columns 8-10 impedance data, with test board via effects, for the single ended 1:1 gnd pattern. Pin # Tr = 200 ps A B D H A C E G H B D F H Table 5: Single ended impedance data for columns 8-10 Date: 2/14/2003 Page 9 of 19

10 VHDM CONNECTOR SINGLE ENDED CROSSTALK: Table 6 shows the first column Next crosstalk data, at various rise times, for the single ended 1:0 gnd pattern. This column does not have a shield on one side. VHDM Single Ended Crosstalk Driven Pins Quiet Pin Crosstalk ( % ) Tr=125 Ps Tr=200 Ps Tr=250 Ps Tr=300 Ps Tr=400 Ps Tr=500 Ps 1.00E E E E E E-010 B1,C1,D1,E1 A A1,C1,D1,E1 B A1,B1,D1,E1 C B1,C1,E1,F1 D End Column C1,D1,F1,G1 E D1,E1,G1,H1 F D1,E1,F1,H1 G D1,E1,F1,G1 H average Table 6: Single ended VHDM unshielded column NEXT data Table7 shows the single ended NEXT contribution across the shield. Notice that most of the noise comes from within column. VHDM Single End Crosstalk - Across Shield Driven Pins Quiet Pin Crosstalk ( % ) Tr=125 Ps Tr=200 Ps Tr=250 Ps Tr=300 Ps Tr=400 Ps Tr=500 Ps 1.00E E E E E E-010 G2,G3,G4 G G1,G3,G4 G H2,H3,H4 H Across Shield H1,H3,H4 H average Table 7: Single ended across shield NEXT VHDM DIFFERENTIAL ENDED CONNECTOR NEXT: Table 8 shows the differential NEXT in the unshielded connector column. VHDM Differential Crosstalk - Middle Column Driven Pins Quiet Pins Crosstalk ( % ) Tr=125 Ps Tr=200 Ps Tr=250 Ps Tr=300 Ps Tr=400 Ps Tr=500 Ps 1.00E E E E E E-010 C1-D1,E1-F1 A1-B Unshielded Column C1-D1,E1-F1 G1-H average A1-B1,E1-F1 C1-D Unshielded Column C1-D1,G1-H1 E1-F average Table 8: VHD M Differential NEXT within column Date: 2/14/2003 Page 10 of 19

11 Table 9 shows the Differential NEXT contribution across the shield. Notice that most of the noise comes from within column. VHDM Differential Crosstalk - Across Shield Driven Pins Quiet Pins Crosstalk ( % ) Tr=125 Ps Tr=200 Ps Tr=250 Ps Tr=300 Ps Tr=400 Ps Tr=500 Ps 1.00E E E E E E-010 G2-H2,G3-H3 G1-H Across Shield G1-H1,G3-H3 G2-H average Table 9: Differential VHDM NEXT across shields VHDM CONNECTOR PROAGATION DELAY Typical VHDM 8 row propagation delays are as follows: H G F E D C BA 50 ohm test boards A' B'C' D' E'F' G' H' Delay measurement test points VHDM Propagation Delay Test Signal Rise Time: 500 ps (10-90%) A -> A' B -> B' C -> C' D -> D' E -> E' F -> F' G -> G' H -> H' 152 ps 171 ps 188 ps 211 ps 222 ps 245 ps 262 ps 290 ps Date: 2/14/2003 Page 11 of 19

12 VHDM L SERIES ELECTRICAL PERFORMANCE: This section of the electrical report includes both Sparameters and TDR data for the VHDM L Series connector. Since the daughtercard wafer contains a floating shield, the S parameter data, shown below, shows no visible oscillation for the frequency s swept. TEST BOARD PATTERN: Figure 6 shows the S/G pattern used on the VHDM L Series test boards H G F COLUMN R O W E D C B A Figure 6: VHDM-L Series S/G test pattern Date: 2/14/2003 Page 12 of 19

13 Frequency Domain Figures 7 thru 14 shows I/L data taken for each terminal. During each measurement all unused terminals were terminated into 50 ohms. Also please note that no resonances were measured, which indicates the disconnected shields have no effect up to the measured frequencies. 0-3 db Red: A10 I/L Blue: B10 I/L Freq, Ghz Figure 7: VHDM-L Series I/L Pins A10 & B db Red: A9 I/L Blue: B9 I/L Freq, Ghz Figure 8: VHDM-L Series I/L Pins A9 & B9 Date: 2/14/2003 Page 13 of 19

14 db Red: A8 I/L Blue: B8 I/L Freq, Ghz Figure 9: VHDM-L Series I/L Pins A8 & B db Red: D8 I/L Blue: E8 I/L Freq, Ghz Figure 10: VHDM-L Series I/L Pins D8 & E8 Date: 2/14/2003 Page 14 of 19

15 db Red: D9 I/L Blue: E9 I/L Freq, Ghz Figure 11: VHDM-L Series I/L Pins D9 & E db Red: G10 I/L Blue: E10 I/L Freq, Ghz Figure 12: VHDM-L Series I/L Pins G10 -H10 Date: 2/14/2003 Page 15 of 19

16 db Red: G9 I/L Blue: E9 I/L Freq, Ghz Figure 13: VHDM-L Series I/L Pins G9-H9 0-3 db Red: G8 I/L Blue: E9 I/L Freq, Ghz Figure 14: VHDM-L Series I/L Pins G8-H8 Date: 2/14/2003 Page 16 of 19

17 VHDM-L SERIES TDR Time Domain Single Ended TDR Data Figures 15 thru 17 represent typical impedance plots at a rise time of 77 ps 10-90%, for terminals A9 thru H9, respectively, using the signal/ground configuration in Figure 6. Since this is probably too aggressive for the open pin field structure, Table 10 tabulates max impedance values at slower rise times, using the same pins. Terminal Tr = 77 ps Tr = 150 ps Tr = 300 ps Tr = 500 ps Tr = 1 ns Pin A9 67 ohms 61 ohms 55 ohms 53 ohms 52 ohms Pin B9 64 ohms 59 ohms 54 ohms 52 ohms 51 ohms Pin D9 64 ohms 61 ohms 55 ohms 53 ohms 52 ohms Pin E9 66 ohms 60 ohms 55 ohms 53 ohms 51 ohms Pin G9 68 ohms 65 ohms 60 ohms 56 ohms 54 ohms Pin H9 68 ohms 67 ohms 63 ohms 59 ohms 55 ohms Table 10: Typical max to baseline impedance values for varing rise times Oh ms Red: A9 Blue: B m2 Time, ns m2 time=620.0psec real(meas_ohms1)= Figure 15: A9 & B9 Tr = 77 ps Date: 2/14/2003 Page 17 of 19

18 Oh ms Red: D9 Blue: E Time, ns m5 m5 time=695.0psec real(meas_ohms4)= Figure 16: D9 & E9 Tr = 77 ps Oh ms Red: G9 Blue: H Time, ns m7 m7 time=785.0psec real(meas_ohms6)= Figure 17: G9 & H9 Tr = 77 ps Date: 2/14/2003 Page 18 of 19

19 VHDM-L SERIES Crosstalk Data Tables 11 & 12 tabulate max NEXT for a 2/1 & 1/1 signal to ground ratio for the following conditions: Driven Lines: A8, A10, B8, B9, B10 Quiet Line: A9 Driven Lines: G8, G10, H8, H9, H10 Quiet Line: B9 Rise times: 77ps, 150ps, 300 ps, 500 ps 1ns No via effects were de-embedded in the data shown below Crosstak Table with a 2:1 signal to ground configuration, per Fig 6 QuietTerminal Tr = 77 ps Tr = 150 ps Tr = 300 ps Tr = 500 ps Tr = 1 ns Pin A9 42 % 37 % 30 % 23 % 12 % Table 11: Max % crosstalk for varing rise times at 2/1 signal/ground ratio Crosstak Table with a 1:1 signal to ground configuration, per Fig 6 QuietTerminal Tr = 77 ps Tr = 150 ps Tr = 300 ps Tr = 500 ps Tr = 1 ns Pin B9 17 % 13 % 8 % 6 % 4 % Table 12: Max % crosstalk for varing rise times at 1/1 signal/ground ratio Date: 2/14/2003 Page 19 of 19

20 VHDM-HSD High Speed Electrical Characterization HDM, VHDM & VHDM-HSD are trademarks or registered trademarks of Teradyne, Inc. Date: 2/14/2003

21 SCOPE 1. The scope of this document is to define the electrical performance of VHDM 5, 6 & 8 row VHDM- HSD Series connector products. 2. Parameters measured include S parameters, reflections, multi -line crosstalk, signal delay and rise time degradation, for all HSD connectors. All rise times in this report are based on 10-90%. 3. Test equipment used in collecting data includes Tektronix 11801C TDR and Agilent s 8720 VNA. Standard measurement and calibration setups were used during data collection. Date: 2/14/2003 Page 2 of 16

22 TEST MEASUREMENT SETUPS: Figure s 1, 2 & 3 show typical TDR test setups. Test Daughter Card Tektronix C Oscilloscope Instrument Controller GPIB HDM 50 Ohm Cable Test Backplane Figure 1: Typical TDR Test Setup Test DaughterCard Tektronix C Oscilloscope Instrument Controller GPIB HDM 50 Ohm Cables Test Backplane Figure 2: Typical TDR Crosstalk Setup Date: 2/14/2003 Page 3 of 16

23 Test DaughterCard Tektronix C Oscilloscope Instrument Controller Calibration Trac e GPIB HDM Test Backplane 50 Ohm Cables Figure 3: Typical Propagation Delay Setup TEST BOARDS & BOARD TEST PATTERNS: Test Boards: All test boards consists of the following construction: Daughtercard and Backplane Board.115 Thickness Layer Count 6 Board material Rogers 4003 on signals, all others FR4 SMA launch Molex high speed design Signal layers Layer 2 & 7 Board construction 2.5 Stripline from SMA to conn via Date: 2/14/2003 Page 4 of 16

24 Figures 4 & 5 show the test fixture used for high speed data collection. Figure 4 VHDM-HSD 8 row Daughtercard Date: 2/14/2003 Page 5 of 16

25 Figure 5: VHDM-HSD 8 row Backplane Each set of Backplane and Daughtercard boards were fabbed in one panel, to minimize board variations. In addition each panel included calibration traces, shown in Figure 6,defined as follows: 1). Trans 1x path length from SMA to the first connector via launch. This defines the speed of the signal arriving at the connector. 2). Reflect1 2x trans line or Total path length from Backplane to Daughtercard: Defines fixture loss contribution. 3). Reflect2 Same as reflect 1 with two press fit pin via s added in the center to help characterize board via effects. All board routing were non-coupled strip lines, to minimize any differential board effects Date: 2/14/2003 Page 6 of 16

26 Figure 6: Typical Panel cal traces Test Equipment: Below is a list of equipment/software used to collect and post process the data: Agilent 8722ES with N4418A test box Tektronix TDR Agilent ADS and PLTS software Appropriate cal kits & high speed cables & terminations Test Fixture Electrical Characterization: Figures 7 thru 9 show TDR and VNA data for both the Trans and Reflect1 cal traces. This data shows that the test fixtures will support bandwidths of 9 3 db or has an equivalent system rise time degradation of approx. 40 ps Date: 2/14/2003 Page 7 of 16

27 Trans Line Tr=35 ps 10 Ω/Div SMA Imp 45 ohms Trace Imp Figure 7: 2.5 Trans Line: TDR Tr=35 ps, 10-90% Date: 2/14/2003 Page 8 of 16

28 Reflect1 Line Tr=35 ps 10 Ω /Div SMA Imp 45ohms Trace Imp Figure 8: 5 Reflect1 Line: TDR Tr=35 ps, 10-90% Reflect1 Line I/L 3dB/Div Figure 9: Reflect1 line I/L Date: 2/14/2003 Page 9 of 16

29 Figure 10 shows the pin map for the 8 row or 40 pair connector patterns. Although not shown in this document, the 5 & 6 row or 20 pair follow similar patterns COLUMN H R O W G F E D Signal Lines Gnds C B A Figure 10:VHDM-HSD 8 row Signal layout Electrical Data: Impedance: Figure 11 shows typical data plots for the longest and shortest VHDM-HSD 8 row impedance 75ps 10-90% 10 Ω/Div Date: 2/14/2003 Page 10 of 16

30 110 Ω PCB Blue: Longest row Green: Shortest Row 110 Ω conn interface 84 Ω Daughtercard via 68 Ω Backplane via Figure 11: Molex VHDM-HSD 8 row pair Tr=75 ps 10-90% VHDM-HSD 5 Row Electrical Data: All data shown below was measured driving the closed 5 pair contributors. VHDM-HSD 5 row data NEXT: Measured Near-End various rise times 10-90% 20-80% AB DE 50ps 38ps 4.15% 3.43% 75ps 56ps 3.64% 3.01% 100ps 75ps 3.34% 2.65% 200ps 150ps 2.13%% 1.51% 300ps 225ps 1.88% 1.32% Data duplicated from Teradyne Electrical Characterization report,tb-2082 VHMD-HSD 5 row data NEXT: Date: 2/14/2003 Page 11 of 16

31 Measured Near-End various rise times 10-90% 20-80% AB DE 50ps 38ps -4.23% -4.73% 75ps 56ps -3.68% -4.3% 100ps 75ps -3.34% -3.89% 200ps 150ps -2.08% -2.72% 300ps 225ps -2.04% -2.59% Data duplicated from Teradyne Electrical Characterization report,tb-2082 VHDM-HSD 5 Propagation Delay: HSD 5 row Prop Delay Pin Electrical Length E E 146ps D-D 136ps B-B 104ps A-A 96ps These numbers do not include any board effects VHDM-HSD 6 Row Electrical Data: All data shown below was measured driving the closed 5 pair contributors. VHDM-HSD 6 row data NEXT: Measured Near-End various rise times 10-90% 20-80% AB DE 50ps 38ps 2.195% -2.50% 75ps 56ps 2.01% -2.15% 100ps 75ps 1.91% -1.8% 200ps 150ps 1.64% -1.06% 300ps 225ps 1.29% -0.87% Data duplicated from Teradyne Electrical Characterization report,tb-2082 VHDM-HSD 6 row data NEXT: Measured Near-End various rise times 10-90% 20-80% AB DE 50ps 38ps -4.38% -3.58% 75ps 56ps -4.18% -3.26% 100ps 75ps -3.71% -2.78% 200ps 150ps -2.51% -1.46% 300ps 225ps -1.53% -0.92% Data duplicated from Teradyne Electrical Characterization report,tb-2082 VHDM-HSD 6 Propagation Delay: VHDM-HSD 5 row Prop Delay Pin Electrical Length E E 145ps D-D 138ps B-B 85ps Date: 2/14/2003 Page 12 of 16

32 A-A 96ps These numbers do not include any board effects VHDM-HSD 8 Row Electrical Data: All data shown below was measured driving the closed 8 pair contributors. VHDM-HSD 8 row data NEXT: Measured Near-End various rise times 10-90% 20-80% AB DE GH 50ps 38ps 3.95% 2.32% 2.76% 75ps 56ps 3.33% 2.08% 2.65% 100ps 75ps 2.85% 1.69% 2.18% 200ps 150ps 1.56% 0.85% 1.24% 300ps 225ps 1.30% 0.62% 1.06% Data duplicated from Teradyne Electrical Characterization report,tb-2082 VHDM-HSD 8 row data FEXT: Measured Near-End various rise times 10-90% 20-80% AB DE GH 50ps 38ps -4.18% -2.99% -4.01% 75ps 56ps -3.8% -2.48% -3.51% 100ps 75ps -3.2% -2.16% -3.10% 200ps 150ps -1.9% -1.21% -1.77% 300ps 225ps -1.36% -0.80% -1.26% Data duplicated from Teradyne Electrical Characterization report,tb-2082 VHDM-HSD 8 Propagation Delay: VHDM-HSD 5 row Prop Delay Pin Electrical Length H-H 200ps G-G 194ps E E 151ps D-D 145ps B-B 108ps A-A 99ps These numbers do not include any board effects Date: 2/14/2003 Page 13 of 16

33 3.0 Molex VHDM-HSD 8 row A 10B10 % N EX T Time, ns Figure 12: VHD M-HSD 5 row pair A10B10 NEXT, all other lines Tr=75 ps 10-90% VHDM-HSD 8 Row Frequency Domain Data: Figures 13 thru 16 show typical differential I/L and R/L data for the longest and shorted row on thevhdm-hsd 8 connector. Please note that board e ffects have not been de-embedded from this data 10db/div Figure 13: VHDM-HSD 8 row R/L for differential pair A10-B10 Date: 2/14/2003 Page 14 of 16

34 3db/div Ghz Figure 14: VHDM-HSD 8 row I/L for differential pair A10-B10 10db/div Figure 15:VHDM-HSD 8 row R/L for differential pair G8H8 Date: 2/14/2003 Page 15 of 16

35 3db/div Ghz Figure 16: VHDM-HSD 8 row I/L for differential pair G8-H8 Date: 2/14/2003 Page 16 of 16