Modeling and Optimized Design of Current Mode MUX/XOR and D Flip-Flop

Transcription

1 452 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 47, NO. 5, MAY 2000 Modeling and Optimized Design of Current Mode MUX/XOR and D Flip-Flop M. Alioto and G. Palumbo, Senior Member, IEEE Abstract This paper deals with current mode logic (CML) and, in particular, models and optimized design strategies for MUX, XOR, and D flip-flop are presented. Both simple and accurate models for propagation delay are proposed. The models represent propagation delay with a few terms, providing a better insight into the relationship between delay and its electrical parameters, which in turn are related to process parameters. The main difference between accurate and simple models is that the former need only a few SPICE simulations to properly evaluate model parameters. The simple models show errors which are always lower than 20%, while accurate models have typical errors of 2%. Design optimization is in terms of bias currents giving minimum propagation delay, and it has been demonstrated that at the cost of a 10% increase in propagation delay we can reduce power dissipation by 40%. The models and design strategies are validated using both a traditional and a high-speed bipolar process which have a transition frequency equal to 6 and 20 GHz, respectively. Index Terms Bipolar logic device, bipolar transistor circuits, current-mode logic, digital integrated circuits, emitter-coupled logic, high-speed integrated circuits, MUX, switching circuits,. I. INTRODUCTION RECENTLY, interest in the high-speed digital bipolar circuit has been increasing [1] [3]. This is due to the continuously expanding markets for mobile telecommunication systems, including automobile and portable telephones, gigabytes/s optical-fiber transmission links, and high-speed measurement equipment. The key digital gates in those fields are exclusive OR (XOR) and D flip-flop (D-FF). The ultrahigh-speed frequency dividers, which are made up of flip-flops, are not only a technology test circuit for demonstrating the high-frequency performance of newly developed transistors, but are also one of the key devices in microwave and satellite communication systems. Indeed, Prescaler IC s that operate in the gigahertz frequency range are essential for frequency synthesizers in mobile telecommunication systems [4] [12]. Moreover, the high-speed time-division multiplexers (MUX s), which are realized with XOR gates, are important basic components in numerous high-speed optical-fiber transmission systems [13] [24]. Current mode logic (CML) and emitter coupled logic (ECL) are the main approaches for implementing bipolar high-speed gates. In the design of these digital circuits, minimization of the propagation delay is a fundamental step, and the target must be achieved with the lowest power consumption. Manuscript received July 1999; revised January This paper was recommended by Associate Editor G. Gielen. The authors are with the Department of Electrical and Electronic Systems, University of Catania, I Catania, Italy. Publisher Item Identifier S (00) The propagation delay models available in the literature for high-speed bipolars are not sufficiently simple for use in pencil and paper optimized design. The model derived by using sensitivity analysis [25] [28] is expressed as sum of a high number of terms (for a CML inverter, which is the simplest gate, the terms are 30 and they increase for more complex gates). In particular, it needs four times the number of simulations than terms to define their values. The approaches proposed in [29] [31] are based on the linearization of the device, but the former method does not lead to a closed-form delay expression, and the other two are not extended to the ECL gates unless by using another approach like the average branch current analysis, which was previously introduced in [32] and [33]. Other methods proposed are too complex for use during design [34]. Recently, the authors proposed a simple model for CML and ECL inverters [35] which can be used to achieve an optimized design of CML and ECL inverters [36]. Unlike the other models available in the literature for high-speed bipolars, the proposed approach is sufficiently simple to allow a pencil-and-paper optimized design. In this paper, models and optimized design of MUX/XOR and flip-flop in CML and ECL design styles are presented. The simpler ones have a maximum error lower than 20%, which is sufficiently accurate to allow an optimized design of the series gating, while the improved models exhibit an error lower than 5% in the range of interest. To perform the design, the bias currents minimizing the propagation delay of the gates are found. Moreover, we demonstrate that at the cost of a 10% increase in propagation delay we can reduce power dissipation by 40%. The models and the design examples are validated by using both a traditional and a high-speed bipolar process which have a transition frequency equal to 6 GHz and 20 GHz, respectively. II. CML MUX/XOR AND D-FF PROPAGATION DELAY MODELS A. Simple MUX/XOR Model A CML MUX and XOR are shown in Fig. 1(a) and (b), respectively. To achieve high-speed performance, their transistors work in a linear region and can be represented with a linearized model identical for both circuits. Let us consider only the input set which gives the worst propagation delay. As stated in [28], the worst case is with an input step at the lower level transistors, Q1-Q2, and setting constant the upper level inputs. This is because in the opposite case, there is a lower number of time constants which contribute to the final propagation delay, allowing intrinsic compensation between the base collector capacitance of the upper switching transistors to be achieved [37], [38]. For /00 $ IEEE

2 ALIOTO AND PALUMBO: CURRENT MODE MUX/XOR AND D FLIP-FLOP 453 where the diffusion capacitance is given by [25] where is the transistor transit time. The base collector capacitances are split into an intrinsic part and an extrinsic one, so as to take their distributed nature into account, using the technological parameter, which ranges between 0 and 1 (2) (3a) (3b) The collector-substrate capacitances,, are only junction capacitances. Moreover, since voltages move rapidly over a wide range, the junction capacitances are modified from their value in a zero-bias condition via coefficients given by [39] (4) Fig. 1. (a) MUX. (b) XOR. (a) (b) where is the built-in potential across the junction, is the grading coefficient of the junction, and and are the minimum and maximum direct voltages across the junction, respectively. It is worth noting that since the voltage variation at the emitter node of the upper transistors is small, we can use small-signal values for and [42]. Finally, it is worth noting that we are assuming a realistic case in which input A is driven by another CML gate. Hence, in the upper input, we have to include the equivalent output resistance of the previous gate, represented by the two resistances, in series with and. However, this equivalent output resistance must not be considered in the switching lower input because it is driven by an ideal voltage generator, which represents the voltage variation on the input node. Load effects on that node can be properly taken into consideration by evaluating the propagation delay of the previous gate. Assuming a dominant pole behavior with a time constant, the propagation delay, is equal to The time constant is given by the sum of time constants associated at each capacitance when the others are opened (i.e., set to a zero value) [40] [42]. Thus, by inspection of the circuit in Fig. 2, neglecting terms with respect to terms and lumping and into, and, respectively, we get gate symmetry without loss of generality, we assume input A to be high (and input B of the MUX to be low). Hence, transistors Q3 and Q6 are on and transistors Q4 and Q5 are off. Since differential operation is assumed, we can limit our analysis to the half-circuit model in Fig. 2. The transconductance, and the input resistance, pertain to the small signal model and, because they are equal for the upper and lower transistors, result in and, respectively. Indeed, the bias condition considered emerges when the lower transistors have half of the switched current. Given that the upper transistors are on, all this current flows through them. The resistances, and are resistive parasitics. The base emitter capacitances of the switching pair (Q1 and Q2),, are composed of a diffusion capacitance and a junction capacitance (1) (5) where and are for lower and upper transistors, respectively, and is the equivalent resistance at the emitter of Q3, given by (6)

3 454 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 47, NO. 5, MAY 2000 Fig. 2. MUX/XOR half-circuit model. The propagation delay is the sum of eight main terms which have a simple circuit meaning. Three terms are due to the lower transistors, four to the upper transistors, and one to the load. B. Improved MUX/XOR Model Although the accuracy of the previous model may be adequate enough during pencil and paper design, it is not when implementing an accurate simulation model to evaluate the delay of a complex system. We thus have to improve the accuracy of the model. The strategy adopted was to introduce five proper coefficients, evaluated by a few simulation runs with a numerical procedure. More specifically, the model given by (5) now becomes should be noted that this approach is not equal to the one used for the improved CML inverter model, where coefficients are introduced for all the parasitic capacitances [35]. The reason is that to apply this approach for the XOR gate, six more coefficients are required, so that the procedure loses its intrinsic simplicity. Thus, to minimize error without increasing the number of the parameters, four of the coefficients are associated to the most critical capacitances, while one is used for all the propagation delay terms unless it is associated with the load capacitance. Among the many ways to obtain the coefficients, the most efficient, because it requires few simulation runs, is minimizing the functional below (8) In (8), parameter is itself a variable, but, according to our experience, it can be set to 5. Moreover, by increasing the load capacitance, the behavior tends to a simple linear one-pole function; hence, the functional is minimized by varying only the bias current and setting the load capacitance equal to zero in all cases. Minimization of functional can be achieved with any type of numerical software such as Mathcad, Matlab, etc. (7) where the values for the base collector and collector-substrate capacitances of Q3 and Q5 are used in zero-bias condition. It C. XOR Model Validation To evaluate the accuracy of the simple and accurate propagation delay models of the XOR, given by (5) and (7), respectively, a comparison with SPICE simulations was carried out. In

4 ALIOTO AND PALUMBO: CURRENT MODE MUX/XOR AND D FLIP-FLOP 455 TABLE I 6-GHz TECHNOLOGY X =0:146 and I =8:91E 0 18 A. ^ This capacitance was evaluated using its small-signal expression. TABLE II 20-GHz TECHNOLOGY Fig. 3. Analytical and simulated delay versus bias current I of MUX/XOR for 6-GHz technology. X =0:23 and I =7:4E 0 18 A. ^ This capacitance was evaluated using its small-signal expression. TABLE III USEFUL PROCESS PARAMETERS Fig. 4. Analytical and simulated delay versus bias current I of MUX/XOR for 20-GHz technology. addition, to generalize the comparison, two different technologies were also taken into consideration, BiCMOS whose n-p-n bipolar transistor has a transition frequency equal to 6 GHz, and a high-speed bipolar technology whose NPN transistor has a transition frequency of 20 GHz. The circuits have a 5-V power supply and a 250-mV logic swing for one branch (i.e., mv) which, for the XOR gate, determines the junction capacitances given in Tables I and II for the 6-GHz and 20-GHz technology, respectively. Tables I and II also include the minimum and maximum direct voltages across the junction, the built-in potential, the grading coefficient, the zero-bias capacitance, and the resulting. Other useful technological parameters are included in Table III. The simple model and simulated propagation delay of XOR versus the bias current whose load capacitance is equal to 0, 100 ff, and 1 pf, is plotted in Figs. 3 and 4 for the 6-GHz and 20-GHz technology respectively. The error for the two technologies lying outside the high-level injection region (i.e., ma and ma for the 6-GHz and 20-GHz technology, respectively) is plotted in Figs. 5 and 6. It has a worst-case error always lower than 15%, and decreases by Fig. 5. Error versus bias current I for MUX/XOR simple model for 6-GHz technology. increasing the load capacitance because tends to dominate over the parasitic capacitances. The accurate model parameters are summarized in Table IV for both technologies. The error found, plotted in Figs. 7 and 8, is limited. Indeed, it is always lower than 5% and is typically about 2%. D. Models Extension to D-FF The only difference between the MUX/XOR gate and the D-FF is due to the different load at the output nodes. Indeed, transistors Q5 and Q6, which are connected in a positive

5 456 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 47, NO. 5, MAY 2000 Fig. 6. Error versus bias current I for MUX/XOR simple model for 20-GHz technology. TABLE IV ACCURATE MODEL PARAMETERS Fig. 9. D-FF. of the differential stage evaluated in Appendix I. Hence, the simple model of propagation delay is that of MUX/XOR in (5) by substituting with equal to Since the loading effects of Q5 and Q6 are estimated in an approximated manner, the accurate model is obtained from the one developed for the MUX/XOR after adding a further term which accurately takes into account the effect of the different load. In particular, we use load instead of, defined as (10) where the unknown capacitance is found by minimizing the functional (9) Fig. 7. Error versus bias current I for MUX/XOR accurate model for 6-GHz technology. (11) Fig. 8. Error versus bias current I for MUX/XOR accurate model for 20-GHz technology. feedback loop, load the output nodes with their equivalent input capacitance (Fig. 9). Neglecting the feedback loop, the added equivalent capacitance can be approximated to that E. D-FF Model Validation We compared the analytical results of both the simple and accurate model with respect to the SPICE simulations of a CML D-FF by working under the same conditions described in Section II-C. The parameters reported in Tables I and II still hold. The only parameter which has to be modified in those tables is the coefficients of, which are equal to and for the 6-GHz and 20-GHz technology, respectively. The simple model and simulated propagation delay of D-FF versus the bias current whose load capacitance is equal to 0, 100 ff, and 1 pf, is plotted in Figs. 10 and 11 for the 6-GHz and 20-GHz technology, respectively. The error outside the high-level injection region, plotted in Figs. 12 and 13, is always lower than 20%, and like for the MUX/XOR, decreases after the load capacitance is increased. The accurate model parameters are summarized in Table IV for both technologies. The error found, plotted in Figs. 14 and

6 ALIOTO AND PALUMBO: CURRENT MODE MUX/XOR AND D FLIP-FLOP 457 Fig. 10. Analytical and simulated delay versus bias current I of D-FF for 6-GHz technology. Fig. 13. Error versus bias current I for 20-GHz technology. Fig. 11. Analytical and simulated delay versus bias current I of D-FF for 20-GHz technology. Fig. 14. Error versus bias current I for 6-GHz technology. Fig. 12. Error versus bias current I for 6-GHz technology. 15, is always lower than 5%, and is typically about 2%. Thus, the same accuracy as the MUX/XOR is achieved. III. XOR AND D-FF OPTIMIZED DESIGN Let us consider the models derived from the XOR and D-FF. Since the swing of a branch (i.e., half the swing of the gate) is equal to, and neglecting with respect to 1, both propagation delay relationships for the simple, or for the accurate case, can be written (12) Fig. 15. Error versus bias current I for 20-GHz technology. which can be optimized in terms of the bias current. Deriving (12) for and setting the result to zero, the minimum propagation delay is achieved by setting the bias current to (13) and results equal to (14) Representing with the ratio between the propagation delay and its optimum value (i.e., ),

7 458 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 47, NO. 5, MAY 2000 Fig. 17. Equivalent circuit for evaluation of a gate input capacitance. Fig. 16. Normalized propagation delay versus normalized bias current. we get (15) where the parameter, is the bias current normalized to. It is worth noting that although approximation does not derive from an intrinsic property of the relationship, it holds for all practical cases as shown in the following subsections. The expression of is independent of the circuit and process parameters, and inspection of its behavior, shown in Fig. 16, shows that a reduction in the bias current around its optimum value (i.e., lower than 1) only determines a small increase in the resulting propagation delay (a gives a ). A good tradeoff between power and speed is achieved by setting (i.e., a bias current equal to 60% of the optimum value), which determines a propagation delay only 10% worse than the optimum value. A. XOR Design As shown in the above section, the simple model is sufficiently accurate to be used during pencil and paper design. Hence, from (5), parameter and become (16c) From (16), the optimum bias current for the XOR is shown in (17), found at the bottom of the page. The optimum value of current for a negligible load capacitance is more than twice as high than a simple CML inverter [36], but tends to its value with increasing load capacitance. Exactly the same consideration can be made for the optimum propagation delay which tends to that of a simple CML inverter with increasing load capacitance. Indeed, parameter in both inverter and XOR is the same. B. D-FF Design The only difference between XOR and D-FF is in parameter, which in this case is (16a) (16b) (18) and hence, the optimum value of current results as in (19), found at the bottom of the next page.it is clear that, for negligible load capacitances, the increased load due to transistors Q5 and Q6 leads an optimum bias current and propagation delay worse than those found for XOR and the inverter gates. However, once again, the difference is strongly reduced for load conditions in which the load capacitance is dominant. (17)

8 ALIOTO AND PALUMBO: CURRENT MODE MUX/XOR AND D FLIP-FLOP 459 C. Non-Unitary Area Design Design optimization can be also performed by properly increasing the transistor area which also determines an increased value of the optimum bias current (i.e., increased power consumption) [36]. Moreover, the increase in area from the unitary value, according to the results given in Appendix I, leads to a proportional increase in the input capacitance of the CML gate, which slows down the response of the previous gate. As a consequence, this procedure is not very efficient. However, an increase in transistor area can be useful when the optimum current for the unitary case (1) gives a nonnegligible high-injection level which reduces the transistor s performance. For this end, we designed the transistor area to avoid high-injection effects. D. Design Examples To illustrate the proposed procedure in detail, XOR and D-FF with both the 6- and the 20-GHz technologies, assuming the fan-out to be equal to 1 and 10, were designed. The gates were powered with 5 V and had mv, thus Tables I III could be used. According to Appendix I, for the 6-GHz technology, the two load conditions are equivalent to a 120-fF and 1.2-pF load capacitance. The optimum bias currents are 1 and 1.9 ma, which leads to a propagation delay of 243 and 338 ps. The values are very close to those given by SPICE simulations, which are 234 and 351 ps. For a fan-out of 10, the current is slightly higher than 1.4 ma; therefore, the transistors work marginally at the high-injection level, but there is no appreciable degradation in the propagation delay. With the 20-GHz technology, the two fan-out conditions are equivalent to a 100-fF and 1-pF load capacitance. The optimum bias currents are 4.8 and 10 ma, which lead to a high power dissipation and are significantly greater than the high-injection level. Hence, we can use the 40% optimum bias current which gives 2.8 and 6 ma for a fan-out of 1 and 10, respectively. In the former case, we can still use a minimum size transistor and the resulting propagation delay is 45 ps, which has an error of 15% with respect to the value given by (5). In the second case, the bias current is excessively higher than the high-injection level and we have to use a transistor with an area three times the minimum size. Under this condition, we get a propagation delay of 69 ps, which shows an error of 13% with respect to the theoretical value. To simply evaluate the propagation delay for gates with a nonunitary size, the relationship in Appendix II can be used. IV. CONCLUSION In this paper, both models and design strategies for MUX/XOR and D-FF CML are given. The simple models, which show typical errors lower than 20%, are suitable for pencil-and-paper design. The accurate models, which have typical errors of 2%, can be used in simulators to evaluate the time behavior of complex systems. It is worth noting that simple model accuracy improves by increasing the load capacitance. Both simple and accurate models have a small number of terms compared to those proposed in the literature. Moreover, the terms used are strongly related to the circuit, and hence, the process parameter. The main difference between the accurate and the simple models is that the former need SPICE simulations to properly evaluate model parameters, although the few simulations required are much fewer than those used with the traditional sensitivity approach. Using the simple models proposed, an optimized design procedure has been presented. The design strategies allow us to set the bias current which gives the best propagation delay. The strategy also demonstrates that by reducing the power dissipation by 40%, we only loose 10% of the speed. Moreover, we show that simple model accuracy is sufficient to allow a pencil and paper design. From the investigation, we find that D-FF has an optimum bias current and a resulting optimum propagation delay higher than the XOR, but this difference tends to be negligible when the load capacitance is higher than the gate parasitic capacitances (i.e., increasing the fan-out). APPENDIX I EVALUATION OF THE INPUT CAPACITANCE OF THE CURRENT-MODE GATE By inspection of the small-signal model of a CML inverter [35], [36], neglecting the parasitic resistance, and applying the Miller theorem on the intrinsic and extrinsic base collector capacitance, the input impedance can be represented with the linear circuit in Fig. 17. The worst case arises when the capacitance in parallel with the resistance is shortcircuited. Thus, the equivalent input capacitance of a CML and ECL gate can be assumed to be (a1.1) Relationship (a1.1) gives a value of 138 and 109 ff for the 6- and 20-GHz technologies, respectively. By simulation, we found that a capacitive load equivalent to a CML or ECL load is 120 and 100 ff for the 6- and 20-GHz technologies respectively, leading to an error lower than 15%. APPENDIX II PROPAGATION DELAY FOR NON-UNITARY AREA Let us consider the transistors made up of unitary transistors, and assuming the resistances, and, and capaci- (19)

9 460 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 47, NO. 5, MAY 2000 tances, and to be those of the unitary transistor, relationship (12) can be rewritten as where and are ACKNOWLEDGMENT (a2.1) (a2.2) (a2.3) The authors would like to thank ST Microelectronics and, in particular, Prof. G. Ferla for having allowed them to use the SPICE model of HSB2 Technology. REFERENCES [1] H. Rein, Design consideration for very-high-speed Si-bipolar IC s operating up to 50 Gb/s, IEEE J. Solid-State Circuits, vol. 31, pp , Aug [2] C. Maier et al., A 533-MHz BiCMOS superscalar RISC microprocessor, IEEE J. Solid-State Circuits, vol. 33, pp , Nov [3] K. Koike et al., High-speed low-power bipolar standard cell design methodology for Gbit/s signal processing, IEEE J. Solid-State Circuits, vol. 33, pp , Oct [4] Y. Akazawa et al., Low power 1 GHz frequency synthesizer LSI s, IEEE J. Solid-State Circuits, vol. SC-18, pp , Feb [5] N. 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I, vol. 46, pp , Nov [37] T. Wakimoto and Y. Akazawa, A low-power wide-band amplifier using a new parasitic capacitance compensation technique, IEEE J. Solid- State Circuits, vol. 25, pp , Feb [38] W. Bell and J. Choma Jr., Charge-neutralized differential amplifier, Int. J. Anal. Integr. Circuits Signal Processing, pp , [39] J. Rabaey, Digital Integrated Circuits (A Design Perspective). Englewood Cliffs, NJ: Prentice-Hall, [40] B. Cochrun and A. Grabel, A method for the determination of the transfer function of electronic circuits, IEEE Trans. Circuit Theory, vol. CT-20, pp , Jan [41] J. Millman and A. Grabel, Microelectronics, 2nd ed. New York: Mc- Graw-Hill, [42] P. Gray and R. Meyer, Analysis and Design of Analog Integrated Circuits, 3rd ed. New York: Wiley, Massimo Alioto was born in Brescia, Italy, in He received the Laurea degree in electronics engineering from the University of Catania, Catania, Italy, in 1997, and is currently working toward the Ph.D. degree. His primary research interest are bipolar and CMOS high-performance digital circuits in terms of high speed or low power dissipation.

10 ALIOTO AND PALUMBO: CURRENT MODE MUX/XOR AND D FLIP-FLOP 461 Gaetano Palumbo (M 91 SM 98) was born in Catania, Italy, in He received the Laurea degree in electrical engineering in 1993 and the Ph.D. degree in 1988 from the University of Catania, Catania, Italy. Since 1987, he has been with the Institute of Electrical and Electronic Systems, University of Catania. In 1989, he was awarded a grant by AEI of Catania. In 1993, he taught a course on electronic devices, and now teaches courses on electronics and electronics for digital systems. In 1994, he joined the Department of Electrical Electronics and System (DEES) as a Researcher, where he is now a Professor. His primary research interests have included analog circuits, with particular emphasis on feedback circuits, compensation techniques, current-mode approach, and low-voltage circuits. Recently, his research involves digital circuits with emphasis on high-performance digital circuits. In these fields, he is developing research activities in collaboration with ST Microelectronics, Catania, Italy. He is co-author of the book CMOS Current-Mode Amplifier (Norwell, MA: Kluwer, 1999) and is author or co-author of more than 120 scientific papers in referred international journals and conferences. Dr. Palumbo is presently an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: FUNDAMENTAL THEORY AND APPLICATIONS.