ENERGY consumption is one of the most important parameters

Transcription

1 1094 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 12, NO. 10, OCTOBER 2004 Evaluation of Energy Consumption in RC Ladder Circuits Driven by a Ramp Input Massimo Alioto, Member, IEEE, Gaetano Palumbo, Senior Member, IEEE, and Massimo Poli Abstract In this paper, the energy consumption of RC ladder networks, which can represent chains of transmission gate or long wire interconnections, is modeled. Their energy dependence on the input rise time is analyzed by assuming a ramp input waveform. Since the analysis can be carried out in a straightforward manner only for very simple RC ladder networks, the exact analysis is first limited to asymptotic values of the input rise time (i.e., for 0 and ). Successively, the energy expression is extended to arbitrary values of the input rise time by introducing a suitable equivalent first-order RC circuit, whose resistance and capacitance are simply related to the resistances and capacitances of the original network. The energy expression found is useful for pencil-andpaper evaluation and affords an intuitive understanding of the network dissipation, since each term has an evident physical meaning. By comparison with SPICE simulations, the energy expression proposed is showed to be accurate enough for modeling purposes. Index Terms Energy consumption, modeling, power dissipation, chain, ladder circuits, TG chain, very large scale integration (VLSI). I. INTRODUCTION ENERGY consumption is one of the most important parameters when designing integrated circuits. Indeed, it has a great impact on the battery lifetime in portable systems and on heat generation in high-performance circuits. For this reason, estimating the energy consumption of the blocks used acquires fundamental importance in the design. Indeed, the designer usually has to choose among different design options by resorting to intuitive understanding or by calculating the approximate dependence of the energy on design parameters. In addition, energy estimation is essential for CAD tools that synthesize logic blocks and their interconnections to meet energy, speed or area constraints [1] [3]. To evaluate energy consumption, and avoid computationally expensive circuit simulations, it is highly desirable to rely on simple and relatively accurate analytical expressions of the energy dissipated by these blocks. Of the blocks used in digital ICs, energy modeling of static or dynamic CMOS gates has been extensively investigated starting from simple capacitance charge models [2] [5] to more accurate analyses which include short-circuit power consumption [6] [9] and leakage current [10]. However, these models cannot be applied to blocks such as adiabatic logic gates [11], [12], Manuscript received April 18, 2003; revised December 15, M. Alioto is with the Dipartimento di Ingegneria dell Informazione (DII), Università di Siena, Siena, Italy ( malioto@dii.unisi.it). G. Palumbo and M. Poli are with the Dipartimento di Ingegneria Elettrica Elettronica e dei Sistemi (DIEES), Università di Catania, Catania, Italy ( gpalumbo@diees.unict.it; mpoli@diees.unict.it. Digital Object Identifier /TVLSI logic gates based on transmission-gates or pass-transistors, and long interconnections [13] [15], since they are accurately modeled by an RC ladder network with grounded capacitances (see Fig. 1). Until now, very little attention has been dedicated to estimating the energy consumption of circuits which can be modeled as RC networks, unless for adiabatic gates that were analyzed in the specific case of a very slow power clock (i.e., a very slow input signal at the input of the RC chain) [16] [18], but the results are not easy to be generalized to faster waveforms. Rather, it would be useful to evaluate the energy consumption for arbitrary waveforms, to fully understand and exploit the tradeoffs involved in the design of adiabatic circuits. This would be especially useful in gates that can operate both in standard static or adiabatic mode, where it is crucial to evaluate the energy reduction offered by the latter mode compared to the former to efficiently manage power saving techniques [19]. Regarding interconnects and circuits based on transmission-gates/pass-transistors, they are usually driven by a driver (i.e., a static logic gate), and the overall energy dissipated by the driver and the equivalent RC network is equal to, where capacitance is the sum of the parasitic capacitance of the driver and the total capacitance of the RC network [20]. However, it is of interest to separately evaluate the energy contributions of the driver and that of the RC network, as discussed in [21], where energy dissipated by each resistor is evaluated only in the specific case of a step input by resorting to model-order reduction. In this paper, the estimation and modeling of the energy dissipation in an RC ladder network are analytically addressed. The effect of the input signal rise time on energy is analyzed by assuming a ramp input waveform, as in the previous literature dealing with the timing behavior of RC circuits [22] [29]. More specifically, simple energy expressions are derived for asymptotical values of the input rise time from the exact expression of energy dissipated during an input transition. By using the results for the two asymptotic cases, the RC network is modeled with a first-order RC circuit which is simply related to the resistances and capacitances of the original network, and this model is justified and validated for intermediate values of rise time. The strategy followed greatly simplifies energy expression, that lends itself to an immediate circuit interpretation and allows the principal contributions to the overall energy of the network to be detected. As a result, the proposed model helps the designer to develop an intuitive understanding of the network dissipation. To test the validity of the model proposed, it is extensively compared to SPICE simulations, and examples dealing with transmission-gates and their modeling are also discussed /04$ IEEE

2 ALIOTO et al.: EVALUATION OF ENERGY CONSUMPTION IN RC LADDER CIRCUITS DRIVEN BY A RAMP INPUT 1095 Fig. 1. nth-order RC ladder circuit. Fig. 2. Ramp input waveform. The general analysis of the energy consumption of RC ladder networks will be analytically dealt with in Section II. In Section III, the general expression will be simplified by considering asymptotic values of the input rise time, and successively extended to generic values by introducing an equivalent first-order RC circuit in Section IV, where a practical example will be introduced. In Section V, the model will be validated by comparison with simulations, and its accuracy in the alternative case of an exponential input waveform is also analyzed. In Section VI, comments will be passed on alternative approaches for evaluating the equivalent first-order circuit, and a simple circuit interpretation of the model will be provided. Finally, in Section VII the conclusions will be reported. To improve the readability of this paper, tedious calculations will be reported as Appendices. II. GENERAL ANALYSIS OF THE ENERGY DISSIPATED BY RC LADDER CIRCUITS Let us consider the th order RC ladder circuit in Fig. 1, made up of resistances and grounded capacitances with. Assume the circuit to be driven by a voltage source,, with a ramp input waveform switching from zero to its amplitude,, with a rise time as depicted in Fig. 2. During this input transition, the voltage source supplies the network with an energy, that is equal (1) to the sum of the energy stored in capacitances the steady state,, given by ( is the circuit overall capacitance) and energy dissipated by resistors. Hence, the expression of the energy dissipated by resistors,, can be obtained by evaluating energy as the integral of the product of the input voltage,, and the input current,, then subtracting the energy stored in the capacitances The input current waveform,, depends on the network s characteristics and can be evaluated via the input admittance of the network,.inrc circuits, input admittance poles and zeroes are real, negative, and alternately placed on the frequency axis, with the first zero being placed at the origin [31]. Analytically, can be written as [30], [31] where and are the time constants associated with the poles and the zeroes of the circuit admittance (i.e., their values are obtained as the negative reciprocal). Moreover, let us assume the time constants are ordered such that at (2) (3) (4)

3 1096 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 12, NO. 10, OCTOBER 2004 Fig. 3. Plot of function f in (9) and its approximation in (10). Fig. 4. Error of (10) with respect to (9). and. Applying partial fraction expansion of the rational function in (4), results in (5) Relationship (5) allows to find the input current waveform,, which can be derived by applying the inverse Laplace transform to. Thus, after some simple calculations developed in Appendix I, the resulting energy dissipated by resistors,, is given by where coefficients can be found by equating relationship (5) to (4), and the following property holds where function is defined as (8) (6) (9) Indeed, equating (4) and (5) we get and is plotted versus function is in Fig. 3. A simple approximation of where the constant term of the left-hand side (equal to unity) must be equal to that of the right-hand side. (7) (10) which is plotted by the dashed line in Fig. 3. The error of relationship (10) with respect to (9), plotted in Fig. 4, is always negative with a magnitude lower than 12%.

4 ALIOTO et al.: EVALUATION OF ENERGY CONSUMPTION IN RC LADDER CIRCUITS DRIVEN BY A RAMP INPUT 1097 Exact evaluation of the energy dissipated by the network by means of relationship (8) requires knowing the expressions of all the poles and zeros (i.e., poles and coefficients ). However, the analytical evaluation of poles and zeroes can be simply found only for very simple networks, such as first- and secondorder circuits (even for the second-order circuits the resulting expression shown in Appendix II is not so simple). Hence, in general, it is not possible to analytically derive the energy dissipation of an RC ladder network, and some approximation must be introduced to ensure the problem is analytically tractable. III. ENERGY EXPRESSION FOR ASYMPTOTIC VALUES OF THE RISE TIME Fig. 5. Typical pole-zero map of the input admittance of an RC circuit. The expression of dissipated energy (8) can be simplified for asymptotical values of rise time (i.e., for and ). Indeed, as demonstrated in the following, in these cases the energy dissipated by the RC circuit can be expressed as a function of only and, thereby avoiding the problem of evaluating network poles and zeroes. Function tends to for. Hence, remembering (6), for relationship (8) becomes (11) It is apparent that the energy dissipated is equal to that of a first-order RC circuit, with capacitance, driven by a step input. For high values of, function is well approximated by. Therefore, for high values of, the energy dissipated (8) turns out to be inversely proportional to the rise time,, and is approximately given by (12) where the term, derived in Appendix III, is expressed as a function of resistances and capacitances only. Relationship (12) is equivalent to the results obtained in [16] [18] (where a single-pole approximation was adopted). IV. GENERAL ENERGY MODELING: FIRST ORDER RC EQUIVALENCE An equivalent first-order RC circuit can be used to model the asymptotic behavior of the original network. Indeed, to match the energy dissipation for its capacitance must be equal to, while for a suitable equivalent time constant,, has to be introduced (in Section VI, we will show that the often used Elmore approximation [22], [23] is inadequate). The expression of can be achieved by equating energy (8), evaluated with and capacitance, to (12), leading to (13) where is the total capacitance to the right of resistance. Even though the first-order equivalent RC circuit was built to match energy dissipation for and, it can also be approximately extended to arbitrary rise time values. This is because the single-pole approximation holds even for intermediate values of, as intuition would suggest. Such an approximation can be justified by considering that the pole-zero map of the th order RC network admittance,, consists of poles and zeroes, that are alternately placed in the frequency axis, as shown in Fig. 5. When the poles are very distant, the dominant-pole approximation trivially holds, while in cases where two poles are close, and hence the dominant-pole condition does not hold, the zero which is in-between also tends to be close to them, nulling the effect of one of the two poles. This suggests that, even when poles are not distant from each other, their overall effect can be represented by a single pole 1. The energy of the equivalent first-order RC circuit discussed above as a function of the input rise time,, is simply achieved from (8) by setting (14) and using relationship (13) to evaluate the equivalent time constant,. It is worth noting that relationship (14) does not explicitly depend on poles and zeroes but only on the resistances and capacitances of the network considered, as is desired. 1 This contrasts with the case of delay evaluation, where the single-pole assumption may lead to very inaccurate results [34]. The different results are justified when we realize that the voltage transfer functions considered in the delay evaluation no longer satisfy the condition that there will always be a zero between two consecutive poles.

5 1098 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 12, NO. 10, OCTOBER 2004 Fig. 6. Circuit example. with (10), relationship (14) sim- Approximating function plifies into TABLE I NUMERICAL VALUES OF R AND C (15) which is simple enough for pencil-and-paper calculations. From (15), simple criteria can be found to establish when asymptotical expressions of energy can be applied instead of exact energy. It is clear that the rise time effect can be neglected (i.e., a step input can be assumed) when rise time,, is much lower than (for example, in the case of a logic gate based on transmission gates driven by a fast static logic gate). In particular, a lower than 10% error compared to (15) can be achieved for. Moreover, energy becomes inversely proportional to when it is much greater than (as in the case of adiabatic circuits, which are driven by a slow ramp waveform), whilst a lower than 10% error is obtained for. For the sake of clarity, let us apply the model strategy discussed above to a practical example. To this end, consider the 10th-order RC circuit in Fig. 6, whose resistances and capacitances are given in Table I. From (13), the equivalent time constant of the network considered is equal to s. The resulting energy consumption normalized to that obtained for the step input is plotted versus in Fig. 7, where the results predicted by (14) and (15) are also reported. The error produced by (14) and (15) with respect to the exact energy evaluation is plotted versus in Fig. 8. Inspection of this figure reveals the magnitude of the maximum error in (14) and (15) to be equal to 16% and 8%, respectively. V. MODEL VALIDATION To test the accuracy of the model (14) (15) based on a first-order equivalence, many RC ladder circuits with an order ranging from 2 to 10 were simulated. To be more specific, more than RC networks were randomly generated and analyzed by applying a ramp input whose rise time ranged from four orders of magnitude lower to four orders higher than the equivalent time constant. Some of the curves obtained are reported in Fig. 9, where the energy normalized to that obtained for a step input is plotted versus. The maximum error of (14) with respect to the simulations performed, plotted versus in Fig. 10, tends to zero both for and, as was expected. By inspection of Fig. 10, the error of (14) is always lower than 25%, while the average error of (14) versus is always lower than 8%, as can be deduced from Fig. 11. This means that model (14) is accurate enough for modeling purposes, providing results which are close to the real ones in typical cases. It is worth noting that the energy dissipation model (14) always overestimates the energy consumption of the original network. Simplified expression (15) was also tested by comparison with simulation results. The error and its average value versus are plotted in Figs. 12 and 13, which show that relationship (15) always approximates the exact energy consumption within 15%, and typically within 8%. Even though results presented above are derived under the assumption of a ramp input waveform, in general arguments about the pole-zero map in Section IV lead to a first-order model regardless of the specific input waveform applied. Therefore, an analogous accuracy is expected for other input waveforms, among which the most significant one in current deep-submicron technologies is the exponential one. Accordingly, the model was tested by applying an exponential input, having a time constant ranging from four orders of magnitude lower to four orders higher than the network time constant. As already done for the ramp input, predicted results were obtained by simply evaluating the energy consumption of a first-order RC circuit having an equivalent time constant. To evaluate the model accuracy, the dissipated energy was evaluated by performing simulations of RC ladder networks with an order ranging from 2 to 10 under the same conditions as before. Results obtained are analogous to (or even better than) those presented for the ramp input, and thus are not plotted for the sake of brevity. To be more specific, the maximum error and its average value result to be close to (or lower than) those found for the ramp input waveform, thus confirming the validity of the model proposed. The previous results hold for RC networks with linear resistances and capacitances. For the sake of completeness, let us consider the case of cascaded transmission gates, which are nonlinear in a strict sense, but exhibit an almost linear behavior in practical cases [20]. Obviously, energy evaluation will be affected by both approximations introduced in the modeling approach proposed and inaccuracy in evaluating equivalent linear parameters. To be more specific, let us consider the transmission gate model in Fig. 14. A straightforward manner to evaluate is to consider a transmission gate driven by a step input and loaded by a large capacitance (i.e.,, which has a delay equal to,

6 ALIOTO et al.: EVALUATION OF ENERGY CONSUMPTION IN RC LADDER CIRCUITS DRIVEN BY A RAMP INPUT 1099 Fig. 7. Plot of normalized energy (8) (solid line), (14) (dotted line), and (15) (dashed line) dissipated by the circuit in Fig. 6 versus T=. Fig. 8. Error of (14) (dotted line), and (15) (dashed line), with respect to (8) versus T= for the circuit in Fig. 6. thus, results in (being the simulated delay) [11], [18], [20]. Analogously, is evaluated by simulating a transmission gate with a zero load capacitance, whose delay is equal to, therefore results as. In particular, for a m CMOS process whose main parameters are reported in Table II, a transmission gate with a minimum-sized NMOS and a symmetrically sized PMOS (larger than the NMOS transistor by a factor 3.6) has k and ff. To evaluate the error of the energy model in circuits based on transmission gates, let us consider a chain of 5 and 10 transmission gates. The resulting energy normalized to (11) versus is plotted in Fig. 15 by assuming that the chain drives a load capacitance equal to 1 pf. Error with respect to simulations is reported in Fig. 16 for ranging from to 100, which is a wide range compared to practical values. By inspection of this figure, error is always lower than 20% and is typically lower (the increase in error for very high values of is due to the energy consumption associated with the leakage currents of transistors). It is worth noting that an even lower error was found for smaller load capacitances. VI. REMARKS A. Comments on the Strategy Adopted In Section IV an equivalent RC circuit was derived to model the energy consumption of an RC ladder network. In particular, the RC circuit time constant was obtained through the asymptotic relationship (12). At a first glance, alternative strategies based on a simpler time constant equivalence (i.e., using the Elmore delay approximation) or a simple approximate procedure (described below) to evaluate energy consumption could have been used. However, as shown in the following, even if the two strategies give an upper and a lower energy bound, they also produce an unacceptable error. We can approximate the time constant of an RC ladder network with the well-known Elmore delay [22], [23] (16)

7 1100 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 12, NO. 10, OCTOBER 2004 Fig. 9. Some simulation results of energy normalized to E versus T=. Fig. 10. Error of (14) with respect to simulations versus T=. that can be substituted into (14). For this results in (17) Simple analytical comparison shows that (17) is greater than (12), and thus represents an upper energy dissipation bound 2 for 2 Actually, the energy consumption of a first-order RC circuit with a time constant equal to constitutes an upper bound for all values of T. Indeed, if we observe that the Elmore delay is equal to coefficient a = of the term proportional to s in the denominator of (4), and function f(x) decreases as x increases, (8) can be upper-bounded by setting =. By using (6) and noting that >, this property is thereby demonstrated.. However, the error of (17) with respect to (12) can be arbitrarily high since their ratio (18) is unbounded. For example, for a second-order network, relationship (18) is maximized by setting equal to (19)

8 ALIOTO et al.: EVALUATION OF ENERGY CONSUMPTION IN RC LADDER CIRCUITS DRIVEN BY A RAMP INPUT 1101 Fig. 11. Average error of (14) with respect to simulations versus T=. Fig. 12. Error of (15) with respect to simulations versus T=. By substituting (19) and assuming in (18), we obtain the unbounded function of the ratio shown in Fig. 17. It apparent that the error on the energy consumption can be arbitrarily high, so that the approach lacks practical usefulness. By following a procedure analogous to the Elmore delay to approximate the network time constant, we may evaluate the energy of the RC ladder network by approximating it with the sum of the energy due to each capacitance at a time, thus obtaining Since the squared sum of the terms is always higher than the sum of the squared terms, relationship (20) is a lower bound for exact energy (12). Moreover, if we consider the ratio of (12) and (20) (21) the value found becomes unacceptably high. Indeed, as an example, consider a second-order RC network, for which (21) can be maximized by setting equal to (20) (22)

9 1102 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 12, NO. 10, OCTOBER 2004 Fig. 13. Average error of (15) with respect to simulations versus T=. TABLE II MAIN PARAMETERS OF THE CMOS PROCESS ADOPTED by referring to resistances and capacitances. Indeed, for fast inputs, the energy dissipated (11) is independent of resistors, and is proportional to the sum of capacitances. Instead, for slow inputs, from (12) the main energy contributions are associated with terms having a high value. This occurs when, proceeding from the input to the output node, a high resistance,, is followed by capacitances which are greater than the preceding ones. In other words, assuming capacitances are of the same order of magnitude, the main contributions are due to high resistances. Instead, if we assume resistances of the same order of magnitude, the main contributions are due to resistances which are followed by high capacitances. Fig. 14. Linear model of the transmission gate. that, substituted in (21), leads to the plot versus reported in Fig. 18. It is apparent that the ratio (21) can be as high as 2 even in the simple case of a second-order RC ladder. Consequently (20) is not suitable for approximating (12). An intuitive explanation that clarifies why the proposed equivalent model is more accurate than the others is obtained considering the energy dissipated in each resistor,. It can be written (23) where represents the current flowing through the resistor which is proportional to the charged capacitive load. Hence,, and are proportional to and, respectively, which is in accordance with the developed model. B. Main Contributions to Energy Consumption It is also possible to find what the main contributions to overall energy are (which could be useful during design), VII. CONCLUSION In this paper, an analytical energy dissipation model for RC ladder networks was proposed. The dependence of energy dissipation on input rise time was analyzed assuming a ramp input waveform. Since the exact analysis can be carried out easily only for very simple RC ladder networks, it was first performed only for asymptotic values of the input rise time (i.e., for and ). Successively, the energy expression was extended to generic values of the input rise time from circuit considerations, by introducing a suitable equivalent first-order RC circuit, whose resistance and capacitance are simply related to the resistances and capacitances of the original network. The same subject was partially addressed in two previous papers, the first of which deals with energy estimation in RC networks driven by a very slow waveform [17], and its results are matched by those of this paper for high values of input rise time. The second paper [21], which is based on model-order reduction, deals with RC networks driven by a step input waveform and allows to evaluate the energy contribution associated with each resistor. This strategy has a good accuracy, but its

10 ALIOTO et al.: EVALUATION OF ENERGY CONSUMPTION IN RC LADDER CIRCUITS DRIVEN BY A RAMP INPUT 1103 Fig. 15. Normalized energy versus T= in a chain of 5 and 10 transmission gates. Fig. 16. Error of the energy model in a chain of 5 and 10 transmission gates with respect to simulations versus T=. Fig. 17. Plot of (18) with n =2under relationship (19). application to circuits having typical complexity is tedious, and hence it is not well suited neither for pencil-and-paper calculations nor for developing an intuitive understanding of the circuit. On the contrary, the strategy developed in this paper allows the overall energy dissipated to be simply evaluated for arbitrary values of input rise time, and also provides explicit energy contributions of resistors for high rise time values. Results obtained are useful to fully understand and exploit the tradeoffs involved

11 1104 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 12, NO. 10, OCTOBER 2004 Fig. 18. Plot of (21) with n =2under relationship (22). in the design of adiabatic gates, where input rise time is intentionally slowed to save energy, as well as to evaluate energy contribution of RC networks that schematize RC interconnects or circuit based on transmission-gates/pass-transistors separately from the contribution of the driver. Alternative strategies to model the time constant of the equivalent first-order RC circuit were also analyzed. Among them, the Elmore delay was demonstrated to be an upper bound for energy and often very inaccurate for estimation, as found previously in the literature regarding propagation delay evaluation [25], [29], [34]. The results obtained with both the first-order approximation and its simplification were then compared to extensive SPICE simulations. Analysis shows that both the models proposed are in good agreement with simulated results, since their maximum error is lower than 25% and 15%, respectively, and their average error is lower than 8%. Analogous results were obtained in the alternative case of an exponential input waveform, which often occurs in current deep-submicron technologies. For the sake of completeness, some examples were also provided by applying the modeling strategy proposed to circuits based on transmission-gates, where accuracy of energy estimation results to be adequate even being affected by RC modeling of transistors. APPENDIX I (A1.1) where is the Heaviside step function. After substituting (A1.1) into (3), we obtain the following general expression of the energy dissipated by resistors in the network (A1.2) Relationship (A1.2) can be written in the more compact form represented by relationship (8) together with (9). APPENDIX II Let us consider a second-order RC ladder circuit. From circuit analysis, the input admittance expression is (A2.1) In Section II, the input current waveform,, can be evaluated by using (5) and applying the inverse Laplace transform to, that results in where (A2.2) (A2.3) (A2.4) where we defined in (A2.5), shown at the bottom of the next page.)

12 ALIOTO et al.: EVALUATION OF ENERGY CONSUMPTION IN RC LADDER CIRCUITS DRIVEN BY A RAMP INPUT 1105 Thus, expressing polynomials and as (A3.3) from (A3.2) we get Fig. 19. Equivalent circuit in Appendix III. (A3.4) By writing relationship (A2.1) in the form (5) and equating the two expressions, the coefficients are found to be (A2.6) B. Demonstration of Property (12) Consider the input admittance in (5), that can be expressed in the rational form (A3.5) (A2.7) from which energy consumption of a second-order RC ladder network can be evaluated. (note that coefficient is equal to zero). Equating (5) to (A3.5), and observing that the terms proportional to in the numerator (i.e., and, respectively) must be equal, we get APPENDIX III A. Property of Input Admittance in Its Rational Form Consider the input admittance of the generic network in Fig. 19, where the equivalent impedance, that represents the network following resistor, can be written as the ratio of polynomials and. In general, the order of numerator is lower or equal to order of denominator. The input admittance in its rational form is (A3.6) In relationship (A3.6), coefficients and can be evaluated by means of relationship (A3.4), observing that, from the timeconstant method [32], [33] coefficients and result in (A3.1) (A3.7a) where the order of polynomials and is equal to (note that the order of is ). From (A3.1), it is apparent that (A3.7b) (A3.2) thus term page. is equal to (A3.8), as shown at the bottom of the (A2.5)

13 1106 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 12, NO. 10, OCTOBER 2004 Substituting relationship (A3.8) and (A3.7a) in (A3.6), the expression of results as and its equivalent representation (A3.13) (A3.9) The third term of the right-hand side of relationship (A3.10) can be rewritten by using (A3.12) on the two inner summation which, after some manipulations is given by (A3.14) then by again applying (A3.12) to the outer summation and using (A3.13) we get (A3.10) As demonstrated in the following, the second and third terms in (A3.10) have equal magnitude but an opposite sign. As a consequence, we can write that demonstrates relationship (A3.11). (A3.15) that demonstrates relationship (12), as desired. Let us resort to the following inversion rule (A3.11) (A3.12) ACKNOWLEDGMENT The authors wish to thank the reviewers for their useful comments and suggestions. REFERENCES [1] A. Chandrakasan, W. Bowhill, and F. Fox, Eds., Design of High-Performance Microprocessor Circuits. Piscataway, NJ: IEEE Press, [2] F. Najm, A survey of power estimation techniques in VLSI circuits, IEEE Trans. VLSI Syst., vol. 2, pp , Dec [3] R. Gu and M. Elmasry, Power dissipation analysis and optimization of deep submicron CMOS digital circuits, IEEE J. Solid-State Circuits, vol. 31, pp , May (A3.8)

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In 2002, he joined the Dipartimento di Ingegneria dell lnformazione (DII) of the University of Siena as an Assistant Professor. Since 2001, he has been teaching undergraduate and graduate courses on basic electronics, microelectronics and digital electronics. His primary research interests include the modeling and optimized design of bipolar and CMOS high-performance digital circuits in terms of high-speed or low-power dissipation, as well as arithmetic circuits. He has authored or co-authored more than 40 journals and conference papers. Gaetano Palumbo (M 91 SM 9S) was born in Catania, Italy, in He received the laurea degree in electrical engineering and the Ph.D. degree from the University of Catania, Catania, Italy, in 1988 and 1993, respectively. Since 1993, he conducts courses on Electronic Devices, Electronics for Digital Systems and basic Electronics. In 1994, he joined the DEES (Dipartimento Elettrico Elettronico e Sistemistico), now DIEES (Dipartimento di Ingegneria Eettrica Elettronica e dei Sistemi) at the University of Catania as a researcher, subsequently becoming Associate Professor in Since 2000, he has been a full professor in the same department. His primary research interest has been analog circuits with particular emphasis on feedback circuits, compensation techniques, current-mode approach, low-voltage circuits. In recent years, his research has also embraced digital circuits with emphasis on bipolar and MOS current-mode digital circuits, adiabatic circuits, and high-performance building blocks focused on achieving optimum speed within the constraint of low power operation. In all these fields he is developing some the research activities in collaboration with STMicroelectronics of Catania. He is coauthor of CMOS Current Amplifiers (Norwell, MA: Kluwer, 1999) and Feedback Amplifiers: Theory and Design (Norwell, MA: Kluwer, 2002). He is also a contributor to the Wiley Encyclopedia of Electrical and Electronics Engineering. In addition, he is the author or co-author of more than 200 scientific papers on international journals (over 80) and in conferences. Dr. Palumbo, served as an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART I: FUNDAMENTAL THEORY AND APPLICATIONS from 1999 to the end of Currently, he is serving as an Associated Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART I: ANALOG AND DIGITAL SIGNAL PROCESSING. In 2003, he received the Darlington Award. Massimo Poli was born in Syracusa, Italy, in He received the M.Sc. degree in electronics engineering, microelectronics specialization (summa cum laude), from the University of Catania, Catania, Italy, in 2001, and is currently working toward the Ph.D. degree in electronic and automation engineering at the same university. His primary research interests include arithmetic circuits and modeling.optimization, in terms of high-speed and low-power dissipation, of CMOS high-performance digital circuits.