IN THE LAST decade, the increasing demand for fast computation

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1 16 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 55, NO. 1, JANUARY 2008 Power-Aware Design of Nanometer MCML Tapered Buffers Massimo Alioto, Senior Member, IEEE, and Gaetano Palumbo, Fellow, IEEE Abstract A strategy to design MOS current-mode logic (MCML) tapered buffers is discussed. Closed-form expressions of the speed and the power consumption of MCML tapered buffers are first derived. Then, analytical criteria are presented to explore the power delay design space and properly size the number of stages and the current tapering factor under a speed/power constraint. These criteria incorporate deep-submicron effects and are simple enough to be used in pencil-and-paper calculations. Being general and independent of the process adopted, the proposed design strategy allows for gaining an insight into the interdependence of design parameters, technology parameters and performance. Moreover, the proposed models of the delay/power consumption under assigned constraints allow the designer to predict the achievable performance before actually carrying out the design. Results are validated by means of Spectre simulations on a 90-nm CMOS technology. Index Terms Buffer, CMOS, high speed, integrated circuit, low power, MOS current-mode logic (MCML), source-coupled logic (SCL). I. INTRODUCTION IN THE LAST decade, the increasing demand for fast computation and transmission over radio frequency (RF) and optic fiber channels has dramatically widened the range of applications where MOS current-mode logic (MCML) circuits are the preferred logic style [1] [8]. Indeed, this logic style allows for improving the speed, the power efficiency and reducing the switching noise, which are key aspects in VLSI circuits [1] [3]. In these high-speed circuits, the performance degradation associated with the heavily loaded nodes is usually counteracted by inserting tapered buffers, which are made up of cascaded buffers whose driving capability progressively increases by the tapering factor [9]. In practical designs, and are design parameters that must be found from the assigned requirements on the load capacitance, the buffer input capacitance, as well as the selected power/delay tradeoff. In this regard, maximum-speed designs are rarely feasible due to the very high power consumption that is needed [10] [12], thus actual designs are always a tradeoff between speed and power consumption [1], [2], [12] [15]. At the best of the authors knowledge, until now, no design strategy to manage the power delay tradeoff in cascaded Manuscript received March 30, 2007; revised July 5, This paper was recommended by Associate Editor V. Kursun. M. Alioto is with the Dipartimento di Ingegneria dell Informazione (DII), Università di Siena, Siena I-53100, Italy ( malioto@dii.unisi.it). G. Palumbo is with DIEES-Dipartimento di Ingegneria Elettrica Elettronica e dei Sistemi, Universitá di Catania, I Catania, Italy ( gpalumbo@diees.unict.it). Digital Object Identifier /TCSII Fig. 1. Structure of a tapered buffer. MCML gates has been proposed, although some strategies were previously elaborated to design chains with CML and emitter coupled logic (ECL) in bipolar technology [16], [17]. In this brief, for the first time a design strategy to manage the power delay tradeoff in MCML tapered buffers is presented. Analysis starts from the gate delay modeling approach previously proposed by the same authors [10], [11], which was further developed and simplified for nanometer technologies in [12]. These models allow for exploring the power delay design space, as well as to understand the mutual dependence of design parameters, technology parameters and performance. The resulting design criteria are simple enough to be used in a pencil-and-paper approach. Models to quickly estimate the achievable performance under power/delay constraints before the design are also derived. The strategy is validated via circuit simulations on a 90-nm CMOS technology. This brief is organized as follows. A preliminary analysis of MCML tapered buffers is presented in Section II, whereas their minimum-delay design is discussed in Section III. The power delay tradeoff is analyzed in Section IV, and the results are validated in Section V, where a design example is presented. Finally, conclusions are reported in Section VI. II. ANALYSIS OF MCML TAPERED BUFFERS A tapered buffer consists of cascaded buffers with increasing sizes, according to Fig. 1. In contrast to static CMOS logic, the MCML tapered buffers can be made inverting or noninverting by properly swapping the differential outputs, regardless of the number of stages. It is worth noting that a capacitive load is assumed in Fig. 1, which represents the case where a large on-chip capacitance must be driven. However, the analysis reported in the following sections can be easily extended to the case where off-chip loads must be driven. 1 A. Brief Review of MCML Buffer Modeling The topology of the generic th MCML buffer stage is reported in Fig. 2. In this figure, the nmos source-coupled pair 1 In high-speed applications, off-chip loads are modeled by transmission lines and require an impedance matching at the chip output. This is achieved by inserting an output stage with matched output resistance (e.g., 50 ), whose design is well understood [3], [4]. Due to its high input capacitance, this stage must be driven by a tapered buffer, as discussed in thisbrief /$ IEEE

2 ALIOTO AND PALUMBO: POWER-AWARE DESIGN OF NANOMETER MCML TAPERED BUFFERS 17 TABLE II MAIN TECHNOLOGY PARAMETERS (90-nm CMOS) where represents the input capacitance per input bias current, and its numerical value is reported in Table I under the conditions above discussed. Fig. 2. Topology of the ith stage (MCML buffer). B. Tapered Buffer Modeling According to Fig. 1, each buffer stage is progressively increased by a tapering factor, which defines the (constant) ratio of the load capacitance and the input capacitance of all stages TABLE I DELAY MODEL PARAMETERS FOR V = 0:7 V, A = 2:2 (90-nm TECHNOLOGY) M1 M2 steers the bias current to the drain of M1 (M2) if the differential input voltage is equal to high (low) logic level value (i.e., a voltage respectively about and ), thereby generating a high (low) output voltage equal to, being the load resistance. Accordingly, the logic swing is, which is preliminarily set along with the voltage gain around the logic threshold from considerations at the system level, in order to meet the desired noise margin requirement [11], [12]. Therefore, in the circuit design and are assigned. According to the methodology in [12] valid for nanometer technologies, the delay of the th stage under an assigned bias current can be expressed as where is the stage load capacitance, is the capacitance at the drain node of MOS transistors M1-M2 per unit bias current, and is the parasitic capacitance associated with the load resistance per unit bias current. 2 The detailed evaluation of these parameters is omitted for the sake of brevity, and is extensively addressed in [12]. The numerical values of these parameters (found according to [11], [12]) are reported in Table I, where the typical values mv and are assumed [12], and the 90-nm CMOS technology with main parameters in Table II is adopted. As shown [12], the input capacitance of the th stage seen by each input node is proportional to via constant 2 Indeed, in [12] it was shown that the overall nmos capacitance at the drain is proportional to I via constant c that depends on both V and A. Analogously, it was shown that the parasitic capacitance associated with R is proportional to 1=I via constant c that depends on V. (1) (2) for (3) Since the load capacitance of each stage is equal to the input capacitance of the successive one (i.e., ), from (2), (3) it is apparent that the bias current of the buffer stages is also progressively increased by the tapering factor, according to (4) for (4a) whereas the bias current of the first stage is found from the requirement of the input capacitance, which, from (2), leads to (4b) From (4a) and (4b), the bias current of the first stage is set by the requirement on the tapered buffer input capacitance, and the following stages currents must be progressively increased by a factor. Observe that, once the bias current of a stage is found, the transistors size and the load resistance are straightforwardly derived by following the procedure in [12]. As is well known from static CMOS tapered buffers [9], parameters and are not independent. Indeed, by observing that the last stage drives the load capacitance of the tapered buffer (i.e., ), iterative evaluation of (3) leads to, or equivalently where it was observed that the ratio represents the fan-out of the tapered buffer. From (5), the only design parameter to optimize is the tapering factor, since the number of stages is set according to (5) once is assigned. Obviously, the number of stages in (5) must be rounded to the nearest integer in practical design cases. The overall power consumption of MCML buffers is essentially static, and is equal to the product of the supply voltage and the overall bias current, thus in the following we will interchangeably refer to bias current and (5)

3 18 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 55, NO. 1, JANUARY 2008 re- power consumption. From (4), the overall bias current sults to The resulting minimum delay obtained with is easily found by substituting (9) into (8) where (i.e., the fan-out from (5)) was assumed to be much greater than unity (otherwise, no buffer is needed). From (6), the overall power consumption linearly increases as increasing the load capacitance, and obviously decreases when increasing the tapering factor. In regard to the tapered buffer delay, it is simply equal to, which from (1) results to where (2) (4) were substituted. Equation (7) can be expressed as a function of only by substituting (5) and performing some analytical manipulations, which yield 3 which depends on the design parameter, the fan-out, as well as the technology-dependent delay coefficients. III. MINIMUM-DELAY DESIGN OF MCML TAPERED BUFFERS Under a fan-out requirement and the available technology, the delay can be minimized by properly setting the tapering factor. Its optimum value is easily found by setting to zero the derivative of (8) for, which leads to the following condition which is very similar to the optimum condition that is found for static CMOS tapered buffers [9]. Indeed, assuming, (9) leads to. In practical cases, factor in (9) is different from zero, and represents the ratio of the nmos capacitance at the drain and the gate terminal, which does not depend on the bias current. It is well known that is slightly lower than unity, and depends very little on the adopted technology [9]. For the adopted 90-nm technology, this ratio results to 0.89, which in turn leads to by numerically solving (9). Very close values of are expected using different technologies, due to the weak dependence of on the technology. For example, if varies from 0.8 to 1, varies from 3.43 to Note that assuming f 1 we have (1=f ) = ((1 0 f )=(1 0 f )) 1. (6) (7) (8) (9) (10) from which it is apparent that the optimum delay linearly increases as increasing. It is worth noting that (10) is very useful in practical designs, since it provides a quick estimation of the achievable speed before actually carrying out the circuit optimization. Analogously, by substituting the resulting, relationship (6) gives the overall bias current (i.e., the power consumption) that is needed to achieve the delay in (10). IV. ANALYSIS OF POWER DELAY TRADEOFF In the previous sections, the optimum value of was evaluated to achieve the best speed. In practical cases, this is not usually allowed due to the constraint on the power consumption, for reasons related to the heat removal and battery lifetime in portable devices. Accordingly, a suitable tradeoff must be chosen in the power delay design space. Analysis of (6) and (8) reveals that increasing values of lead to a worse speed and at the same time a power saving. Obviously, values of lower than should always be avoided, since they lead to both speed degradation and power consumption increase. To better understand the power delay tradeoff, let us consider the overall buffer current normalized to the optimum value in (6) with, and the overall delay normalized to the optimum value in (10), whose expressions are immediately found from (6) and (8) (11a) (11b) Various interesting properties of and can be derived from (11). First, if, the normalized current is approximately inversely proportional to. This means that an increase in by a given factor leads to a proportional power saving, compared to the optimum case with. Secondly, the normalized delay in (11b) almost linearly increases as increasing, considering that the logarithmic function at the denominator has a weak dependence on. To better understand the dependence of (11a), (11b) on, these relationships are plotted versus in Fig. 3 under the adopted 90-nm technology, i.e., with (almost the same results are expected with different technologies, due to the weak effect of technology on, as discussed in Section III). From Fig. 3, it is apparent that the normalized delay slowly increases when increasing, whereas the normalized current decreases much faster. Hence, a considerable power saving can be achieved by increasing at the cost of a small speed degradation, as compared to the optimum case. For example, from Fig. 3, a 50% reduction in the power consumption (i.e., ) is achieved with, which leads to a delay increase of only 10% (i.e., ). Alternatively, a 63% reduction in the power consumption with a delay increase of 20% is achieved with. Different power delay tradeoffs

4 ALIOTO AND PALUMBO: POWER-AWARE DESIGN OF NANOMETER MCML TAPERED BUFFERS 19 Fig. 3. Plot of I and versus f. can be chosen from Fig. 3, depending on the considered application. As previously discussed, these numerical results are almost independent of the adopted technology. 4 According to the above considerations, the optimum sizing discussed in Section III rarely makes sense, since almost the same speed can be achieved at much lower power consumption, as compared to the minimum-delay design. A better understanding of the power delay tradeoff can be achieved from the power delay product and the energy delay product normalized to the optimum case in (12a), (12b) (12a) (12b) which measure the power efficiency in applications where the power delay balance and a high speed are respectively required. From Fig. 4, which plots (12a) and (12b) versus, the PDP always decreases when increasing, i.e., the tapered buffer is more power efficient for increasing values of since the power saving is always greater than the speed degradation. From Fig. 4, the EDP rapidly decreases for ranging from to about 6, whereas it has a very flat minimum for greater values of. This means that, even in high-speed designs, the tapered buffer is strongly power-inefficient for, which agrees with the above intuitive considerations. Therefore, should always be set to a value greater than 6, according to the specific tradeoff required by the considered application. Interestingly, due to the almost constant EDP for, from (12b) a current decrease by a given factor leads to a (lower) delay increase by the square root of the same factor. V. DESIGN EXAMPLES AND VALIDATION The theoretical results presented in the previous sections were validated by means of Spectre simulations of MCML tapered buffers, which were designed assuming the typical values 4 For example, for a technology having f = 3:43 (i.e., c =c =0:8, from Section III) a 50% (63%) power reduction is achieved with f = 5:9 (f = 7:5), which is very close to the value f =6(f =7:6) previously found for the 90-nm technology. Fig. 4. Plot of PDP and EDP versus f. mv and with the above considered 90-nm CMOS technology and for different values of. The fan-out was chosen as a power of, to widely explore the design space with integer values of from (5). Some results are reported in Table III, where is assumed to be assigned to twice the input capacitance of a minimumsized transistor, i.e., af. Observe that the wire capacitance to connect adjacent cells is about this value, hence it does not make sense to consider lower values of, since they would slow down the tapered buffer [from (8)] without significantly improving the speed of the gate driving it. In Table III, the minimum-delay designs (i.e., with ) are reported in bold, whereas the other cases have a greater [i.e. a lower, as compared to the optimum number of stages from (5)]. Analysis of Table III reveals that the tapered buffer delay model (8) (10) agrees well with simulation results. Indeed, the error with respect to simulations is always lower than 23% and typically much lower (in the order of 10%). In addition, results with greater values of, which are omitted for reasons of space, always have a better accuracy compared to Table III. In regard to the power delay tradeoff, the predicted and in (11) agree well with simulation results, with a maximum error of 11.9%. Therefore, the proposed models are adequately accurate for design purposes. A. Case With For the sake of clarity, let us discuss the design with in Table III. According to (5), five stages are required. According to (4) and data in Table I, from the requirement 288 af, the first stage has a bias current of A, and the subsequent stages have a current that is progressively increased by, 5 i.e., 60.4, 211.3, A, and ma. The resulting simulated delay is ps, which comes at the cost of high power consumption, due to the high overall current of 3.62 ma. To achieve a more power-efficient design, let us increase to 8.1, which leads to a 3-stage design from (5), a 23% delay 5 Note that not only evaluation of f from (9) is accurate enough for modeling and design, but, since the curve in Fig. 3 is flat around f, also in case of inaccuracies around its theoretical value we get a very small delay penalty.

5 20 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 55, NO. 1, JANUARY 2008 TABLE III SIMULATION AND PREDICTED DELAY (90-nm TECHNOLOGY: F =3:5, Cin = 288 af) to quickly estimate the achievable performance under power/ delay constraints before the design are also derived. A design example and various design cases have been presented by adopting a 90-nm CMOS technology. Simulations confirm the validity of the model adopted and approximations introduced. REFERENCES increase from (11b), and a 65% reduction in the power consumption from (11a). According to (4b), the current of the first stage is again A, whereas the following stages have a current of A and ma, respectively. Compared to the minimum-delay design, the overall current (i.e., 1.28 ma) is reduced by 65%, as expected. The resulting delay (i.e., ps) is increased by 30%, which agrees well with the predicted 23% increase. For the sake of clarity, all predicted and simulated results reported in Table III are plotted in Fig. 4 versus. The results were shown to agree well with simulations in several other design cases, which are omitted for the sake of brevity. VI. CONCLUSION In this brief, a design strategy for MCML tapered buffers has been proposed. At the best of the authors knowledge, this is the first attempt to analytically manage the power delay tradeoff in MCML cascaded gates. Simple and general design criteria have been provided to manage the power delay tradeoff, as well as to size the bias currents of the buffer stages. Interestingly, it has been shown that minimum-delay design does not make sense even in high-speed applications, since the power consumption can be considerably reduced at the cost of a negligible delay increase. For example, a 50% power reduction is achieved with a 10% delay increase, and in general the power reduction is always much greater than the corresponding delay penalty. It has also been shown that the theoretical results are essentially independent of the technology in practical cases. Models [1] M. Mizuno et al., A GHz MOS adaptive pipeline techniques using MOS current-mode logic, IEEE J. Solid-State Circuits, vol. 31, no. 6, pp , Jun [2] A. Tanabe, M. Umetani, I. Fujiwara, T. Ogura, K. Kataoka, M. Okiara, H. Sakuraba, T. Endoh, and F. Masuoka, 0.18-m CMOS 10-Gb/s multiplexer/demultiplexer ICs using current-mode logic with tolerance to threshold voltage fluctuation, IEEE J. Solid-State Circuits, vol. 36, no. 6, Jun [3] B. Razavi, Design of Integrated Circuits for Optical Communications. New York: McGraw-Hill, [4] T. H. Lee, The Design of CMOS Radio Frequency Integrated Circuits, 2nd ed. Cambridge, U.K.: Cambridge University Press, [5] A. Tanabe, Y. Nakahara, A. Furukawa, and T. Mogami, A redundant multivalued logic for a 10-Gb/s CMOS demultiplexer IC, IEEE J. Solid-State Circuits, vol. 38, no. 1, pp , Jan [6] Y. Moon, S. Lee, and D. Shim, A divide-by-16.5 circuit for 10-Gb ethernet transceiver in m CMOS, IEEE J. Solid-State Circuits, vol. 40, no. 5, pp , May [7] M. Alioto, R. Mita, and G. Palumbo, Design of high-speed power-efficient MOS current-mode logic frequency dividers, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 11, pp , Nov [8] R. Nonis, E. Palumbo, P. Palestri, and L. Selmi, A design methodology for MOS current-mode logic frequency dividers, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 2, pp , Feb [9] J. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits (A Design Perspective). Upper Saddle River, NJ: Prentice-Hall, [10] M. Alioto and G. Palumbo, Design strategies for source coupled logic gates, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 50, no. 5, pp , May [11] M. Alioto and G. Palumbo, Model and Design of Bipolar and MOS Current-Mode Logic: CML, ECL and SCL Digital Circuits. Norwell, MA: Springer, [12] M. Alioto and G. Palumbo, Power-aware design techniques for nanometer MOS current-mode logic gates: A design framework, IEEE Circuits Syst. Mag., no. 4, pp , Dec [13] J. Musicer and J. Rabaey, MOS current-mode logic for low power, low noise CORDIC computation in mixed-signal environments, in Proc. ISLPED, 2000, pp [14] H. Hasan, M. Anis, and M. Elmasry, MOS current mode circuits: Analysis, design, and variability, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 8, pp , Aug [15] M. Alioto, L. Pancioni, S. Rocchi, and V. Vignoli, Power delayarea-noise margin tradeoffs in positive-feedback source-coupled logic gates, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 9, pp , Sep [16] M. Alioto and G. Palumbo, Design strategies of Cascaded CML Gates, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 2, pp , Feb [17] M. Alioto, A. D. Grasso, and G. Palumbo, Design of cascaded ECL gates with a power constraint, Electron. Lett., vol. 42, no. 4, pp , Feb