IN PAST years, the delay uncertainty has become a fundamental

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1 1322 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 12, DECEMBER 2006 Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison Massimo Alioto, Fellow, IEEE, and Gaetano Palumbo, Senior Member, IEEE Abstract In this paper, some of the most practically interesting full adder topologies are analyzed in terms of their delay dependence on the supply voltage fluctuations, which are a major contribution to the delay uncertainty, which in turn limits the speed performance of current VLSI circuits. Analytical models of the delay sensitivity with respect to supply variations are derived by following a simplified circuit analysis, and the resulting expressions are simple enough to afford a deeper insight into the impact of supply voltage variations on each topology. The models are shown to be sufficiently accurate through simulations with CMOS technologies having a minimum feature size ranging from 90 nm to 0.35 m. Several interesting properties and design considerations are derived from these models, and the effect of the supply voltage scaling, technology scaling, transistor sizing, and input transition time is discussed. Strategies to evaluate the delay sensitivity since the early design phases (e.g., from ring oscillator measurements) are also introduced. As a fundamental result, it is shown that the delay sensitivity to supply variations will increase in the next technology nodes, thus, it is expected that controlling the supply variations will be an increasingly important issue in the design of the next generation VLSI circuits. The proposed methodology is also analyzed in the case of more general digital circuits, and is used to estimate the impact of the inter-die threshold voltage variations on the delay of the considered full adder topologies. Index Terms Adders, CMOS, delay variations, full adder, inter-die variations, modeling, supply variations, VLSI. I. INTRODUCTION IN PAST years, the delay uncertainty has become a fundamental aspect in the design of deep-submicrometer (DSM) CMOS digital circuits [1] [3]. Indeed, the delay of the logic gates and the interconnects are affected by variations that are due to process, environmental, and supply variations. In particular, the process fluctuations introduce statistical inter-die/ intra-die variations both in the physical properties (e.g., transistor threshold voltage and transconductance, interconnect resistance, and capacitance) and geometries of the layers which transistors and interconnects consist of, which in turn translate into delay variations [4] [6]. Environmental variations also contribute to the delay uncertainty, such in the case of the temperature which varies both in time (according to the instantaneous power consumption) and space (due to nonuniform power consumption), which in turn affects the physical properties and, hence, the delay of logic gates and interconnects. As a third Manuscript received January 21, 2006; revised July 26, M. Alioto is with the Dipartimento di Ingegneria dell Informazione (DII), Università di Siena, Siena 53100, Italy ( malioto@dii.unisi.it). G. Palumbo is with the Dipartimento di Ingegneria Elettrica Elettronica e dei Sistemi (DIEES), Università di Catania, Catania 95125, Italy ( gpalumbo@diees.unict.it). Digital Object Identifier /TVLSI source of delay uncertainty, supply voltage variations are always observed in integrated circuits (ICs) due to the time-varying voltage drops in the supply distribution network that are determined by the large currents drawn by the switching logic gates [7]. Finally, a fourth and increasingly important source of delay uncertainty is the delay noise, which arises from the capacitive coupling between switching nodes [1]. Delay variations impose a limit to the speed performance of synchronous circuits, since the minimum allowed cycle time is determined by the delay of the critical path where the actual delay of the generic th path (due to flip-flops, combinational logic, interconnect delay, clock skew, and jitter) is the sum of its nominal value and its variation (whose sign is often time-varying). From (1), an increase in the delay uncertainty in the critical path(s) determines an increase in the cycle time and, hence, a performance degradation. Moreover, the delay uncertainty is becoming an increasing fraction of the clock period [2], and thus, a major limit to the speed improvement in current deep-sub-micrometer (DSM) technologies [1], [3], [8]. Moreover, the delay uncertainty significantly increases the design effort to meet a cycle time specification, since a greater number of potentially critical paths must be considered and carefully designed [2]. In this paper, the delay uncertainty due to supply variations is analyzed in the particular case of the adder circuits, which are a very important class of digital circuits since they are frequently in the critical path of the control unit (due to the widespread usage of branch-prediction techniques) and the data-path of microprocessors and DSPs [2], [3], [7], [9]. Accordingly, the delay variations of adder circuits often affect the cycle time in (1). Since many adder architectures are based on the full adder gate as a building block, and their overall delay is proportional to the carry input to carry output delay of this gate [3], [9], it is sufficient to evaluate the full adder delay variations to predict the delay variations of the adders. For this reason, in this paper, the analysis is focused on the evaluation of the delay uncertainty of the most important topologies used to implement a full adder, which were identified in a previous paper by the same authors [10]. The sensitivity of these topologies to supply variations is analytically evaluated by resorting to simplified circuit models, and the results are extensively validated by means of circuit simulations with a 90-nm, m, and m CMOS technology, that span five technology generations. The analytical models derived allow a better understanding of the main contributions to the delay variation, and are useful (1) /$ IEEE

2 ALIOTO AND PALUMBO: IMPACT OF SUPPLY VOLTAGE VARIATIONS ON FULL ADDER DELAY: ANALYSIS AND COMPARISON 1323 for the system-level design to predict the delay variations due to an assigned supply variation, as well as for the transistor-level design to identify the best topology under constraints on the delay, the power consumption, and the supply variations. These models also allow to carry out a clear comparison between different topologies regardless of the adopted technology, and to derive several interesting properties. The effect of the supply voltage scaling, technology scaling, transistor sizing and input transition time is discussed. For example, it is shown that the input rise/fall time plays a very important role only in some topologies, and that down-scaled technologies and low-power designs pay a greater speed penalty due to the supply variations. Accordingly, the delay sensitivity with respect to supply variations will grow in the next technology generations, thus, the supply fluctuations will have to be more tightly controlled, thereby making the design of the supply network more critical. Finally, the more general case of generic logic gates is also discussed in the context of the proposed methodology, which is also applied to evaluate the effect of the inter-die threshold voltage variations. This paper is organized as follows. In Section II, general considerations are reported, a figure of merit is introduced, the most important full adder topologies are briefly reviewed, and simulation conditions are identified to achieve meaningful results. In Section III, the Mirror topology is analyzed and modeled after analyzing a simpler class of static CMOS gates (i.e., the ring oscillator). In Section IV, the results for the Mirror full adder are extended to the Dual-Rail Domino and Complimentary Pass-Transistor Logic (CPL) topologies, whereas the Transmission Gate (TG) topology is analyzed in Section V. Further remarks on the proposed approach and extension to general digital circuits are discussed in Section VI, along with the analysis of the impact of the inter-die threshold voltage variations. Conclusions are finally reported in Section VII, and two Appendices are added to improve the readability of this paper. II. CONSIDERATIONS ON ADDERS AND THEIR DELAY UNCERTAINTY DUE TO SUPPLY VARIATIONS The full adder gate is the main building block of several adder architectures, such as the ripple carry, carry skip, and carry select adders [3], [9], [11]. The full adder inputs are the two digits to be summed, and, and the carry input deriving from the previous digits calculations. The outputs are the result of the sum operation and the carry out, respectively, given by (2a) (2b) from which if, and in this case, the full adder is said to be in the propagate mode. The previously mentioned adder architectures are implemented by properly cascading full adders, each of which has its carry output connected to the carry input of the following one, as depicted in Fig. 1. The resulting overall worst-case delay derives from the carry propagation (i.e., with all full adders in the propagate mode) from the first to the last full adder, as shown in Fig. 1 by the path in the gray line. Accordingly, the worst-case adder delay is well-known to be equal to the Fig. 1. Typical chain of full adders. Fig. 2. Circuit setup to evaluate the carry input to carry output delay of a full adder. product of the carry input to carry output delay of the full adder and a constant which depends on the number of bits and the specific architecture [7], [11] [14]. Thus, the adder delay variations, due to supply voltage variations, are directly determined by the variations of the carry input to carry output delay of the full adder, and it is sufficient to know the variations in to evaluate the adder delay variations. To correctly evaluate the delay, the full adder gate must be driven with a realistic input waveform and has to drive a realistic load, since they both significantly affect the gate delay. Since from Fig. 1, each cascaded full adder is driven and loaded by an equal one, the resulting circuit setup 1 to evaluate is reported in Fig. 2, where the full adder FA2 under test is driven by the output waveform of FA1 and is loaded by the input capacitance of FA3. Moreover, since the latter capacitance may slightly be affected by the load of FA3 through the Miller effect in capacitances which couple input and output of FA3 (usually gate-drain transistor capacitances), FA3 is loaded by another equal full adder FA4. In Fig. 2, all full adders are in the propagate mode, and is taken as the worst-case delay among the different values of and and the rise/fall carry transient. In the literature, many full adder topologies were proposed, but only a few are actually suitable for current applications aiming at a high-speed performance, a low power consumption, or an efficient balance of these requirements. As was shown in [10], among the existing topologies, the Mirror adder is particularly interesting due to its favorable power-delay tradeoff, the dynamic Dual-Rail Domino and the CPL due to their very high speed, and the TG topology due to its low power consumption. In the following sections, these topologies will be analyzed in terms of the delay dependence on supply variations through the circuit setup in Fig Actually, FA4 of Fig. 2 was eliminated only for the TG full adder because this topology does not provide input/output (I/O) decoupling, i.e., FA2 is loaded by all successive full adders (not only by FA3) [10]. Otherwise, the presence of FA4 would have lead to an unfair evaluation of the delay of FA2, compared to the other topologies.

3 1324 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 12, DECEMBER 2006 Fig. 3. Topology of the Mirror full adder. Now, let us consider the effect of a variation in the nominal supply voltage on the full adder delay. In practical cases, the variation is reduced by properly sizing the supply distribution rails and the decoupling capacitors which filter out the supply fluctuations, even though their effectiveness is limited by their area growth: as a compromise, 5%-10% supply voltage variations are usually tolerated in VLSI circuits [3]. This means that the ratio is small (between 0.05 and 0.1), thus, the delay dependence on supply variations can reasonably be measured by the delay sensitivity with respect to the supply voltage which, in the following, will be adopted as a figure of merit to evaluate the impact of supply variations on the delay of the full adder topologies, and thus, their speed penalty in (1) paid for a delay variation. III. ANALYSIS AND MODELING OF THE MIRROR TOPOLOGY The Mirror full adder topology in Fig. 3 is implemented with the traditional static CMOS logic style. Until now, some delay variation models for this logic style have been recently proposed [15] [17], but their results are not satisfactory. Indeed, in [15] and [16], an empiric delay model around only one nominal supply is proposed, thus, it is strongly inaccurate for a supply voltage significantly different from the nominal value, and cannot be used to analyze the delay variation versus arbitrary values of. Furthermore, these models are empiric and, thus, lack of physical meaning, thus, they do not provide any insight into the delay dependence. In [17], the delay is evaluated by assuming a square I-V MOS characteristics, which is strongly unrealistic in current DSM technologies, and the results in [1] are not useful neither to model nor to understand the delay dependence on supply variations, since they are based on simulations in a narrow range of technologies. To evaluate the delay dependence on supply variations of the Mirror full adder, it should be recalled that the delay of a generic (3) Fig. 4. Topology of a CMOS ring oscillator. CMOS gate can be evaluated by reducing its pull-up (pull-down) network to a single pmos (nmos) transistor, i.e., analyzing a simple inverter gate (or a cascade of inverter gates when a logic gate consists of simpler cascaded gates) [7]. Moreover, the delay dependence on supply variations of full adders must be evaluated by assuming cascaded gates that are equally loaded and driven, as discussed in Section II. Thus, the delay sensitivity of full adders can be analyzed by simply considering a cascade of inverter gates, as in the case of a traditional ring oscillator. Accordingly, the delay analysis in the much simpler case of a ring oscillator will be first addressed in Section III-A, and the results will be then extended to cascaded full adders in Section III-B. A. Effect of Supply Variations on CMOS Ring Oscillators Let us consider a CMOS ring oscillator consisting of a loop of (odd) cascaded inverter gates, each being driven and loaded by an equal gate, according to Fig. 4. As usual, the delay of each stage during a transition can be evaluated by analyzing the (dis)charge transient of the equivalent capacitance at the output node through a current source which schematizes the switching transistor providing the (dis)charge current. Moreover, in the following the alpha-power law is adopted for the sake of simplicity [18]. In this I-V model, the nmos transistor current in the saturation region is expressed as a function of the gate source voltage according to (4) (4)

4 ALIOTO AND PALUMBO: IMPACT OF SUPPLY VOLTAGE VARIATIONS ON FULL ADDER DELAY: ANALYSIS AND COMPARISON 1325 TABLE I MAIN PROCESS PARAMETERS FOR THE ADOPTED TECHNOLOGIES Fig. 5. Equivalent circuit of a generic ring oscillator stage (high-to-low output transition). TABLE II NUMERICAL VALUES OF PARAMETERS IN (13b) where is a technology-dependent constant which is proportional to the transistor aspect ratio, is the transistor threshold voltage, and is a technology-dependent coefficient ranging from 1 (DSM transistors) to 2 (long-channel transistors). Now, let us analyze the delay of a ring oscillator inverter in a high-to-low output transition. During this transition, the pmos transistor is rapidly lead to the cutoff region, whereas the nmos transistor works in the saturation region. 2 Hence, the generic inverter can be represented by the nmos providing the current in (4) and an equivalent linear capacitance at the output node which accounts for the nmos/pmos contributions, the wire parasitic capacitance and the input capacitance of the following gate, according to Fig. 5. Assuming that the capacitance is initially charged at the voltage, the output voltage waveform is equal to the voltage across the capacitance (5) from which parameter is obtained by setting and solving for, which yields From (8), the delay results to where is actually an unknown variable, which can be approximately found by observing that it is the time required to cross the entire logic swing. In general, we can assume that (8) (9) where the gate source voltage of the nmos transistor in CMOS static logic is well approximated by a saturated ramp with rise time [3], leads to the fol- after substituting it in (9) and solving for lowing inverter delay expression: (10) if if (6) (11) The inverter delay is defined as the difference of the time when crosses the value and the time when reaches the same value. From (6), parameter results to, whereas parameter can be found by setting and solving (5) for. Since in a ring oscillator the input and output rise time of each stage are equal (i.e., and vary at the same speed), it is reasonable to assume that for the input transient has not been completed. Accordingly, the expression of for in (6) must be substituted in (5), which can be rewritten as 2 Observe that this assumption is correct even when the output voltage falls at the half-swing point V =2, since the transistor drain-source voltage V under which the transistor leaves the saturation region (entering the triode region) is much lower in deep-submicrometer devices, due to the velocity saturation of carriers. (7) By substituting (11) in (3), the following expression of the delay sensitivity with respect to supply variations is achieved: (12) In ring oscillators, where each inverter is driven and loaded by equal gates, the slope of the voltage variation is equal for each node. Assuming that the output node of an inverter starts switching when the input node reaches the inverter logic threshold (typically for symmetrical gates), is easily found to be twice. Accordingly, can be set to 2 in (11) and (12), thereby yielding (13a) (13b)

5 1326 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 12, DECEMBER 2006 Fig. 6. (a) Magnitude of the delay sensitivity versus V =V in a ring oscillator stage (90-nm technology). (b) Magnitude of the delay sensitivity versus V =V in a ring oscillator stage (0.18-m technology). (c) Magnitude of the delay sensitivity versus V =V in a ring oscillator stage (0.35-m technology). (d) Delay sensitivity model error versus V =V in a ring oscillator stage. Relationship (13b) was validated by performing circuit simulations with three different technologies having a minimum feature size of 90 nm, 0.18 m, and 0.35 m, whose main parameters are reported in Table I. The resulting numerical values of parameters and in (13b) for these technologies are reported in Table II. In particular, parameter was found by interpolating the simulated values and of the transistor current (4), respectively, obtained for equal to the maximum supply voltage allowed by the technology and (by inverting the ratio, immediately results to ). Parameter was found by extrapolating the value such that, which is easily accomplished by inspection of the plot of versus, since it is a linear function from (4). The magnitude of the predicted sensitivity in (13b) and the simulated values are plotted versus in Fig. 6(a) (c) for the 90-nm, m, and m technology, respectively, and the error of (13b) compared to simulations is plotted in Fig. 6(d). Observe that in Fig. 6(a) (d) the maximum value of is different for the three considered technologies, since the maximum allowed supply voltage scales faster than the threshold voltage [8], whereas the minimum value was chosen equal to 1.5 because the CMOS gates are well known to be power-inefficient for [7]. From Fig. 6(d), the model error is typically in the order of a few percent and is always lower than 18% for. It is worth noting that these results also account for the low-to-high transition, since they are obtained from the oscillation period of the ring oscillator, thus, the theoretical model in (13b) is valid for both output transitions. 3 It is worth noting that the assumption of a linear capacitance at the output node in Fig. 5 was verified to be correct through simulations. Indeed, the same circuit was simulated by adding a large linear capacitance at the output of each stage, and the resulting sensitivity agreed very well (within 1% 2%) with the values previously found with only parasitic transistor capacitances. This is easily justified by considering that the overlap and the channel capacitive contributions are essentially linear, and the same consideration holds for the drain-bulk junction capacitances since they are strongly reverse biased. B. Effect of Voltage Variations on the Mirror Full Adder The results obtained for the ring oscillator stage in the previous subsection can be extended to the Mirror full adder under 3 This is partially due to the symmetric transistor sizing (i.e., with the pmos aspect ratio doubled with respect to the nmos), and confirms that the dependence of the current i on V in a pmos is very similar to that of an nmos transistor. In the following sections, it will be shown that the model is accurate even for nonsymmetric sizing.

6 ALIOTO AND PALUMBO: IMPACT OF SUPPLY VOLTAGE VARIATIONS ON FULL ADDER DELAY: ANALYSIS AND COMPARISON 1327 proper assumptions. Indeed, when considering the path from the carry input to the carry output in Fig. 3, the Mirror full adder can be modeled as two cascaded inverters, i.e., the equivalent inverter associated with the static network generating the signal [obtained by lumping all nmos (pmos) transistors in the pull-down (pull-up) network into a single equivalent nmos (pmos) transistor] and the subsequent inverter driven by this signal. Accordingly, the delay is equal to the sum of the two corresponding delay contributions, each of which can be evaluated by analyzing the same equivalent circuit in Fig. 5 that was previously used for ring oscillators. Assuming again that for each equivalent inverter the rise time is twice the delay time (i.e., ), which often holds in CMOS digital circuits, the resulting delay sensitivity is still expressed by (13b), as shown in detail in Appendix I. The model in (13b) was validated for a Mirror full adder designed with the three adopted technologies and with different transistor sizes. To be more specific, transistors were sized in three practical design cases, with a low-power target (i.e., with minimum-sized transistors), a power-efficient target (i.e., with transistors sized to minimize the power-delay product (PDP) [7]) and a high-speed target (i.e., with transistors sized to minimize the energy-delay product (EDP) [7]). The simulated results and those predicted by (13b) are plotted versus in Fig. 7(a) for the 90-nm technology. Analogous results were found for the and m technology, and are not reported for the sake of brevity. Inspection of Fig. 7(b) reporting the error of (13b) compared to simulations confirms that the sensitivity model in (13b) has an adequate accuracy for practical purposes, as the error is always within 22%, 19%, and 18% in the low-power, power-efficient, and high-speed design, and the average error is only 5.6%, 9.5%, and 9.3%, respectively. For the m technology under the same cases, the maximum error was found to be 20%, 8.2%, and 6.4%, respectively, and the average error was 11%, 3%, and 2.5%. For the m technology, the maximum error was found to be 21%, 15%, and 14%, respectively, and the average error was 13%, 8%, and 6%. C. Delay Sensitivity Considerations The sensitivity model in (13b) can be exploited to derive some interesting properties of the delay dependence on supply variations. As expected, the sensitivity (13b) is always negative, i.e., an increase in leads to a decrease in the delay. Moreover, it mainly depends on the ratio of the supply voltage and the transistor threshold voltage, and a lower sensitivity is achieved for greater values on this ratio. In other words, the traditional high-speed strategy based on the supply voltage increase to decrease the nominal delay also decreases its uncertainty under a given tolerance on, at the expense of a greater power consumption. Nevertheless, low-power designs with lower pay a significant speed penalty due to the increased delay sensitivity. For example, from Fig. 7(a), a 60% sensitivity increase is observed for a 30% decrease of, compared to the maximum supply voltage of the 90-nm process. This translates into a power efficiency degradation of circuits designed for low power. In regard to the effect of the dimensional scaling, the maximum supply voltage scales faster than the threshold voltage to Fig. 7. (a) Magnitude of the delay sensitivity versus V =V in a Mirror full adder (90-nm technology). (b) Delay sensitivity model error versus V =V in a Mirror full adder (90-nm technology). limit the increase in the subthreshold current [8], thus, future technologies are expected to have a greater delay sensitivity to supply variations from (13b). As an opposite phenomenon, parameter tends to be slightly closer to unity for scaled processes (due to the carrier velocity saturation effects), but the corresponding sensitivity reduction is insignificant in deep-submicrometer processes and introduces only negligible effects. These considerations explain why the design of the supply network has become more critical in DSM technologies, and shows that the control of the supply voltage will be more and more important to avoid an excessive speed penalty in later technology nodes, according to the experimental results in [2] and [3]. From (13b), it is also apparent that the sensitivity essentially does not depend on the load capacitance, and thus, on the fan-out and the wire capacitance. This allows for accurately evaluating the delay sensitivity of a given circuit at the transistor-level design phase, without requiring a detailed physical design. In addition, from (13b), the delay sensitivity is almost independent of the transistor sizing, as confirmed by Fig. 7(a). Finally, it was shown that the delay sensitivity of the Mirror full adder is essentially the same as the ring oscillator. This property is very useful, since the delay per stage in a ring oscillator (or equivalently its oscillation frequency) is a well-known figure of merit to evaluate and optimize the process, and is known well before the circuit design phase.

7 1328 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 12, DECEMBER 2006 Fig. 8. Topology of the Dual-Rail Domino full adder. IV. ANALYSIS AND MODELING OF THE DUAL-RAIL DOMINO AND THE CPL TOPOLOGIES In this section, it is shown that the model in (13b) and the related considerations in Section III-C also hold for the Dual- Rail Domino and the CPL full adder. A. Effect of Voltage Variations on the Dual-Rail Full Adder The Dual-Rail Domino full adder in Fig. 8 consists of the cascade of two CMOS gates (i.e., a differential dynamic gate and an inverter for each output) that can be modeled by the equivalent circuit in Fig. 5, whose delay and sensitivity model have already been derived for the Mirror adder. Thus, the sensitivity model in (13b) is expected to be valid for the Dual-Rail Domino full adder. To validate this model, (13b) was compared to simulation results in two design cases, with a power-efficient target (i.e., with transistors sized to minimize the PDP) and a high-speed target (i.e., with transistors sized to minimize the EDP), whereas the low-power target was not considered because of the unsuitability of dynamic logic for low-power applications. The resulting predicted and simulated delay sensitivity for the 90-nm technology is plotted versus in Fig. 9(a), and the model error is plotted in Fig. 9(b). Inspection of these figures confirms that the model in (13b) is sufficiently accurate, as the error is always lower than 18% and the average error is only 5%. For the m (0.35- m) technology, the error was found to be always lower than 11% (20%), with an average value of 6% (10%). B. Effect of Voltage Variations on the CPL Full Adder Now, let us consider the CPL full adder in Fig. 10, and in particular, its carry logic in the left-hand side that defines the carry delay. It is interesting to observe that the CPL topology consists of the cascade of a pass-transistor circuit and an inverter. The latter apparently has the same delay dependence on supply variations as the CMOS Mirror topology discussed in Section III, whereas the analysis of the pass-transistor carry logic needs some further observation. In particular, let us observe that the carry delay is evaluated when the carry input switches with other inputs and being kept constant. Under this specific condition, the transistors driven by inputs and have already switched, thus, the pass-transistor logic is equivalent to a single nmos transistor driven by the carry input which switches and (dis)charges the capacitance at the inverter input node, i.e., the pass-transistor logic of the CPL topology can still be schematized as in Fig. 5 (note that the cross-coupled pmos level restorers are designed to provide a small current only at

8 ALIOTO AND PALUMBO: IMPACT OF SUPPLY VOLTAGE VARIATIONS ON FULL ADDER DELAY: ANALYSIS AND COMPARISON 1329 driving the parasitic capacitance at the carry output node, as depicted in Fig. 13. Accordingly, the TG full adder delay under a step input is equal to (14) whereas, for non-zero values of the input transition time, the delay of the first-order RC circuit can be expressed as, where is a coefficient ranging from 0.69 (very fast inputs) to 1 (very slow inputs) [19]. However, when the input and output transition time are comparable, parameter is approximately equal to 0.8 [20], thus, in practical cases, the delay of the RC circuit in Fig. 13 (and thus, that of a TG full adder) ranges from to. Moreover, as was discussed in Section III, the transistor capacitance contributions to in (14) are essentially independent of the supply voltage, and can be approximated to a linear capacitance. From (14), the delay sensitivity (3) for a TG full adder is simplified into (15) that requires the evaluation of the dependence of on the supply voltage. In the following, will be evaluated as the reciprocal of the average conductance Fig. 9. (a) Magnitude of the delay sensitivity versus V =V in a Dual-Rail Domino full adder (90-nm technology). (b) Delay sensitivity model error versus V =V in a Dual-Rail Domino full adder (90-nm technology). the very end of the transient [7], [10], thus, they do not significantly affect the delay variations). Accordingly, the passtransistor logic has the same delay dependence on the supply voltage as the CMOS inverter discussed in Section III-A, thus, the sensitivity model in (13b) still applies to the CPL logic style. To validate this model, simulations were performed under a low-power and a power-efficient design, for which the same results were obtained since they lead to the same transistor sizing. The high-speed design case was not considered since for very high-speed requirements the CPL full adder is less efficient than the Dual-Rail Domino Topology. The resulting predicted and simulated delay sensitivity for the 90-nm technology is plotted versus in Fig. 11(a), and the model error is plotted in Fig. 11(b). From these figures, the error is always lower than 18% and typically in the order of 4%, thereby confirming the adequate accuracy of (13b) for the CPL topology. For the m (0.35- m) technology, the error was found to be always lower than 21% (22%), with an average value of 11% (12%). V. ANALYSIS AND MODELING OF THE TG TOPOLOGY The TG full adder in Fig. 12 is well known to be lacking of an I/O decoupling, thus, it cannot be modeled as in Fig. 5. Observe that during a carry input transition the other inputs are stable, thus, the carry delay is determined by the Transmission Gate consisting of transistors M1-M2 in Fig. 12. As is well known, this Transmission Gate can be modeled with a resistance (16) which is obtained by averaging the TG small-signal conductance, which is equal to the sum of the small-signal nmos and pmos conductances and (since M1-M2 are connected in parallel) across all possible values of (from 0 to ). The small-signal nmos conductances and are usually modeled by if (17a) if if (17b) where is the effective carrier mobility, is the gate capacitance per unit area, is the transistor aspect ratio, and subscript is adopted for the nmos (pmos) transistor. By solving the integral (16), after substituting (17), assuming a symmetric transistor sizing (i.e., with ) and performing the calculations in Appendix II, the Transmission Gate resistance results to (18) where the average of the nmos and pmos threshold voltages, was expressed in Appendix II [see (B.8)] as a function of according to (19)

9 1330 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 12, DECEMBER 2006 Fig. 10. Topology of the CPL full adder. being and technology-dependent coefficients (derived in Appendix II) accounting for the body effect, whose numerical value for the three adopted technologies is reported in Table III. By substituting (18) into (15), the delay sensitivity of the TG full adder results to (20) whose magnitude is plotted versus (to make comparison with Figs. 7, 9, and 11 easier) in Fig. 14(a) for the 90-nm technology, along with the simulated results. The error of model (20) compared to the simulated results is plotted versus in Fig. 14(b), whose inspection reveals that the error of (20) is always lower than 15% and is typically lower than 11%. For the m (0.35- m) technology, the maximum and average error were found to be 17% (16%) and 10% (8%). Finally, to understand the effect of the technology scaling on the delay sensitivity of the TG full adder, it is useful to observe that the coefficient in (19) tends to decrease in down-scaled technologies, since it represents the threshold voltage contribution that is independent of the source-bulk voltage (i.e., not affected by the body effect). Instead, the coefficient in (19) is much lower than unity, thus, the term can be considered almost constant across different technologies. The net effect is a delay sensitivity increase due to the technology scaling at high values of that are usually adopted in TG full adders. For example, the delay sensitivity (20) for the 90-nm, m, and the m technology at the maximum supply voltage is respectively found to be 1.87, 1.7, and 1.55, from Table III. It is worth noting that the sensitivity increase compared to older technologies is lower than the increase observed in the other topologies. VI. REMARKS ON THE PROPOSED METHODOLOGY A. Comments on the Generality of the Proposed Approach The proposed methodology can be exploited to compare the impact of supply voltage variations on different logic styles. To this purpose, consider logic styles having driving capability (e.g., the traditional static CMOS logic), in which every gate can be modeled with an equivalent inverter, thus, its sensitivity is given by relationship (12). However, observe that the delay sensitivity evaluation in (12) requires the evaluation of parameter, which is related to the driving and the loading condition of the gate. In particular, let us consider the special case of an ideal step input (i.e., ), or a value of that is representative of typical situation. In the first case, relationship (12) no longer holds, and the sensitivity can be evaluated by setting in (5) and reiterating the same calculations as in Section III-A. After some analytical manipulations, the delay sensitivity is easily found to be given by (21) It is apparent that (21) is lower than (13b) due to the lower addend in the numerator (equal to 1 instead of 2). To be more specific, for the 90-nm technology with data in Table II and the supply voltage at the maximum value 1 V, a 45% reduction in the sensitivity is observed with respect to (13b), and an

10 ALIOTO AND PALUMBO: IMPACT OF SUPPLY VOLTAGE VARIATIONS ON FULL ADDER DELAY: ANALYSIS AND COMPARISON 1331 Fig. 12. Topology of the TG full adder. TABLE III NUMERICAL VALUES OF PARAMETERS IN (19) Fig. 11. (a) Magnitude of the delay sensitivity versus V =V in a CPL full adder (90-nm technology). (b) Delay sensitivity model error versus V =V in a CPL full adder (90-nm technology). even greater reduction is observed reducing the ratio. Moreover, especially in low-power designs or in technologies with a lower minimum feature size (where is scaled more aggressively), (21) is too optimistic and relationship (13b) must be used. This means that the input rise time gives a considerable contribution to the sensitivity in logic styles with driving capability. It is worth noting that the delay sensitivity in (12) increases as increasing the parameter, and this increase is more pronounced in down-scaled technologies. On the other hand, according to (20) the delay sensitivity is independent of the input slope in the case of logic styles without driving capability (e.g., circuits based on transmission gates or pass transistors). Thanks to relationship (A.1) in Appendix I, the proposed methodology can also be used in general digital circuits consisting of cascaded gates with driving capability, provided that the delay and parameter of each gate are known. Of course, when the value of parameter of each gate leads to approximately equal delay sensitivities for all gates (as in the case of cascaded full adders), relationship (12) can be used again to evaluate the overall delay sensitivity. As discussed in Appendix I, relationship (12) can also be used in cases where the gates with a different value of have a negligible propagation delay compared to the other cascaded gates having the same value of. B. Effect of Inter-Die Threshold Voltage Variations Although the proposed methodology is not sufficiently general to account for all the process and environmental variations affecting the delay, it can be used to model the effect of the variations that equally impact all the transistors of the same kind (nmos or pmos) lying in the same chip, as in the case of inter-die threshold voltage variations in circuits based on full adders. On the other hand, the analysis of intra-die threshold voltage variations is much more complex and computationally intensive, since such variations differently impact each transistor. This makes the proposed methodology unsuitable for analyzing intra-die variations. Now, let us evaluate the delay sensitivity to the inter-die threshold voltage variations. To this aim, observe that (11) was derived on a symmetrical inverter where the nmos and pmos threshold voltages were assumed to be equal. In a more general case, with different threshold voltages and, relationship (11) represents the fall delay or the rise delay if or is used instead of, respectively. Adopting the traditional definition, the delay is given by their average [7] (22)

11 1332 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 12, DECEMBER 2006 Fig. 13. Equivalent circuit of a TG full adder. Fig. 15. Delay sensitivity to the threshold voltage versus V =V in full adders with driving capability. for the power supply variations, the delay sensitivity of Mirror, dual-rail, and CPL full adders turns out to be (24) Fig. 14. (a) Magnitude of the delay sensitivity versus V =V in a TG full adder (90-nm technology). (b) Delay sensitivity model error versus V =V in a TG full adder (90-nm technology). from which the delay sensitivity with respect to to results that is plotted versus in Fig. 15 for the adopted CMOS technologies. Comparison of (13b) and (24) (or equivalently of Figs. 6 and 15) shows that the sensitivity to threshold voltage variations is significantly lower than the sensitivity to supply variations, i.e., the impact of a percentage variation on the power supply voltage is more significant than that of the same percentage variation on the threshold voltage. Moreover, from (24), the sensitivity with respect to the threshold voltage increases as scaling the technology, since is almost constant and tends to decrease, as discussed in Section III-C. In the case of the TG topology, the effect of inter-die threshold voltage variations must be evaluated for both nmos and pmos transistors. Without loss of generality, let us consider the inter-die threshold voltage variations of nmos transistors, that, after manipulating (18) and using (B.2), leads to (25) (23) and a similar relationship holds for the sensitivity with respect to. Hence, setting parameter equal to 2 as previously done that is approximately equal to relationship (24), considering that is close to unity in deep-submicrometer technologies. Of course, an equivalent relationship can be derived for the variations on.

12 ALIOTO AND PALUMBO: IMPACT OF SUPPLY VOLTAGE VARIATIONS ON FULL ADDER DELAY: ANALYSIS AND COMPARISON 1333 VII. CONCLUSION In this paper, the delay sensitivity to supply voltage variations was evaluated for some practically interesting full adder topologies. The analytical models are very simple and afford a deeper understanding of the delay uncertainty dependence on the design parameters, identifying the main contributions. As a fundamental result, it was shown that the delay sensitivity to supply variations decreases when increasing, thus, the traditional high-speed strategy based on the supply voltage increase to decrease the nominal delay also decreases its uncertainty under a given tolerance on at the expense of a greater power consumption. The considered topologies were found to have roughly the same sensitivity to supply variations, thus, the latter is not a meaningful figure of merit to select the proper topology for a given application. As far as the effect of the dimensional scaling is concerned, it was found that the technology scaling leads to a delay sensitivity increase for all full adder topologies, which means that the problem of controlling the supply variations will be an increasingly important issue in the next technology nodes. Furthermore, the TG full adder exhibits a slightly lower delay sensitivity increase due to the technology scaling at typical supply voltages, compared to the other topologies. Comparing the results for the TG full adder with those of the other topologies (having driving capability), it is apparent that no significant difference among the considered full adder circuits is observed (even considering the omitted curves obtained with the and m technology). To be more specific, the TG full adder has a moderately worse delay variation for high values of the supply voltage, especially in the case of the high-speed transistor sizing. Moreover, the small advantage of the TG full adder at low supply voltages cannot be exploited in practical case since its speed performance is severely degraded for [10], [21]. The sensitivity models were shown to be independent of the gate load capacitance, thus, the fan-out and the interconnect capacitances do not affect the delay variations. This means that the delay sensitivity can be accurately evaluated at the circuit design level, i.e., before the layout. As a further interesting property, it was shown that the Mirror, dual-rail, and CPL topologies have a delay sensitivity which is very close to that of a simple ring oscillator. Since the stage delay of a ring oscillator is a figure of merit that is usually adopted during the optimization of the fabrication process, the delay sensitivity of these full adder topologies is known once the process fine-tuning is concluded, i.e., before the circuit design. The analytical models were validated with Spectre simulations on a range of technologies spanning five technology nodes (i.e., by using a 90-nm, a m, and a m CMOS technology). The accuracy of the proposed expressions was shown to be adequate for modeling purposes. Thanks to their simplicity, the proposed analytical models can be used to predict the delay uncertainty under a bounded supply fluctuation, as well as to find the maximum tolerable supply variation for a given timing constraint. Therefore, these models are also a useful tool to design full adders (and thus, adder circuits) when the delay variations due to supply variations are taken into account, as is needed in current DSM CMOS technologies. Finally, it was shown that the proposed methodology is not only valid to analyze full adders, but can be applied in several other cases either by using the general results in Appendix I or using, again, the relationship applied for full adder cells if the digital circuit under analysis satisfies the conditions that allow the approximations in (13b). Moreover, this methodology was used to evaluate the impact of inter-die threshold voltage variations, and this analysis shows that the power supply variations typically have a higher impact on the delay variation than the inter-die threshold voltage variations. APPENDIX I Let us evaluate the overall delay sensitivity of cascaded gates, each of which can be modeled as an equivalent inverter with delay for given by relationship (11). After simple calculations, the overall delay sensitivity with respect to the power supply voltage results to (A.1) Observe that in (A.1) the delay contributions differ only for parameter and, where the former is related to the transistor aspect ratio of the equivalent inverter, whereas parameter relates the rise time to the delay. Moreover, from (12) the gate delay sensitivity differs only for parameter. Thus, assuming to be the same for, the corresponding gate delay sensitivity is the same for all gates, thus, the overall delay sensitivity is immediately found to still be given by (12). It is worth noting that (A.1) is approximately equal to (12) also when the gates that have different sensitivity values are very fast, i.e., when their propagation delay is negligible compared to the other gates having the same sensitivity. APPENDIX II The TG resistance can be explicitly evaluated by substituting (17a) (b) into (16) and solving the integral, thereby yielding (B.1) that was simplified by assuming a symmetric transistor sizing (i.e., ). Relationship (B.1) can be further simplified by observing that and in CMOS technologies have similar values, thus (B.2)

13 1334 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 12, DECEMBER 2006 where the average threshold voltage was defined as [the error of the right-hand side of (B.2) compared to its left-hand side is lower than 1% for the considered technologies]. By substituting (B.2) into (B.1), the resistance results to (B.3) which demonstrates (18). It is useful to observe that (B.3) was evaluated by assuming the mobility and the threshold voltage to be approximately independent of the supply voltage. For the adopted technologies, this approximation was verified to be very well satisfied for the mobility, whereas it is not correct for the threshold voltage, due to the body effect. Accordingly, to simplify the calculations the resistance can be still modeled by (B.3) by first assuming independent of, and then expressing as a function of. To this aim, let us consider the expression of the nmos threshold voltage that is adopted in standard BSIM models [22] (B.4) where is the threshold voltage with a zero source-bulk voltage, is a BSIM model parameter and is the well-known Fermi potential. The worst-case value of (B.4) occurs at the maximum source voltage (since the bulk is grounded), which in the range of interest where the nmos transistor is ON is equal to (for greater source voltages the nmos operates in the cutoff region) (B.5) where was approximated to (to avoid solving the nonlinear equation (B.5) with ). Now, (B.5) can be linearized around the maximum supply voltage allowed by the technology where coefficients and were defined as (B.6) (B.7a) (B.7b) Analogous results were obtained for the pmos transistor, with (B.6) (B.7) still valid but leading to different numerical values of the coefficients and. Accordingly, the average threshold voltage results to which demonstrates (19), after defining the coefficient the average of and ( and ). (B.8) ACKNOWLEDGMENT The authors would like to thank the anonymous reviewers for their stimulating comments and suggestions. REFERENCES [1] K. Bernstein et al., High Speed CMOS Design Styles. Norwell, MA: Kluwer, [2] D. Chinnery and K. Keutzer, Closing the Gap between ASIC & Custom. Norwell, MA: Kluwer, [3] A. Chrakasan, W. Bowhill, and F. Fox, Eds., Design of High-Performance Microprocessor Circuits. Piscataway, NJ: IEEE Press, [4] M. Eisele, J. Berthold, D. Shmitt-Landsiedel, and R. Mahnkopf, The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits, IEEE Trans. Very Large Scale Integrat. (VLSI) Syst., vol. 5, no. 4, pp , Dec [5] N. Shigyo, Tradeoff between interconnect capacitance and RC delay variations induced by process fluctuations, IEEE Trans. Electron Devices, vol. 47, no. 9, pp , Sep [6] J.-J. Liou, A. Krstic, Y. M. Jiang, and K.-T. Cheng, Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 22, no. 6, pp , Jun [7] J. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits (A Design Perspective). Englewood Cliffs, NJ: Prentice-Hall, [8] ITRS, International technology roadmap for semiconductors, (2006). [Online]. Available: [9] C. Nagendra, M. Irwin, and R. Owens, Area-time-power tradeoffs in parallel adders, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 43, no. 10, pp , Oct [10] M. Alioto and G. Palumbo, Analysis and comparison on full adder block in sub-micron technology, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 10, no. 6, pp , Dec [11] T. Callaway and E. Swartzlander, Low Power Arithmetic Components. Norwell, MA: Kluwer, [12] M. Alioto and G. Palumbo, A simple strategy for optimized design of one-level carry-skip adders, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 50, no. 1, pp , Jan [13] M. Alioto, G. Palumbo, and M. Poli, A gate-level strategy to design carry select adders, in Proc. ISCAS, 2004, pp [14] B. Parhami, Computer Arithmetic, Algorithms and Hardware Designs. New York: Oxford, [15] M. Saint-Laurent and M. Swaminathan, Impact of power-supply noise on timing in high-frequency microprocessors, IEEE Trans. Adv. Packag., vol. 27, no. 1, pp , Feb [16] S. Pant et al., Vectorless analysis of supply noise induced delay variation, in Proc. ICCAD, 2003, pp [17] R. Ahmadi and F. N. Najm, Timing analysis in presence of power supply and ground voltage variations, in Proc. ICCAD, 2003, pp [18] T. Sakurai and A. R. Newton, Alpha-Power law MOSFET model and its applications to CMOS inverter delay and other formulas, IEEE J. Solid-State Circuits, vol. 25, no. 2, pp , Apr [19] R. Mita, G. Palumbo, and M. Poli, Propagation delay of an RC-chain with a ramp input, IEEE Trans. Circuits Syst. II, Exp. Briefs, tobe published. as

14 ALIOTO AND PALUMBO: IMPACT OF SUPPLY VOLTAGE VARIATIONS ON FULL ADDER DELAY: ANALYSIS AND COMPARISON 1335 [20] M. Alioto and G. Palumbo, Oscillation frequency in CML and ESCL ring oscillators, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 48, no. 2, pp , Feb [21] R. Zimmermann and W. Fichtner, Low-power logic styles: CMOS versus pass-transistor logic, IEEE J. Solid State Circuits, vol. 32, no. 7, pp , Jul [22] Y. Cheng and C. Hu, MOSFET Modeling & BSIM3 User s Guide. Norwell, MA: Kluwer, Massimo Alioto (M 01 F 07) was born in Brescia, Italy, in He received the Laurea degree in electronics engineering and the Ph.D. degree in electrical engineering from the University of Catania, Catania, Italy, in 1997 and 2001, respectively. In 2002, he joined the Dipartimento di Ingegneria dell Informazione (DII), University of Siena, Siena, Italy, as a Research Associate and also as an Assistant Professor. In 2006, he became an Associate Professor in the same faculty. Since 2001 he has been teaching undergraduate and graduate courses on basic electronics, microelectronics, and advanced VLSI digital design. He has authored or co-authored about 80 referred international journals (more than 30) and conference papers. He is co-author of the book Model and Design of Bipolar and MOS Current-Mode Logic: CML, ECL and SCL Digital Circuits (Springer, 2005). His primary research interests include the modeling and optimized design of bipolar and CMOS high-performance digital circuits in terms of high-speed or low-power dissipation, as well as arithmetic circuits and circuits for cryptographic applications. Gaetano Palumbo (SM 98) was born in Catania, Italy, in He received the Laurea degree in electrical engineering and the Ph.D. degree from the University of Catania, Catania, Italy, in 1988 and 1993, respectively. Since 1993, he has been conducting courses on electronic devices, electronics for digital systems, and basic electronics. In 1994, he joined the Dipartimento Elettrico Elettronico e Sistemistico (DEES), now Dipartimento di Ingegneria Elettrica Elettronica e dei Sistemi (DIEES), University of Catania as a Researcher, subsequently becoming Associate Professor in Since 2000, he has been a Full Professor in the same department. His primary research interest has been analog circuits with particular emphasis on feedback circuits, compensation techniques, current-mode approach, low-voltage circuits. His research has also embraced digital circuits with emphasis on bipolar and MOS current-mode digital circuits, adiabatic circuits, and high-performance building blocks focused on achieving optimum speed within the constraint of low power operation. In all these fields he is developing some research activities in collaboration with STMicroelectronics of Catania. He was the co-author of three books: CMOS Current Amplifiers (Kluwer, 1999), Feedback Amplifiers: Theory and Design (Kluwer, 2001), and Model and Design of Bipolar and MOS Current-Mode Logic (CML, ECL, and SCL Digital Circuits) (Kluwer, 2005), and a textbook on electronic devices in He is a contributor to the Wiley Encyclopedia of Electrical and Electronics Engineering. He is the author of more than 300 scientific papers on referred international journals (almost 120 international journals) and in conferences. Moreover, he is co-author of several patents. Dr. Palumbo served as an Associated Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS for the topic Analog Circuits and Filters and digital circuits and systems, respectively, since June 1999 to the end of 2001 and from 2004 to Since 2006, he has served as an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS. In 2005 he was a panelist in the Scientific-Disciplinare area 09 industrial and information engineering of the CIVR (Committee for Evaluation of Italian Research), which evaluates the Italian research in this area for the period of 2001 to In 2003, he received the Darlington Award.