Current Based Delay Models: A Must For Nanometer Timing

Transcription

1 Current Based Delay Models: A Must For Nanometer Timing Ratnakar Goyal rgoyal@cadence.com Naresh Kumar nkumar@cadence.com Cadence Design Systems, Inc. Abstract In order to accurately account for nanometer effects during timing analysis, traditional cell models must be replaced. The assumption of linear input voltages and lumped output load are no longer valid [1]. The existing cell delay models do not match well with the advanced interconnect delay models. Interconnect models consume linear voltage waveforms produced by these cell models and produce voltage waveforms for consumption by downstream cell models. Further, the arbitrary waveforms produced by these interconnect models are linearized for consumption by cell models. Current based delay models circumvent this problem and provide a cell delay model which can both produce and consume nonlinear current/voltage waveforms. Keywords Interconnect Delay, Driver Model, Receiver Model, Voltage Source, Current Source, IR Drop, Delay Calculation, and Signal Integrity 1. Introduction Transistor drive capability and input capacitance are becoming more complex and non-linear at nanometer geometries. Computing the response of a gate and the interconnect it drives, is challenging, particularly for highly resistive nets. In addition, delay and slew of signals are dependent on many variables. For example, voltage drop from non-ideal power networks can degrade performance significantly [2]. Low power design styles incorporate two or more islands of logic, each running at a different operating voltage and the contemporary delay models fail to meet the modeling requirements of these design methodologies. Low power designs at 90nm have introduced new challenges for timing and delay calculation to support design styles that include [3]: multiple supplies to single instance (level shifters) cells used with different supplies (voltage islands) lower supply voltages to save power, but with increased sensitivity to IR drop and signal integrity. Different solutions have been proposed to overcome the challenges posed by these process and design styles. Liberty forum proposed Scalable Polynomial Delay Model (SPDM) whereas Cadence came up with Effective Current Source Model (ECSM). Recently, in the release, Liberty announced the support for Composite Current Source Model (CCS). Section 2 discusses in detail the limitations of traditional delay models. In the same section we will also describe how current models overcome these limitations for nanometer designs. Section 3 describes the characterization of current models. Section 4.1 discusses more about ECSM models and about CCS models are discussed in section 4.2. Section 5 presents a comparison of ECSM, SPDM and CCS models. Sections 6 presents the details of a comparitive study between SPICE and ECSM models. The paper concludes with a Summary section. 2. Why Current Based Models? In this section we will describe in detail the cell modeling requirements for accurate delay calculation, for the nanometer design regime and why do the traditional cell models fail to meet the modeling requirements at these geometries. 2.1 Delay Calculation Delay Calculation involves the calculation cell delay and interconnect delay. The delay calculator also computes the slew at the cell input and output pins. The delay and slew values are dependant on the cell model provided to the delay calculator, network topology and boundary conditions. Delay Calculation forms the heart of Static Timing Analysis (STA). Signal Integrity Analysis (SI) also depends on the results of delay calculation for

2 accurate generation of Timing Windows used for SI Analysis. It is thus important to have an accurate Delay Calculator which can produce results which are close to the actual delays produced using SPICE simulation. It is worth noting that delay calculation itself is dependent on the cell delay models. The most widely available cell models have been the table lookup models. These models when indexed by the input slew and the effective load capacitance produce delay and slew numbers at the output of the cell. More accurate, but less commonly available models have been proposed, such as the linear timevarying voltage source and associated resistance proposed in [4]. In [5] the authors extend the Thevenin model of [4] to accurately model the nonlinear tails exhibited when driving highly resistive interconnect. Though such cell models are not available in the delay models provided by the ASIC library vendor, different delay calculation tools have used the table lookup models to derive models which are close to those described in [5] and produced numbers which are close to SPICE for 130nm technology. However, at 90nm the interconnect delay dominates. There are three primary effects Wiring delay accounts for 75% of the overall delay [6] Interconnect delay calculation needs to more accurate. Interconnect resistance can become several Kilo- Ohms. This renders the existing models unsuitable for use at these geometries. The waveforms are becoming highly non-linear, due to high shielding resistance offered by long interconnects the cell models should provide the capability of modeling the waveforms rather than relying on the waveform generated by delay calculation engines using the existing models. Because of these effects, the models described in [4] are becoming ineffective. To understand this, let s look at relationship between input and output voltage: Vout(s)/Vin(s) = Z(s)/[Z(s)+R] where Z(s) is the impedance of the load seen by the cell and R is the equivalent Thevenin Resistance of the cell model described in [4]. For Z(s)>>R, these models tend to produce an output waveform which is the same as input waveform and the output load has no effect on the cell response. This, however, is very different from the actual waveforms produced in reality. Long interconnects which cause high load impedance also add to the non-linearity of the output waveform. Standard models, which assume ramp -like behavior, cannot handle these effects. Current models, on the other hand, model the driver as voltage-controlled current source [7] and thus do not suffer from the same shortcoming as voltage driver models. One may argue that a voltagecontrolled voltage source model can be converted into an equivalent voltage-controlled current source model and hence there should be no need for a new library cell delay model. It is, however, important to note that actual issue is not current or voltage models but it is the fact that the non-linear aspects of the input-output relationship are not maintained in the traditional ASIC libraries. Ief f ts Ief f V(y), I(y) C Ief f Figure 1: Voltage based driver model and current based driver models. A current model represents the output current waveform as a set of (current, time) pair. A different waveform is represented for each pair of input slew and output load combination. The current waveforms can be interpolated to determine the response of the cell for load and/or slew values which are not found in the characterized current model. These models help the delay calculator to accurately compute the non-linear cell output waveform. This non-linear waveform can be used to: accurately compute the gate delay accurately computation of interconnect delay precisely compute the waveform at the input of the receiving cell. Delay calculation depends on: The input-output waveform The load seen by the driver cell. The load seen by the driver depends on the pin capacitances of the receiver cell(s) and the interconnect network between the driver and driven cells. Existing cell models support only a single value of pin capacitance (a separate capacitance value can

3 be specified for rise and fall transitions). However, this single value of capacitance turns out to be insufficient for nanometer designs. The assumption of a single value of capacitance is no longer valid. Pin capacitance needs to be modeled as a function of slew arriving and the input pin and the load at the output of the receiver cell. Pin capacitance can be modeled at arc level in the timing library. For inputs which do not have any arc to an output pin, the capacitance needs to be modeled as a function of input slew only (as there is no associated load for such pins) and is modeled at the pin level. For example, the input (D) pin of a flip-flop does not have any outgoing arc. The new receiver model supports this type of modeling and also takes into account the effect of Miller capacitance. Delay calculation needs to use this model for accurate waveform construction at the receiver pin, especially when the waveforms are highly non-linear at 90nm. 2.2 Variable Voltage Design/IR Drop Analysis In order to optimize a design using multiple variable supplies, the timing of the design must be analyzed with each permissible combination of voltage ranges. Traditionally, to accurately model cell delays for a particular voltage level to within a few percent of SPICE, characterized timing views for that voltage level must be created. The problem with this approach is that it requires extensive, costly characterization. For example, to utilize six different voltage levels at three different process/temperature corners requires 18 separate timing library characterizations [7]. Even if the delay calculator can utilize timing views for all required voltage levels, an error is still incurred for any cell with an operating voltage falling between the characterized supply levels. This situation can occur, for example, due to voltage variation in the power rails (IR drop) caused by simultaneous switching of I/Os, clocks, and on chip devices. The existing lookup based models do not provide a good means of the calculating the effect of IR drop on cell delay, because of the limited capability of modeling the variation in delay as a linear function (using k-factor derating functions) of voltage variation. 1.2E E E E E E E Figure 2: Accurate non-linear IR drop using current modeling on delay versus k -factor derating On the other hand, current based models characterized for two or more different voltages have been successfully used to model the relationship between voltage and delay through non-linear interpolation. 2.3 Signal Integrity Analysis K-factor derating As already described in section 2.1, SI analysis depends on the Timing Window File (TWF) generated by the STA tool. TWF contains information about the switching window and transition times. As current based models lead to accurate delay calculation, we also get more accurate TWF and thus more accurate SI analysis. 3. Characterization of Current Based Delay Models Current based models can be generated using the same infrastructure as that used for lookup based cell models. The additional requirement is to measure and record the input and output waveforms for both current and/or voltage while characterizing the cell delay and slew values. Once the I/V (Current/Voltage) waveforms are available at the input and output of the cell, these can be easily represented in any of the formats like ECSM and CCS. 4. Industry Formats for Current Delay Models In this section, we will describe industry formats which cater to the modeling needs of nanometer designs.

4 4.1 Effective Current Source Model (ECSM) ECSM provides all the features wh ich are required of a current based delay model (described in detail in the proceeding sections). The advantages of ECSM which include: Accurate modeling of nanometer timing, including supply voltage variation Easy characterization. Characterization software from Magma and Cadence. Broad library support from vendors such as Artisan, TSMC and Virtual Silicon. Chip design software in Cadence SoC Encounter and Magma Blast Fusion. Production proven on 120+ tape outs Initially ECSM was represented in SignalStorm proprietary binary format, more commonly known as ipdb (intellectual property data base). However, as of today ECSM can be represented as a property field inside.lib file (as Liberty extensions for ECSM). This means that existing tools which do not support ECSM but do comply with the.lib standard are ECSM -compatible, although are not as accurate. the circuit. ECSM models are traditionally generated by SignalStorm s library characterization (SLC) tool and stored directly in a SignalStorm database (ipdb). The next section describes, in brief, how ECSM information can be derived from a generic characterization flow and stored in a traditional library file Representing ECSM in Liberty ECSM is stored in the form of output voltage waveforms. Given that the transition table is based on input slew rate and output loading capacitance and that the delay model uses a lumped capacitance to represent the observed loading, the output current (I out ) can be computed using the following equation: C t 2 ECSM(t 1, t 2 ) = load Vout t) dt 2 V(y) V(y) t1 ( / t t 1 I(y) I(y) Time time Figure 4: Relationship between current-voltage and voltage-time waveforms. Figure 3: ECSM data for a single slew value Cadence s nanometer signoff delay calculation tool, SignalStorm, uses ECSM driver model to represent the effect of non-linear switching waveforms on cellbased interconnect delay calculation and signal integrity. The ECSM database enables the delay calculator to utilize detailed driver current-voltage characteristics rather than relying on reverseengineered driver output waveforms derived from the delay and slew tables. It provides an efficient mechanism for storing output current or voltage profiles during active transitions on Using this equation, the output voltage waveform can be converted to ECSM. To support multiple supply voltage corners, the output voltage numbers need to be normalized from 0.0 to 1.0 of the supply voltage. The effective current also needs to be normalized to the supply voltage. With the output voltage waveform approach, the ECSM extension in Liberty is a table of voltage over transition times for every input slew and output loading capacitance index combination Formatting ECSM in Liberty Two groups are added to the Liberty specification to define the ECSM driver model: ecsm_waveform ecsm_waveform_set

5 These groups allow the creation of output voltage waveforms as a function of time and are placed within the rise_transition or fall_transition groups within a timing group. The ecsm_waveform and ecsm_waveform_set extensions are described by the following Liberty constructs: define_group(ecsm_waveform, rise_transition); define_group(ecsm_waveform_set, rise_transition); define_group(ecsm_waveform, fall_transition); define_group(ecsm_waveform_set, fall_transition); define( index_1, ecsm_waveform, string ); define( values, ecsm_waveform, string ); define( values, ecsm_waveform_set, string ); In addition, ecsm_waveform_set must be named using a reference to a template similar to other nonlinear delay model (NLDM) tables in Liberty: define_group( ecsm_lut_template, library ); define( variable_1, ecsm_lut_template, string ); define( index_1, ecsm_lut_template, string ); The ecsm_waveform and ecsm_waveform_set groups are alternate ways of describing the output rise or fall voltage waveform during a transition. provides a more compact model, although all waveforms must be represented with the same number of sample points. The ecsm_lut_template defines the points at which the output voltage is sampled, allowing the sample points to be overridden, if required, within the ecsm_waveform_set group. All the attributes associated with the timing group in which the rise_transition or fall_transition group resides are associated with the ecsm_waveform or ecsm_waveform_set groups, including attributes such as related_pin, timing_sense, and timing_type ECSM Receiver Model The ecsm_capacitance group describes the input capacitance during the rise or fall transition. It can be defined either at pin level or arc level. The following constructs are defined at library level in the.lib file. define_group(ecsm_capacitance, rise_transition); define_group(ecsm_capacitance, fall_transition); define_group(ecsm_capacitance. pin); define(index_1, ecsm_capacitance, string); define(values, ecsm_capacitance, string); 4.2 CCS Features and Format Liberty format has now come up with very similar modeling to Cadence's ECSM, called Composite Current Source (CCS). The CCS technology includes a current-based driver model and a receiver model to provide accurate delay calculation and signal integrity analysis. Figure5: ECSM waveform representation in.lib The ecsm_waveform group allows the output voltage waveforms to be specified separately for each index permutation suggested by the slew and load indexes. It also allows each waveform to be sampled at different points so that waveforms that are predominantly linear can be represented with fewer sample points. The ecsm_waveform_set group allows output voltage waveforms for all index permutations to be stored in the same group. All waveforms are assumed to be sampled at the same output voltage values. This Representing CCS in Liberty Following is the list of constructs supported in Liberty for CCS modeling output_current_template at library level. output_current_rise and output_current_fall at timing arc level receiver_capacitance at pin level receiver_capaciatnce1_rise, receiver_capacitance1_fall, receiver_capacitance2_rise, receiver_capacitance2_fall at timing arc level.

6 More details on the usage of these constructs can be found in the Liberty reference manual. 5. Comparison between different Industry Formats 5.1 Comparison between ECSM and SPDM SPDM is a mathematical model which represents the delay and slew values as a function of voltage and temperature in addition to the parameters of a lookup model. SPDM is a polynomial abstract, with multiple coefficients relating timing to a variety of inputs. SPDM requires elaborate curve fitting techniques for an accurate curve fit. However, an exact fit curve can lead to large number of co-efficient. Large number of co-efficient can cause runtime bottleneck when these large polynomials are evaluated. Inaccurate curve fitting and need for a new characterization setup has made SPDM unpopular with library vendors and designers. It also increases the characterization time 10x over NLDM and decreases the accuracy for a nominal single voltage case. ECSM, on the hand models a unique dataset for each voltage-temperature combination. Given ECSM data characterized for three voltage corners, SignalStorm delay calculator can accurately compute the delay for any other voltage by using non-linear interpolation of the 3 sets of data. The same also holds true while computing the effect of IR drop on delay. ECSM does not require any additional characterization methodology and increases the characterization time only 3x. 5.2 Comparison between ECSM and CCS CCS was released in the release of Liberty and as of today (July 2005) there is no available commercial library support from any library vendor. Further, there is no available characterization tool for CCS characterization. CCS is supported by PrimeTime but there is no flow support in implementation tools. Further there is no information about Multiple Supply Voltage or IR drop for CCS. On the other hand, ECSM has been there since 2001 and has well defined characterization flows from Cadence and Magma for the same. ECSM is supported in various Cadence tools and flows and also in Magma s BlastFusion tool. ECSM libraries are readily available from Library vendors like Artisan, TSMC, Virage Logic and Virtual Silicon. characterization challenges in directly measuring current as required in CCS. Also, there is no errorcontrol of i(t) in Spice-like simulators in the CCS flow. 6. Study of ECSM Accuracy versus SPICE using Variable Voltage Levels To verify the accuracy of ECSM delay models at different voltage levels, Artisan and Cadence performed qualification using the Artisan SAGE-X standard cell library for TSMC s 130 nm CL013G process, and measured delays against SPICE while varying voltage, slew, and load. Five cells were chosen to undergo detailed examination: three simple logic gates (BUFX2, NOR3X1, NAND2X1) and two complex cells (DFFX2, AFCSHCINX2). DFFX2 is a positive edge triggered D flip -flop and AFCSHCINX2 implements a carry-select adder function that produces the arithmetic sum (S) and carry-outs (CO0, CO1) of the operands (A, B) with active-low carry-ins (CI0N, CI1N). ECSM data was characterized: At three voltage levels (0.7V, 0.9V, and 1.08V, nominal voltage). For the slow process corner at 125 o C. Cell delays reported by SignalStorm NDC were measured using six voltage levels (0.7V, 0.8V, 0.9V, 1V, 1.08V, and 1.2V), and the results compared with SPICE simulations. Each cell was subject to Three different input slews:.042ns (min), 0.206ns(mid), and 1.5ns (max). Three different loads: 1.58fF(min), fF(mid), and fF(max). 6.1 Results The average difference between ECSM and SPICE for all the cells, across all voltage ranges, slews, and loads was 0.5% with a standard deviation of 0.63%. The distribution from all of the results is shown in Figure 6. It should be noted that though the formats are similar, ECSM is easy to characterize whereas there are

7 Accuracy % ECSM Vs Spice % -1.5% 0.5% 2.5% 4.5% -20 Figure 6: Distribution of delay error, ECSM vs. SPICE all cells, voltages, slews, and loads. Average difference is 0.5 and standard deviation of 0.63 The worst-case error (5.38%) occurred using the NAND2X1 cell with a 1.2V supply, a 1.5ns input slew, and a 1.58fF load. The absolute delay difference for this case was 3ps (ECSM predicted 48ps; SPICE predicted 45ps). Figure 8: ECSM vs. SPICE for BUFX2, output rising transition, all voltage levels, slews, loads A comparison for a complex cell (AFCSHCINX2) measuring falling transitions across all voltage levels for different slews and loads is shown in Figure 9. The accuracy of the ECSM model is valid for both simple and complex cell types and was bounded for all cell types, for both rise and fall transitions at all voltage levels. A comparison based on cell type for the midrange slew (0.206ns) and midrange load (20.224fF) is shown in Figure 7. Figure 9: ECSM vs. SPICE for AFCSHCINX2, output falling transition, all voltage levels, slews, loads Summary Figure 7 : ECSM vs. SPICE for different cell types and all voltage levels, using midrange slew and midrange load The accuracy of the ECSM model is valid across a wide range of slews and loads as well as voltage levels. A comparison for a simple cell (BUFX2) measuring rising transitions across all voltage levels for different slews and loads is shown in Figure 8. In this paper, we looked at the cell modeling challenges for the nanometer design regime. We discussed in detail about current based delay models and how they meet the nanometer design challenges. We also discussed the ECSM and CCS models. We found that though both ECSM and CCS provide similar modeling capabilities, CCS characterization has the limitations related to fast and accurate current measurement. We conclude this section with the following salient points about ECSM: Customer acceptance for ECSM as a sign-off quality. Large experience in characterization and usage. SignalStorm is the default delay calculation based on ECSM. Production proven on 120+tapeouts. Acknowledgements We acknowledge special thanks to Rahul Deokar and Vassilios Gerousis for providing their inputs on this

8 paper work. We are also thankful to Prashant Sethia, Parveen Khurana and Harindranath Parmeswaran for their guidance. References: [1] John F. Croix and D.F.Wong: Blade and Razor: Cell and Interconnect Delay Analysis Using Current- Based Models. IEEE/ACM DAC 2003 proceedings. [2] CCS offers advanced delay calculation methodology EETimes Oct [3] ECSM sets new standard for timing model accuracy EETimes Oct [4] F. Dartu, N.Menezes, J. Qian, and L.T.Pilage: A gate-delay model for high speed CMOS circuits. IEEE/ACM DAC 1994 proceedings. [5] F. Dartu, N.Menezes, and L.T.Pilage Performance computation of precharacterized CMOS gates with RC loads. IEEE/ACM DAC 1996 proceedings. [6] SignalStorm NDC [7] Accurate Multi-Voltage Delay Analysis ( [8] United States Patent: High accuracy timing model for integrated circuit verification, Li, et al. [9] ECSM Library Format( [10] Liberty Reference Manual. [11] SignalStorm ( [12] SignalStorm Nanometer Delay Calculator( [13] Timing models present another standards test( [14] EDA vendors spar over current-source modeling(