CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer

Transcription

1 9-57; Rev ; 6/7 EVALUATION KIT AVAILABLE CDMA IF VGAs and I/Q Demodulators General Description The MA3/MA3/MA34/MA36 are IF receivers designed for dual-band, dual-mode, and single-mode N-CDMA and W-CDMA cellular phone systems. The signal path consists of a variable gain amplifier (VGA) and I/Q demodulator. The devices feature guaranteed +.7V operation, a dynamic range of over db, and high input IP3 (-33dBm at 35dB gain,.7dbm at -35dB). Unlike similar devices, the MA3 family of receivers includes dual oscillators and synthesizers to form a self-contained IF subsystem. The synthesizer s reference and RF dividers are fully programmable through a 3-wire serial bus, enabling dual-band system architectures using any common reference and IF frequency. The differential baseband outputs have enough bandwidth to suit both N-CDMA and W-CDMA systems, and offer saturated output levels of.7vp-p at a low +.75V supply voltage. Including the low-noise voltage-controlled oscillator (VCO) and synthesizer, the MA3 draws only 6mA from a +.75V supply in CDMA (differential IF) mode. The MA3/MA3/MA34/MA36 are available in 8-pin QSOP packages. Applications Single/Dual/Triple-Mode CDMA Handsets Globalstar Dual-Mode Handsets Wireless Data Links Tetra Direct-Conversion Receivers Wireless Local Loop (WLL) PART MA3 MODE AMPS, Cellular CDMA, PCS CDMA Features Complete IF Subsystem Includes VCO and Synthesizer Supports Dual-Band, Triple-Mode Operation VGA with >db Gain Control Quadrature Demodulator High Output Level (.7V) Programmable Charge-Pump Current Supports Any IF Frequency Between 4MHz and 3MHz 3-Wire Programmable Interface Low Supply Voltage (+.7V) PART MA3EEI MA3EEI MA34EEI MA36EEI Ordering Information TEMP RANGE -4 C to +85 C -4 C to +85 C -4 C to +85 C -4 C to +85 C Pin Configurations appear at end of data sheet. Block Diagram appears at end of data sheet. DESCRIPTION Dual Band, Triple Mode PIN-PACKAGE 8 QSOP 8 QSOP 8 QSOP 8 QSOP Selector Guide INPUT RANGE 4MHz to 3MHz MA3/MA3/MA34/MA36 MA3 PCS CDMA Single Band, Single Mode 67MHz to 3MHz MA34 AMPS, Cellular CDMA Single Band, Dual Mode 4MHz to 5MHz MA36 Cellular CDMA Single Band, Single Mode or Single Band, Dual Mode with External Discriminator 4MHz to 5MHz Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at , or visit Maxim s website at

2 MA3/MA3/MA34/MA36 ABSOLUTE MAIMUM RATINGS to...-.3v, +6.V to...-.3v to ( +.3V), BUFEN, MODE, EN, DATA, CLK, DIVSEL...-.3V to ( +.3V) VGC to...-.3v, the lesser of +4.V or ( +.3V) AC Signals TankH ±, TankL ±, REF, FM ±, CDMA ±...V peak Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS ( = +.7V to +5.5V, MODE = DIVSEL = = = BUFEN = high, differential output load = kω, T A = -4 C to +85 C, registers set to default power-up settings. Typical values are at = +.75V and T A = +5 C, unless otherwise noted.) PARAMETER Supply Current (Note ) Shutdown Current Register Shutdown Current Logic High Logic Low Logic High Input Current Logic Low Input Current VGC Control Input Current VGC Control Input Current During Shutdown Lock Indicator High (locked) Lock Indicator Low (unlocked) DC Offset Voltage Common-Mode Output Voltage SYMBOL I CC I CC I CC I CC I IH I IL = low 5kΩ load 5kΩ load I+ to I- and Q+ to Q-, PLL locked =.75V Digital Input Current, MODE, DIVSEL, BUFEN, DATA, CLK, EN,...±mA Continuous Power Dissipation (T A = +7 C) 8-pin QSOP (derate mw/ C above T A = +7 C)...8mW Operating Temperature Range...-4 C to +85 C Junction Temperature...+5 C Storage Temperature Range C to +6 C Lead Temperature (soldering, s)...+3 C CONDITIONS CDMA mode T A = +5 C T A = -4 C to +85 C FM IQ mode T A = +5 C T A = -4 C to +85 C FM I mode T A = +5 C T A = -4 C to +85 C STANDBY (VCO_H) T A = +5 C T A = -4 C to +85 C STANDBY (VCO_L) T A = +5 C T A = -4 C to +85 C MIN TYP MA Addition for LO out (BUFEN = low) 3.5 = low.5 µa ma. V.5 V µa µa.5v < V VGC <.3V -5 5 µa. - ± UNITS ma µa V V mv V

3 AC ELECTRICAL CHARACTERISTICS (MA3/MA34 or MA3/MA36 EV kit, = +.75V, registers set to default power-up states, f IN =.88MHz for CDMA, f IN = 85.88MHz for FM, f REF = 9.68MHz, synthesizer locked with passive nd-order lead-lag loop filter, = high, VGC set for +35dB voltage gain, differential output load = kω, all power levels referred to 5Ω, T A = +5 C, unless otherwise noted.) PARAMETER Input Frequency Reference Frequency Frequency Reference Signal Level SIGNAL PATH, CDMA MODE Input Third-Order Intercept Input db Compression Input.5dB Desensitization Minimum Voltage Gain Maximum Voltage Gain DSB Noise Figure SIGNAL PATH, FM_IQ MODE Input Third-Order Intercept Input db Compression Minimum Voltage Gain Maximum Voltage Gain SYMBOL f IN f REF V REF IIP3 P db A V A V NF IIP3 P db A V A V SIGNAL PATH, CDMA and FM_IQ MODE Maximum Gain Variation Over Temperature Baseband.5dB Bandwidth Quadrature Suppression LO to Baseband Leakage Saturated Output Level PHASE-LOCKED LOOP VCO Tune Range LOOUT Output Power V SAT f VCO_L f VCO_H P LO (Note ) (Note ) Gain = -35dB (Note 3) Gain = +35dB (Note 4) Gain = -35dB Gain = +35dB (Note 5) V GC =.5V (Note 6) V GC =.3V (Note 6) Gain = -35dB Gain = +35dB (Note 7) (Notes 6, 8) V GC =.5V (Note 6) V GC =.3V (Note 6) Normalized to +5 C Differential CONDITIONS T A = T MIN to T MA (Note 6) (Note ) R L = 5Ω, BUFEN = low Gain = -35dB Gain = +35dB Gain = -35dB Gain = +35dB Gain = -35dB Gain = +35dB MIN TYP MA ± UNITS MHz MHz Vp-p dbm dbm dbm db db db dbm dbm db db db MHz db mvp-p Vp-p MHz dbm MA3/MA3/MA34/MA36 3

4 MA3/MA3/MA34/MA36 AC ELECTRICAL CHARACTERISTICS (continued) (MA3/MA34 or MA3/MA36 EV kit, = +.75V, registers set to default power-up states, f IN =.88MHz for CDMA, f IN = 85.88MHz for FM, f REF = 9.68MHz, synthesizer locked with passive nd-order lead-lag loop filter, = high, VGC set for +35dB voltage gain, differential output load = kω, all power levels referred to 5Ω, T A = +5 C, unless otherwise noted.) PARAMETER VCO Minimum Divide Ratio VCO Maximum Divide Ratio REF Minimum Divide Ratio REF Maximum Divide Ratio Minimum Phase Detector Comparison Frequency Maximum Phase Detector Comparison Frequency Base Band Spurious due to PLL LOOUT at 85MHz, VCO_L Enabled (Note 9) LOOUT at MHz, VCO_H Enabled (Note 9) Charge-Pump Source/Sink Current Charge-Pump Source/Sink Matching SYMBOL M, M M, M R, R R, R (Note 6) (Note 6) khz offset.5khz offset 3kHz offset khz offset 9kHz offset khz offset.5khz offset CONDITIONS 3kHz offset khz offset 9kHz offset Acquisition, CP =, TC = (Note ) Locked, CP = Locked, CP = Locked, CP = Locked, CP = Locked, all values of CP,.5V < V CP < -.5V MIN TYP MA Note : FM_IQ and FM_I modes are not available on MA3 and MA36. Note : Recommended operating frequency range. Note 3: f =.88MHz, f =.89MHz, P f = P f = -5dBm. Note 4: f =.88MHz, f =.89MHz, P f = P f = -5dBm. Note 5: Small-signal gain at khz below the LO frequency will be reduced by less than.5db when an interfering signal at.5mhz below the LO frequency is applied at the specified level. Note 6: Guaranteed by design and characterization. Note 7: f = 85.88MHz, f = 85.98MHz, P f = P f = -5dBm. Note 8: f = 85.88MHz, f = 85.98MHz, P f = P f = -5dBm. Note 9: Measured at LOOUT with BD = ( selected). Note : Not available on MA36. UNITS khz khz dbc dbc/hz dbc/hz µa % 4

5 Typical Operating Characteristics (MA3/MA34 or MA3/MA36 EV kit, = +.75V, registers set to default power-up states, f IN =.88MHz for CDMA, f IN = 85.88MHz for FM, f REF = 9.68MHz, synthesizer locked with passive nd-order lead-lag loop filter, = high, VGC set for +35dB voltage gain, differential output load = kω, all power levels referred to 5Ω, T A = +5 C, unless otherwise noted.) SUPPLY CURRENT (ma) GAIN (db) RECEIVE SUPPLY CURRENT vs. SUPPLY VOLTAGE T A = +85 C T A = +5 C T A = -4 C SUPPLY VOLTAGE (V) GAIN vs. INPUT FREQUENCY V GC =.5V FREQUENCY (MHz) NOISE FIGURE vs. GAIN MA3 toc MA3 toc4 MA3 toc7 SHUTDOWN CURRENT (ma) RELATIVE GAIN (db) RECEIVE SHUTDOWN CURRENT vs. SUPPLY VOLTAGE T A = +5 C T A = +85 C T A = -4 C SUPPLY VOLTAGE (V) GAIN vs. BASEBAND FREQUENCY FREQUENCY (MHz) NOISE FIGURE vs. TEMPERATURE MA3 toc MA3 toc5 MA3 toc8 GAIN (db) IIP3 (dbm) T A = +5 C T A = -4 C GAIN vs. V GC T A = +85 C V GC (V) THIRD-ORDER INPUT INTERCEPT vs. GAIN T A = -4 C T A = +5 C T A = +85 C GAIN (db) VCO VOLTAGE vs. TIME MA3 toc9 NA3 toc3 MA3 toc6 VCO VOLTAGE MA3/MA3/MA34/MA36 NF (db) 4 3 NF (db) VOLTS (V/div) LOCK GAIN (db) TEMPERATURE ( C) TIME (5μs/div) LOCK TIME.83ms 5

6 MA3/MA3/MA34/MA36 Typical Operating Characteristics (continued) (MA3/MA34 or MA3/MA36 EV kit, = +.75V, registers set to default power-up states, f IN =.88MHz for CDMA, f IN = 85.88MHz for FM, f REF = 9.68MHz, synthesizer locked with passive nd-order lead-lag loop filter, = high, VGC set for +35dB voltage gain, differential output load = kω, all power levels referred to 5Ω, T A = +5 C, unless otherwise noted.) MA3 3 4, 5 FM PORT S vs. FREQUENCY 4 3 MA3 toc : 64 - j48 MHz : 7 - j6 85MHz 3: 4 - j73 MHz 4:.8 - j39 6MHz LOOUT PORT S vs. FREQUENCY PIN MA3 MA MA3 toc3 MA36 TANKL PORT /S vs. FREQUENCY : 8.63Ω (Re).66Ω (m) 4MHz : 34.99Ω (Re) 3.7Ω (m) 5MHz 3: 58.83Ω (Re) 39.58Ω (m) 3MHz NAME, MA3 toc : -3.6ms + j349μs, MHz : -3.ms + j853μs, 6MHz 3: -3.ms + j.45ms, 4MHz 4: -3.4ms + j.85ms, 3MHz CP_OUT Charge-Pump Output 3 3 Analog Ground Reference 4, 5 5, 6 TANKL+, TANKL- CDMA PORT S vs. FREQUENCY 4 TANKH PORT /S vs. FREQUENCY FUNCTION 3 MA3 toc4 4 3 : MHz, 375Ω - j56ω : 85MHz, 85Ω - jω 3: MHz, 73Ω - j69ω 4: 6MHz,.Ω - j34ω Pin Description Bypass Node. Must be capacitively decoupled (bypassed) to analog ground. Differential Tank Input for Low-Frequency Oscillator 4 DIVSEL High selects M/R; low selects M/R. MA3 toc :.98ms + j437µs, MHz :.8ms + j853µs, 6MHz 3:.ms +j.53ms, 4MHz 4:.7ms +j 3.7ms, 6MHz 6

7 8 3, 4 3, , 7 6, CLK Clock input of the 3-wire serial bus 7, 8 7, 8 PIN MA3 MA3 MA34 MA36 8 3, 4 3, , 7 6, 7 7, 8 7, 8 NAME LOOUT REF Reference Frequency Input IOUT+, IOUT- LOCK QOUT-, QOUT+ Pin Description (continued) FUNCTION 7 7 BUFEN LO Buffer Amplifier active low 6, 7 N.C. No Connection. Must be left open-circuit. 8 MODE Mode Select. High selects CDMA mode; low selects FM mode. Internal VCO Output. Depending on setting of BD bit, LOOUT is either the VCO frequency (twice the IF frequency) or onehalf the VCO frequency (equal to the IF frequency) V to +5.5V Supply for Digital Circuits Digital Ground Shutdown Input active low. Low powers down entire device, including registers and serial interface. Differential In-Phase Baseband Output, or FM signal output FM_I mode is selected. Lock Output open-collector pin. Logic high indicates phaselocked condition. Differential Quadrature-Phase Baseband Output. Disabled if FM_I mode is selected EN Enable Input. When low, input shift register is enabled. DATA Data input of the 3-wire serial bus..7v to 5.5V Supply for Analog Circuits VGC VGA Gain Control Input. Control voltage range is.5v to.3v. CDMA-, 3, 4 3, 4 3, 4 3, 4 Differential CDMA Input. Active in CDMA mode. CDMA+ 5 5 FM+ Differential Positive Input. Active in FM mode. 5 5 N.C. No Connection TANKH+, 6, 7 5, 6 Differential Tank Input for High-Frequency Oscillator TANKH- FM- Differential Negative Input for FM signal. Bypass to for single-ended operation. Standby Input active low. Low powers down VGA and demodulator while keeping VCO, PLL, and serial bus on. Bypass Node. Must be capacitively decoupled (bypassed) to analog. MA3/MA3/MA34/MA36 7

8 MA3/MA3/MA34/MA36 kω.33μf kω kω kω kω I 3.3nF 8pF 5pF 8pF pf.5pf pf.μf 68nH 8nH kω CPOUT FM- FM+ TANKL+ CDMA+ MA3 TANKL- CDMA- TANKH+ VGC TANKH- MODE DATA EN CLK REF IOUT+ QOUT+ IOUT- QOUT- LOCK.μF.μF.μF 68Ω 3-WIRE kω 47kΩ FM CDMA DAC Q Figure. MA3 Typical Operating Circuit Detailed Description MA3 The MA3 is intended for dual-band (PCS and cellular) and dual-mode code division multiple access (CDMA) and FM applications (Figure ). The device includes an IF variable-gain amplifier, quadrature demodulator, dual VCOs, and dual-frequency synthesizers (Figure 7). Dual VCOs are provided for applications using different IF frequencies for each mode or band of operation. The analog FM output signal can be configured for conversion to the I channel, or it may be converted in quadrature to both the I and Q channels. The MA3 s operation modes are described in Table. These modes are set by programming the control register and setting logic levels on control pins. If MODE is left floating, the internal register controls the operation. If driven high or low, mode will override certain register bits, as shown in Table. 8

9 Table. MA3 Control Register States OPERATIONAL MODE ACTION RESULT MA3/MA36 The MA3/MA36 quadrature demodulators are simplified versions of the MA3 that can be used in single-mode CDMA or dual mode using an external FM discriminator (Figures a and b). The MA3 VCO is optimized for the 67MHz to 3MHz IF frequency range, while the MA36 VCO is optimized for the 4MHz to 5MHz IF frequency range. Both devices include a buffered output for the VCO. The buffered VCO output can be used to support systems implementing traditional limiting IF stages for FM demodulation in dual-mode phones as well as for the transmit LO in TDD systems. This buffered output can PINS MODE M M L S CONTROL SB REGISTER S B B SHUTDOWN Shutdown pin completely powers down the chip L SHUTDOWN in shutdown register bit leaves serial port active H STANDBY in standby register bit turns off VGA and modulator only Mode pin overrides VCO_SEL, DIVSEL, and IN_SEL to high Floating mode pin returns control to register Mode pin overrides VCO_SEL, DIVSEL, and IN_SEL to low Floating mode pin returns control to register Mode pin overrides VCO_SEL, DIVSEL, and IN_SEL to low Floating pins return control to register H TEST_MODE CP POL TEST_EN TURBOCHARGE DIVSEL VCO_ VCO_SEL be configured for the VCO frequency (twice the IF frequency) or one-half the VCO frequency (IF frequency). The BUFEN pin enables this feature. A standby mode, in which only the VCO and synthesizer are operational, can be selected through the serial interface or the pin. The MA3/MA36s operational modes are described in Table. These modes are set by programming the control register and/or setting logic levels on control pins. If the control pins (, BUFEN, DIVSEL) are left floating, the internal register controls the operational mode. If driven high or low, the control pins will override certain register bits, as shown in Table. BUF_DIV BUFEN FM_TYPE IN_SEL CDMA H H CDMA H F FM_IQ H L FM_IQ H F FM_I H L FM_I Note: H = high, L = low, F = floating pin, = don t care, Blank = independent parameter, = logic high, = logic low. H L F MA3/MA3/MA34/MA36 9

10 MA3/MA3/MA34/MA36 kω.μf.33μf 33pF kω pf.5pf 8nH kω pf I kω Figure a. MA3 Typical Operating Circuit CPOUT DIVSEL TANKH+ CDMA+ MA3 TANKH- CDMA- BUFEN VGC LOOUT DATA REF EN CLK IOUT+ QOUT+ IOUT- QOUT- LOCK.μF.μF 68Ω 3-WIRE kω 47kΩ CDMA DAC Q

11 .33μF kω 33pF kω 7pF 5pF kω 8pF DISCRIMINATOR 455kHz LIMITER I FM Figure b. MA36 Typical Operating Circuit.μF 68nH kω CP_OUT DIVSEL TANKL+ CDMA+ MA36 TANKL- CDMA- BUFEN VGC LOOUT DATA REF EN CLK IOUT+ QOUT+ IOUT- QOUT- LOCK.μF.μF 68Ω 3-WIRE kω 47kΩ CDMA DAC Q MA3/MA3/MA34/MA36

12 MA3/MA3/MA34/MA36 Table. MA3/MA36 Control Register States OPERATIONAL MODE SHUTDOWN SHUTDOWN STANDBY STANDBY DIVIDER SELECT DIVIDER SELECT LO BUFFER ENABLE LO BUFFER ENABLE ACTION RESULT Shutdown pin completely powers down the chip in shutdown register bit leaves serial bus active in standby pin turns off VGA and modulator only in standby register bit turns off VGA and modulator only DIV_SEL pin overrides DIV_SEL register bit If DIV_SEL pin is floated, then register bit selects divider BUFEN pin controls the LO buffer and overrides the bit If pin is floated, then BUFEN register bit controls buffer H H H/ L H DIVSEL H H/ L H H/ L PINS F BUFEN H H F L H H M L S CONTROL MSBREGISTER S B B TEST_MODE L H CP_POL TES_TEN TURBOCHARGE DIVSEL / VCO_ VCO_SEL BUF_DIV BUFEN / FM_TYPE IN_SEL Note: H = high, L = low, = logic high, = logic low, = don t care, blank = independent parameter.

13 kω.μf.33μf 33pF kω 8pF 5pF 68nH kω 8pF pf kω Figure 3. MA34 Typical Operating Circuit MA34 CP_OUT FM- TANKL+ FM+ CDMA+ TANKL- CDMA- VGC DATA REF EN CLK I_OUT+ Q_OUT+ I_OUT- Q_OUT- LOCK.μF.μF.μF 68Ω 3-WIRE kω 47kΩ CDMA DAC Q FM MA3/MA3/MA34/MA36 MA34 The MA34 supports CDMA cellular-band, dualmode operation. As with the MA3, the FM mode can be configured for conversion to the I port or quadrature conversion to both the I and Q ports (Figure 3). The MA34 s operational modes are described in Table 3. These modes are set by programming the control register and setting logic levels on control pins. Applications Information Variable-Gain Amplifier and Demodulator The MA3 family provides a Variable-Gain Amplifier (VGA) with exceptional gain range. The MA3/ MA34 support multimode applications with dual differential inputs, selectable with the IN_SEL (IS) control bit. On the MA3 this function can be controlled with the MODE pin, which overrides the IS control bit. The VGA s gain is controlled over a db range with 3

14 MA3/MA3/MA34/MA36 Table 3. MA34 Control Register States OPERATIONAL MODE SHUTDOWN SHUTDOWN STANDBY ACTION RESULT Shutdown pin completely shuts down chip in shutdown register bit leaves serial port active in standby pin turns off VGA and modulator only CDMA CDMA operation H FM_IQ FM IQ quadrature operation H FM_I FM I operation H Note: H = high, L = low, = logic high, = logic low, = don t care, blank = independent parameter the VGC pin. The output of the VGA drives the RF ports of a quadrature demodulator. The MA3/MA34 provide two types of FM demodulation, controlled by the FM_TYPE (FT) control bit. When FM_TYPE is, the signal is passed through both the I and Q signal paths for subsequent lowpass filtering and A/D conversion at baseband. If FM_TYPE is, the FM signal is passed through the I mixer only. Voltage-Controlled Oscillator, Buffers, and Quadrature Generation The LO signal for downconversion is provided by a voltage-controlled oscillator (VCO) consisting of an onchip differential oscillator, and an off-chip high-q resonant network. Figure 4 shows a simplified schematic of the VCO oscillator. Multiband operation is supported by the MA3 with dual VCOs. VCO_H and VCO_L are selectable with the MODE pin or the VCO_SEL (VS) P I N H M M L S CONTROL SREGISTER S B B B TEST_MODE CP_POL TEST_EN TURBOCHARGE L H DIVSEL VCO_ VCO_SEL control bit. They oscillate at twice the desired LO frequency. For applications requiring an external LO, the VCOs can be bypassed with the VCO_ (VB) control bit. The MA3/MA36 buffer the output of the VCO and provide this signal at the LOOUT pin. This signal is enabled by the BUFEN (BE) control bit or by the BUFEN control pin. The frequency of this signal is selected by the BUF_DIV (BD) control bit, and can be either the VCO frequency or half the VCO frequency. Quadrature downconversion is realized by providing inphase (I) and quadrature-phase (Q) components of the LO signal to the LO ports of the demodulator described above. The quadrature LO signals are generated by dividing the VCO output frequency using two latches. The appropriate latch outputs provide I and Q signals at the desired LO frequency. BUF_DIV BUFEN FM_TYPE IN_SEL L 4

15 Synthesizer The VCO s output frequency is controlled by an internal phase-locked-loop (PLL) dual-modulus synthesizer. The loop filter is off-chip to simplify loop design for emerging applications. The tunable resonant network is also off-chip for maximum Q and for system design flexibility. The VCO output frequency is divided down to the desired comparison frequency with the M counter. The M counter consists of a 4-bit A swallow counter and a -bit P counter. A reference signal is provided from an external source and is divided down to the comparison frequency with the R counter. The two divided signals are compared with a three-state digital phase-frequency detector. The phase-detector output drives a charge pump as well as lock-detect logic and turbocharge control logic. The charge pump output (CP_OUT) pin is processed by the loop filter and drives the tunable resonant network, altering the VCO frequency and closing the loop. Multimode applications are supported by two independent programmable registers each for the M counter (M, M), the R counter (R, R), and the charge-pump output current magnitude (CP, CP). The DIVSEL (DS) bit selects which set of registers is used. It can be overridden by the MA3 s MODE pin or the MA3/ MA36 s DIVSEL pin. Programming these registers is discussed in the 3-Wire Interface and Registers section. TANK+ R L C F R B D R 8μA R B C F R L TANK- When the part initially powers up or changes state, the synthesizer acquisition time can be reduced by using the Turbo feature, enabled by the TURBOCHARGE (TC) control bit. Turbo functionality provides a larger charge-pump current during acquisition mode. Once the VCO frequency is acquired, the charge-pump output current magnitude automatically returns to the preprogrammed state to maintain loop stability and minimize spurs in the VCO output signal. The lock detect output indicates when the PLL is locked with a logic high. 3-Wire Interface and Registers The MA3 family incorporates a 3-wire interface for synthesizer programming and device configuration (Figure 5). The 3-wire interface consists of a clock, data, and ENABLE. It controls the VCO dividers (M and M), reference frequency dividers (R and R), and a 3-bit control register. The control register is used to set up the operational modes (Table 4). The input shift is 7 data bits long and requires a total of 8 clock bits (Figure 6). A single clock pulse is required before enable drops low to initialize the data bus. Whenever the M or R divide register value is programmed and downloaded, the control register must also be subsequently updated. This prevents turbolock from going active when not desired. The control bit is notable because it differs from the pin. When the control bit is low, the registers and serial interface are left active, retaining the values stored in the latches, while the rest of the device is shut off. In contrast, the pin, when low, shuts down everything, including the registers and serial interface. See the functional diagram in Figure 7. Registers Figure 8 shows the programming logic. The 7-bit shift register is programmed by clocking in data at the rising edge of CLK. Before the shift register is able to accept data, it must be initialized by driving it with at least one full clock cycle at the CLK input with EN high (see Figure 6). Pulling enable low will allow data to be clocked into the shift register; pulling enable high loads the register addressed by A, A, and A, respectively (Figure 8). Table 5 lists the power-on default values of all registers. Table 6 lists the charge-pump current, depending on CP and CP. MA3/MA3/MA34/MA36 R E R E Figure 4. Voltage-Controlled Oscillators 5

16 MA3/MA3/MA34/MA36 VCO VCO M U DATA CLK EN Figure 5. 3-Wire Control Block Diagram DATA CLOCK * 3-BIT CONTROL REGISTER 4-BIT M COUNTER () START BIT 6-BIT DATA/ADDRESS REGISTER () MSB *SB () () () 4-BIT M COUNTER -BIT CP -BIT CP *START BIT MUST BE LOGIC HIGH. -BIT R COUNTER -BIT R COUNTER *RISE AND FALL REQUIRED PRIOR TO EN GOING LOW. CPI F REF CP LSB CPOUT ENABLE Figure 6. 3-Wire Interface Timing Diagram 6

17 SB MA3 MA3 MA34 MA36 CP CP SHIFT REGISTER M REGISTER M REGISTER R REGISTER R REGISTER TM POL TE TC DS VB VS BD BE FT IS SB SD REF CONTROL CDMA+ 4 4 R COUNTER POL Ø DET CHARGE PUMP 4 DIVSEL (MA3/6) DS 4 M COUNTER LOCK DET TURBO CONTROL MODE (MA3) TC IS VS VGC FT VCO_L VCO_H CDMA- LOGIC EN CLK (MA3/4) DATA FM+ FM- 4 IOUT+ IOUT- QOUT+ QOUT- TANKL+ TANKL- VB TANKH+ TANKH- LOCK MA3/MA3/MA34/MA36 BIAS LO_OUT (MA3/6) SB SD CP_OUT BD BE (MA3/6) BUFEN Figure 7. Functional Diagram 7

18 MA3/MA3/MA34/MA36 Table 4. Control Register, Default State: B57h, Address: b BIT ID POL TE TEST_ENABLE Must be for normal operation. TC DS DIV_SEL 8 Logic selects M/R divide ratios. Logic selects M/R. VS VCO_SEL 6 Logic selects VCO_H. Logic selects VCO_L. BD FT SB SD BIT NAME CP_POL TURBO_CHARGE BUF_DIV BE BUFEN 4 Logic disables LOOUT. Logic enables LOOUT. FM_TYPE Table 5. Register Defaults POWER- UP STATE VB VCO_ 7 Logic bypasses the VCO inputs for external VCO operation. 5 3 BIT LOCATION = LSB TM TEST_MODE Must be for normal operation. 9 FUNCTION Logic causes the charge-pump output CP_OUT to source current when f REF /R > f VCO /M. This state is used when the VCO tune polarity is such that increasing voltage produces increasing frequency. Logic causes CP_OUT to source current when f VCO /M > f REF /R. This state is used when increasing tune voltage causes the VCO frequency to decrease. Logic activates turbocharge mode, which provides rapid frequency acquisition in the PLL. Not available on MA36. Logic selects divide-by- on LOOUT port. Logic bypasses divider. Active in FM mode. Logic selects quadrature demodulator for FM mode. Logic selects downconversion to I port. IS IN_SEL Logic selects FM input port. Logic selects CDMA input. Logic enables standby mode, which shuts down the VGA and demodulator stages, leaving the VCO locked and the registers active. Logic enables register-based shutdown. This mode shuts down everything except the M and R latches and the serial bus. Table 6. Charge-Pump Control Bits REGISTER M M R R CTRL CP CP DEFAULT 59 DEC 469 DEC 49 DEC 49 DEC OB57 HE BIN BIN CP CP CHARGE-PUMP CURRENT AFTER ACQUISITION (µa)

19 SHIFT REGISTER M REGISTER M REGISTER CP AND R REGISTERS CP AND R REGISTERS CTRL REGISTER START BIT Figure 8. Programming Logic M 3 M 3 M / CP / CP / R / CP // CP / R / TM POL TE TC DS VB VS BD BE FT IS SB SD R / A /M A A A /M A A M / R / ADDRESS DECODED DATA MA3/MA3/MA34/MA36 9

20 MA3/MA3/MA34/MA36 CDMA IF VGAs and I/Q Demodulators Pin Configurations BUFEN FM- FM+ CDMA+ CDMA- LOCK VGC DATA CLK QOUT+ QOUT- IOUT- IOUT+ REF MODE TANKH- TANKH+ TANKL- TANKL+ CP_OUT QSOP TOP VIEW EN MA FM- FM+ CDMA+ CDMA- LOCK VGC DATA CLK QOUT+ QOUT- IOUT- IOUT+ REF N.C. N.C. TANKL- TANKL+ CP_OUT QSOP EN MA N.C. CDMA+ CDMA- LOCK VGC DATA CLK QOUT+ QOUT- IOUT- IOUT+ REF LOOUT TANKH- TANKH+ DIVSEL CPOUT QSOP EN MA N.C. CDMA+ CDMA- LOCK VGC DATA CLK QOUT+ QOUT- IOUT- IOUT+ REF LOOUT TANKL- TANKL+ DIVSEL CP_OUT QSOP EN MA36 BUFEN

21 TRANSISTOR COUNT: 64 Chip Information CP_OUT IOUT- A TANKL+ TANKH+ TANKL- TANKH- MODE EN D CLK CHARGE PUMP QOUT+ 9 / REF /M PHASE DETECTOR /R DAC AVCC FM- FM+ CDMA+ CDMA- VGA DATA MA3 QOUT- LOCK Block Diagram IOUT+ MA3/MA3/MA34/MA36

22 MA3/MA3/MA34/MA36 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to QSOP.EPS Revision History Pages changed at Rev :, 4, 8, Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.