L18. Digitaalsüsteemide automaatprojekteerimine,
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1 Digitaalsüsteemide automaatprojekteerimine J.F. Wakerly Digital Design: Principles and Practices - 1.5, L18. Digitaalsüsteemide automaatprojekteerimine, sünteesi etapid. L19. VHDL ja süntees. Süsteemitasemesüntees. L20. Füüsikalise taseme projekteerimine. Keerukate süsteemide iseärasused. 1 Digitaalsüsteemi loomine Tootlikkuse puudujääk (productivity gap) tehnoloogia võimaluste kasv 58% aastas projekteerija jõudluse kasv 21% aastas Kuidas sellega hakkama saada? Vaadelda süsteemi kui tervikut ülesande püstitamine riist- ja tarkvara koosdisain Olemasolevate lahenduste kasutamine olemasolevad algoritmid (tarkvara teegid) olemasolevad moodulid (riistvara teegid ) IP-plokid [ IP = Intellectual Property ] Projekteerimine on jagatud sammudeks 2 1
2 Abstraktsioonitasemed Süsteemi tase moodulid & infokanalid Algoritmi tase alam-moodulid & protokollid Register-siirete (RT) tase ALS-d, registrid & siinid Loogikatase skeem loogikaelementidest Füüsikatase skeem transistoridest kristalli pinnalaotus 3 Sünteesi tasemed Süsteemi tase Algoritmi tase süntees Käitumuslik mõõde Register-siirete tase süsteemi spetsifikatsioon analüüs täpsustaminealgoritm Loogika tase register-siirete kirjeldus loogika-avaldised Skeemi tase diferentsiaalvõrrandid Füüsikaline mõõde Struktuurne mõõde CPU, mälu protsessor, alamsüsteem ALU, register, MUX loogikalüli, triger transistor optimeerimine abstraheerimine ristkülik / polügon genereerimine std.element / alam-element makro-element ekstraheerimine plokk / kiip kiip / trükkplaat 4 2
3 Sünteesi tasemed Tase Abstraktsioon Vahendid Süsteem Käitumine ruumis ja ajas, väljaviigud, ajalised piirangud Plokk-skeemid, diagrammid, kõrgtaseme keeled Arhitektuur Funktsionaalsete üksuste üldine jaotus HDL-d, pinnaplaneeringu vahendid ennustamiseks Registersiire Andmevoo sidumine sõlmede ja mikrokäskudega Süntees, simuleerimine, resursside kasutamine Funktsionaalsed moodulid Primitiivsed operatsioonid ja juhtimisvahendid Teegid, moodulite generaatorid, skeemisisestus Loogika Loogikafunktsioonid, skeemid loogikaelementidest Skeemisisestus, süntees ja simuleerimine, test Lülitus Transistorskeemide elektrilised omadused RC ekstraheerimine, ajastuse kontroll ja analüüs Pinnalaotus Geomeetrilised parameetrid Pinnalaotuse redaktor, DRC, laotus ja trasseerimine 5 Sünteesi-süsteemid Süsteemi süntees Liideste süntees Kõrgtaseme süntees Formaalne süntees Registersiirete taseme süntees Loogika süntees Testi süntees Füüsikaline süntees 6 3
4 Sünteesi võlud Automatiseerimine võimaldab vähendada projekteerimiskulusid kiirendada projekteerimist uusimate tehnoloogiate kasutamist formaliseeritus rohkem võimalikke lahendusvariante vähem vigu projekteerimisel 7 Otsustused sünteesil Loogikatase tuhanded sõlmed mõni realiseerimisviis Register-siirete tase sajad sõlmed kümned realiseerimisviisid Käitumuslik ja süsteemi tase kümned sõlmed sajad realiseerimisviisid 8 4
5 Sünteesi valud Loogikatase teisendus mõjutab ainult lähinaabreid lihtsad teisendusalgoritmid on ka efektiivsed Register-siirete tase teisenduse mõjutab suurem Käitumuslik ja süsteemi tase teisendus mõjutab praktiliselt kogu süsteemi puuduvad universaalsed (ja efektiivsed) teisendus-algoritmid 9 Ränikompileerimine Kõrgtaseme süntees sisendiks riistvara kirjelduskeel väljundiks operatsioonide järjestus (mikro)programm väljundiks mooduli arhitektuur Tarkvara süntees (kompileerimine) sisendiks kõrgtaseme keel väljundiks operatsioonide järjestus (assembler) programm 10 5
6 Disaini / sünteesi etapid Ideest realisatsioonini / töötava mudelini Simuleeritava spetsifikatsioon loomine idee korrektsuse kontroll Spetsifikatsiooni tükeldamine hallatavus ja korduvkasutatavus Algoritmide täpsustamine arhitektuursete lahenduste valimine Spetsifikatsiooni teisendamine skeemiks süntees kitsamas tähenduses Realiseerimine / Prototüüpimine 11 Süntees ~~ Tükeldamine Digitaalsüsteem = juhtosa + andmeosa + liides + mälusüsteem control control PE C M PE C M control control control PE C M PE C M PE C M 12 6
7 Esitusviisid Algoritmid programmeerimiskeeled funktsionaalne tükeldamine algoritmi ja andmete täpsustamine riistvara kirjelduskeeled struktuursed, käitumuslikud ja sünteesitavad keeled plokk-diagrammid ja nende sarnased StateChart, Behavioral FSM, jne. 13 Abstraktsed mudelid Struktuurid naabrusmaatriks ahelaloend (netlist) lihtne esitada hierarhiat n1 p1 m1 p4 p6 m1 m2 m3 p2 n2 n3 p7 n1 n2 n3 m2 p3 p5 m3 m1 m2 m3 Loogikavõrkgraafid struktuur + käitumine kombinatoorne sünkroonne a b c a b c p=ac p q q=p+c x y x y 14 7
8 Abstraktsed mudelid Automaadid Andmevoograafid x1=a+b; x2=x1*c; x3=d+e; x4=x3*f; x=x2+x4; otsene sõltuvus operatsioonide (ülesannete) vahel c a + b * * f d + e kontrollsõltuvused? + x 15 Abstraktsed mudelid DFG - Data-Flow Graph CFG - Control-Flow Graph CDFG - Control-and-Data-Flow Graph nop Hierarhia * * Kontrollsõltuvused call / return hargnemised tsüklid + nop br * nop nop + nop nop nop 16 8
9 Näiteülesanne Valgusfoori kontroller vt. ka sidestreet_light highway_car highway_light sidestreet_car 17 Vahendid Xilinx ISE (Xilinx, Inc., simulaator + süntesaator XSA-3S1000 (XESS Corp.,
10 VHDL-st skeemini Ideest mudelini modelleeritav spetsifikatsioon käitumuslik VHDL Mudelist struktuurini struktuur register-siirete tasemel sünteesitav VHDL Struktuurist skeemini loogikaelemendid + ühendused sünteesi juhtimine Iteratsioonid! 19 Valgusfoori kontroller Kiirtee ja kõrvaltee auto sensorid highway_car & sidestreet_car valusfoorid highway_light & sidestreet_light Tulede kombinatsioonid & lülitumiste järjekorrad kiirtee kõrvaltee kestus 1 roheline punane piiramata 2 vilkuv roheline punane 3 sek. 3 kollane kollane 2 sek. 4 punane roheline maksimaalselt 10 sek. 5 punane vilkuv roheline 3 sek. 6 kollane kollane 2 sek. Ooteajad: autole kõrvalteel mitte üle 30 sekundi, kui kiirteel on autosid roheline kõrvalteele 10 sekundit (pluss 3 vilkuvat rohelist) 20 10
11 Ideest mudelini Modelleeritav spetsifikatsioon käitumuslik VHDL Liidese ja andmetüüpide deklareerimine abstraktsed andmetüübid Käitumusliku spetsifikatsiooni loomine kontrollvoog & keerukad ajakontrolli käsud Testkeskkonna loomine, simuleerimine lihtne testimine kiire, kuid ebapiisav... põhjalik testimine keerukas ja aeglane Ideest mudelini Andmetüübid (pkg-enum.vhd) package TLC_data_types is -- Sensors type Sensor is (NoCar, Car); -- Lights type Light is (Red, Yellow, Green, GreenBlink); end TLC_data_types; Olem (tlc-entity.vhd) use work.tlc_data_types.all; entity TLC is port ( highway_car : in Sensor; sidestreet_car : in Sensor; highway_light : out Light := Red; sidestreet_light : out Light := Red ); end TLC; 22 11
12 Ideest mudelini Kontrollvoog & ajakontrolli käsud Waiting for no more than 25 seconds... if highway_car = Car then wait until highway_car = NoCar for 25 sec; end if; vt. tlc-bhv.vhd Testimine kiire vali olem ja forsseeri signaalid [signals] sidestreet_car -> Edit -> Force raske kontrollida kriitilisi olukordi 23 Ideest mudelini Testimine põhjalikum testkeskkond fikseeritud autode saabumisjadaga (vt. tlc-qtst.vhd) universaalne testkeskkond muudetava autode liikumisjadaga (vt. tlc-tst.vhd) Failid pkg-enum.vhd cfg-[q]bhv.vhd tlc-[q]tst.vhd tlc-entity.vhd tlc-bhv.vhd (1) pakett TLC_data_types (5) konfiguratsioon (4) testkeskkond (2) olem TLC (3) arhitektuur BEHAVIOR 24 12
13 Simuleerimine (Modelsim) Andmed loendustüüp 25 Mudelist struktuurini Struktuur register-siirete tasemel sünteesitav VHDL (1) Riistvaralised andmetüübid loendusandmetüübid > bititüübid (2) Käitumise täpsustamine #1 vilkuv roheline (3) Käitumise täpsustamine #2 taimer (2 Hz) ja loogika vilgutamiseks ajakontrollikäsud > sünk.käsud+taimer (4) Sünteesitav VHDL (& struktuur) 26 13
14 Riistvaralised andmetüübid Andmetüübid (pkg-bitv.vhd) package TLC_data_types is -- Sensors subtype Sensor is bit; constant NoCar : Sensor := '0'; constant Car : Sensor := '1'; -- Lights -- "red" - bit 0, i.e., the uppermost light -- "yellow" - bit 1, i.e., the middle light -- "green" - bit 2, i.e., the lowermost light subtype Light is BIT_VECTOR (0 to 2); constant Red : Light := "100"; constant Yellow : Light := "010"; constant Green : Light := "001"; constant GreenBlink : Light := "000"; end TLC_data_types; 27 Riistvaralised andmetüübid Testimine identne esialgsega Failid pkg-bitv.vhd cfg-[q]bhv.vhd tlc-[q]tst.vhd tlc-entity.vhd tlc-bhv.vhd (1) pakett TLC_data_types (5) konfiguratsioonid (4) testkeskkonnad (2) olem TLC (3) arhitektuur BEHAVIOR Kõik uuesti kompileerida! 28 14
15 Simuleerimine (Modelsim) Andmed bit ja bit_vector 29 Käitumise täpsustamine #1 Rohelise tule vilkumine täpsustatud highway_light<=greenblink; on asendatud tsükliga wait for 3 sec; for i in 1 to 6 loop highway_light <= GreenBlink; wait for 0.25 sec; highway_light <= Green; wait for 0.25 sec; end loop; Uued failid cfg-bhv2.vhd tlc-bhv2.vhd konfiguratsioon (pikk test) arhitektuur bhv_refined 30 15
16 Simuleerimine (Modelsim) Täpsustatud rohelise tule vilkumine 31 Käitumise täpsustamine #2 Esmane tükeldamine neljaks alamosaks: (1) Taimeri taktsignaal sagedusega 2 Hz (määratud rohelise tule vilkumissagedusega), kasutatav ka süsteemse taktina (2) ja (3) Sama-aegne protseduur vilkuvat roheliset tekitava kombinatoorse loogika jaoks (4) Kontrollvoog, kuhu on sisse toodud taktsignaal (timer) ja ajakontrolli käsud on asendatud sünkroniseerimiskäskude ja loenduri kombinatsiooniga Protseduur WaitFor asendamaks wait for käske 32 16
17 Käitumise täpsustamine #2 Teisendusi -- Waiting for no more than 25 seconds... if highway_car = Car then wait until highway_car = NoCar for 25 sec; end if; on asendatud -- Waiting for no more than 25 seconds... if highway_car = Car then for counter in 0 to 49 loop seconds exit when highway_car = NoCar; wait on timer until timer='1'; end loop; end if; 33 Uued failid Käitumise täpsustamine #2 cfg-bhv-rtl.vhd tlc-bhv-rtl.vhd konfiguratsioon (pikk test) arhitektuur bhv_rtl Simuleerimine on oluliselt aeglasem Aeg vaja paikka panna run 400 sec Kontrollvoole vastav protsess on põhimõtteliselt sünteesitav kõrgtasemesüntesaatori poolt Vajalikud võivad olla konkreetse sünteesivahendi iseärasustest tingitud muudatused 34 17
18 Simuleerimine (Modelsim) Esmane struktuur + taktsignaalid 35 Sünteesitav VHDL Registersiirete tasemele vastav kirjeldus Sünteesitav enamike sünteesivahendite poolt (võib vajada pisitäpsustusi) nt. teisendus integer range 0 to 63 -> unsigned(5 downto 0) (IEEE 1164) Struktuur esialgse tükeldamise täpsustus Täiendavad signaalid (nt. reset) Kontrollvoog on asendatud automaadi ja loenduriga 36 18
19 Sünteesitav VHDL Komponendid (1) Arhitektuur RTL, mis seob komponendid (fail tlc-rtl.vhd ). Sünteesitav (RTL mõistes). (2) Taktgeneraator (olem clock(bhv) failis tlc-rtl.vhd ). Genereerib taimeri 2 Hz signaali, süsteemse taktsignaali (100 Hz) ja algnullimissignaali. (3) Vilkuvat rohelist tekitav kombinatoorne loogika (olem BlinkLights(bhv) failis tlc-rtl-blnk.vhd ). Sünteesitav. (4) Kontroller automaadi ja loendurina (olem Controller(RTL) failis tlc-rtl-ctrl.vhd ). Sünteesitav. 37 Sünteesitav VHDL Clock TLC Controller BlinkLights BlinkLights highway sidestreet state highway_light_sgn sidestreet_light_sgn highway_light_new sidestreet_light_new next_state highway_car sidestreet_car reset timer clk f-n reset_counter reg cnt counter_out highway_light sidestreet_light Controller(RTL) 38 19
20 Sünteesitav VHDL VHDL konstruktsioone automaadi olek -- FSM state type state_type is (highway_green, highway_wait_25sec, highway_wait_25sec_loop,... sidestreet_yellow, sidestreet_yellow_loop); signal state, next_state: state_type; abisignaalid register->komb.loogika: highway_light_sgn komb.loogika-> register: highway_light_new taimeri väärtus & nullimine 39 Sünteesitav VHDL VHDL konstruktsioone next_state <= state; case state is Waiting for no more than 25 seconds... when highway_wait_25sec => if highway_car=nocar then next_state <= highway_blink; end if; reset_counter <= '1'; next_state <= highway_wait_25sec_loop; when highway_wait_25sec_loop => if highway_car=nocar or counter_out >= 50 then next_state <= highway_blink; end if;
21 Uued failid cfg-[q]rtl.vhd tlc-rtl.vhd tlc-rtl-blnk.vhd tlc-rtl-ctrl.vhd Sünteesitav VHDL konfiguratsioonid arhitektuur RTL vilkuv roheline [BinkLights(bhv)] kontroller+taimer [Controller(RTL)] Simuleerimine on oluliselt aeglasem Aeg vaja paikka panna run 50 sec run 400 sec [konfiguratsioon tlc-qrtl ] [konfiguratsioon tlc-rtl ] 41 Simuleerimine (Modelsim) Sünteesitav VHDL + kiire testpink 42 21
22 Süntees & prototüüpimine Taktsignaal & taimer XSA plaadi taktigeneraator - 10 MHz 2 Hz genereerimine taktsignaalist 22-bitine loendur --> 4* > 2,38 Hz architecture behave of timer is signal count: std_logic_vector (21 downto 0); begin process begin wait on clk until clk='1'; count <= count + '1'; end process; blink <= To_Bit ( count (count'high) ); end behave; 43 Süntees & prototüüpimine Väljaviikude määramine XSA plaadi piirangud Uued failid tlc-rtl-fpga.vhd tlc-rtl-timer.vhd Etapid arhitektuur RTL_fpga 2 Hz taimer [Timer(behave)] süntees (RTL kirjeldus --> CLB) paigaldus & trasseerimine FPGA konfiguratsiooni genereerimine 45 moodulit 768-st (5%) & 112 Mhz 44 22
23 WebPACK / ISE 45 FPGA sisu 46 23
24 FPGA detailsem sisu 47 Hilisemad muudatused Täiustatud taimer 10 MHz / ja 0,5-ne täitetegur (fail "tlc-rtl-timer2.vhd") Muudetud pakett "TLC_data_types kollase ja rohelise tule korraga põlemine (fail "pkg-bitv2.vhd") Muudetud kontroller 2 sek. vilkuv roheline, 3 sek. põlev kollane ja kollane põleb koos punasega enne rohelist (fail "tlc-rtl-ctrl2.vhd") 48 24
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