RED. Course on Electronic Design Automation. (Rechnergestützter Entwurf Digital) lektronik abor

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1 lektronik abor Course on Electronic Design Automation RED (Rechnergestützter Entwurf Digital) Prof. Dr. Martin J. W. Schubert Electronics Laboratory Regensburg University of Applied Sciences, Regensburg

2 Abstract. Course RED: Rechnergestützter Entwurf Digital (Electronic Design Automation) teaches the competences of using software tools applied to an example including project management, system, subsystem module and implementation levels. Knowledge of course System Concepts is no precondition but helpful to understand mathematical. 1 Introduction and Overview 1.1 Introduction and Structure of this Course Course RED: Rechnergestützter Entwurf Digital (Electronic Design Automation) is typically presented in German language with English documentation, but can be offered in English language if necessary. RED course teaches competences to use software tools from project management to hardware implementation. Course SK: Systemkonzepte (System Concepts) is helpful to understand mathematical backgrounds but not necessary. Formulae derived in SK will will be presented as given recipes here in RED. The organization of this course is as follows: 50% of the time are spend in a PC pool and the other 50% are practical training Chapter 1: Introduction explaining the structure of this course Chapter 2: Process models V-Model [1] and Agile [2], Scrum [3] and Kanban Tables[4]. Chapter 3: Specification level: Requirements Engineering Chapter 4: System level: modeling & simulation using Spice [5], [6] and Matlab/Simulink [7] Chapter 5: Subsystem level: cycle-based simulation using Matlab [8] ASCII code Chapter 6 : Module level: event-driven VHDL models simulated with ModelSim [9]. Chapter 7: Implementation Level: VHDL model synthesis by Quartus II [10], download into an FPGA [11], hardware tests. Alternatively using micro controller instead of FPGA. Chapter 8: Summary and Outlook Chapter 9 References - 2 -

3 1.2 Process models V-Model and Agile/Scrum How do we structure the process of a project workflow? The most important process models today are V-Model and Agile / Scrum V-Model Fig.1.2.1: Simplified V-Model [1]. Table 2 illustrates the system interpretation of this project. We shall do subsystem design with Spcie and Matlab, in a first step using behavioral models, then the design is broken down to finite state machines (FSMs). Module design translates Matlab FSMs to VHDL modules. Table 1.2.1: Possible implementation of V-Model structure - 3 -

4 1.2.2 Agile [2] / Scrum [3] / Kanban Tables [4] <Bild aus Copyright-Gründen gelöscht> <Figure deleted due to copyright reasons> Classical process models: Milestones must be reached. (A car must be ready when sold) Agile/Scrum: Deadlines must be reached. (E.g. a practical training will end on 3. July.) <Figure deleted due to copyright reasons> <Bild aus Copyright-Gründen gelöscht> - 4 -

5 1.3 Specification Level: Requirements Engineering (a) Screenshot taken from [11]: LDOs AME1117 [12] translate voltage differences to heat (b) VCC12, VCC18 in (a) generated with LDOs, (c) goal: use configurable DC/DC converters Fig : Generation of core voltages for an FPGA As example we use the FPGA core voltage generation of VCC12 = 1.2V and VCC18 = 1.8V from VCC33 = 3.3V. On the FPGA board of an international vendor 3.3V are generated efficiently from a 220V power supply. Using an LDO to convert 3.3V to 1.8V and 1.2V translates more than 45% and 63% of the supply power into heat, respectively. This is unsupportable for portable devices. Therefore, we want to replace the LDOs by energy-efficient, digitally controlled DC/DC buck conveters. Requirement: 8 -bit control signal w = sets set-point for Uout to V in steps of 1mV for the DC/DC buck converter System modeling language SysML [13] may be used to support requirement engineering and specification

6 1.4 System Level Behavioral Modeling Setting up the System (d) Control loop stabillizing lowpass / oscillator Fig : Generation of core voltages for an FPGA: (a) PWM filtered by (b) RLC lowpass. A DC/DC buck converter consist basically of a RLC lowpass smoothing a PWM signal. High efficiency requires to minimize resistive losses of the RLC lowpass. This makes it an oscillator. A regulator (controller) is required to stabilize output voltage. Goal: Build a digital regulator using the numerical power of the FPGA

7 1.4.2 Spice Behavioral System Model (a) LTspice behovioral simulation setup (b) 17 DAC-Levels, A/D/A conversion delay = 3 µs (c) 2 DAC-Levels, A/D/A conversion delay = 3 µs (d) 17 DAC-Levels, A/D/A conversion delay = 30 µs Fig : LTspice [5] simulation compares impact of A/D/A delay versus DAC accuracy. Green: voltage set point, red: output voltage, pink: load current, cyan: DAC output. An all-analog loop model is set up and simulated behaviorally with LTspice. Green ist the voltage set point, red the output voltage, pink the load current jumping at 1ms to 1A and at 2ms back to 0. Cyan is the DAC output = lowpass/oscillator input. Reducing DAC output resolution from 17 to 2 levels has no effect on quality, but increasing A/D/A conversion delay removes stability. A noise voltage added from 3ms to the lowpass input has few impact

8 LTspice [5] is available for free by Linear Technology, which is now a part of Analog Devices. Recently, Texas Instruments offers a free analog network analyzer named TINA [6]. Phase margin loss due to delay: Δϕ M = -ω T T del Matlab/Simulink Behavioral System Model (a) Simulink model of the control loop (a) Matlab/Simulink Scope output of (a); green: voltage set point, red: output voltage Fig : Simulink system simulation observed in the Simulink-Scope. Matlab/Simulink can combine time-continuous and time-discrete models. However, the tool is not available for free

9 1.5 Subsystem Level: Cycle-based Modeling Using Matlab Cylcle-Based FSM Modeling and Simulation Fig : Finite State Machine (FSM) model. Clycle-based modeling considers the state memory as vector and the next-state logic as function. An Important point is that we get the transition from time-continuous modeling to a time-discrete FSM model Cylcle-Based Modeling and Simulation of DC/DC Buck Converter Fig : Time-discrete DC/DC buck converter model. Subsystem level, cycle-based model to be described with Matlab ASCII code using the bilinear transformation s = (1-z -1 )/(1+z -1 )2/T - 9 -

10 1.6 Module-Level: Event-Driven Modeling Using VHDL Module level, event-driven VHDL models simulated with ModelSim. Fig. 1.6: Simulation of a VHDL model using ModelSim [9]. Top down signal description: Cyan: set voltage, green: load current, red + brown: output voltages obtained with regulator working with real and integer numbers, respectively, black: controller output. The figure above shows a simulation obtained with ModelSim simulator. In a first step the cycle-based Matlab FSM model is translated to a VDHL event-driven FSM model using real numbes. As real numbers cannot be synthesized (with this tools) the digital regulator (controller) has to be realized with integral numbers as I/O signals. The similarity of the red and brown curves in the figure above illustrate the success. Event-driven designs are known to simulate some times slower than cycle-based models, but the allow to observe gate-delays and later synthesis. Building such an event-driven simulation model with VHDL is a considerably larger effort than building a cycle-based model with Matlab

11 1.7 Hardware Implementation (a) Schematics of digital 2 nd order IIR filter in 1 st canonical direct structure before translation to VHDL code (b) RTL View after syntesis of VHDL code by Quartus II 8.1 (c) Timing information of the synthesizer delivers timing information such as t su, t co, t pd : Clock "clock" has Internal fmax of MHz (period= ns) tsu for register... ("x[18]", "clock") is ns tco from "clock" to destination pin "y[29]" is ns Longest tpd from pin "x[18]" to pin "y[29]" is ns Fig. 1.7: Synthesis of the regulator model realized as 2 nd order IIR filter with Quartus II [10]. Legend: tpd: propagation delay: from change in stimulus vector x to Mealy outputs of y being stable. tsu: setup time from change in vectors x, y to nextstate vector stable for active clock edge. tco: clock-to-output: time from active clock edge to output vector y being stable

12 Synthesizer Quartus II compiles VHDL code for download into our Terasic DE2 board with a Cyclone type Altera FPGA. Quartus II can synthesize mathematical operations +, -, *, /, but requires integer or bitvector data-type signals. After compilation of our VHDL code we can compare our original controller schematics with Quartus II s RTL-View as shown in Fig The synthesizer delivers valuable timing information such as setup time t su, clock-to-output t co or propagation delay t pd. Significan optimzizations are possible, e.g. by dividing through c0 = 2 N with N being an integral number the division can be realized as bit-shift operation. An oscillator circuit driven by an DAC and its output voltage measured by an ADC is under construction and hopefully ready to use in October Conclusions and Outlook Applying manament process models such as V-Model or Agile/Scrum to a DC/DC buck converter example takes the modeling layers system, subsystem, module, hardware implementation. Realization of a hardware oscillator daughter board with DAC and ADC is on the way. 1.9 References [1] V-Model [1] release 2.1, published by Deutsche Bundeswehr on 6. June 2017, available: [2] Agile, available [3] Scrum, available [4] Kanban Table, available: [5] LTspice, available: [6] TINA, available: [7] Simulink, available: [8] Matlab, available: [9] ModelSim, available: [10] Quartus II, available: [11] DE2 Development and Education Board User Manual, Terasic Technologies, available: [12] AME1117, available: [13] SysML, available: