A DSP Based Class D Audio Amplifier *

Transcription

1 OpenStax-CNX module: m A DSP Based Class D Audio Amplifier * Jacob Fainguelernt This work is produced by OpenStax-CNX and licensed under the Creative Commons Attribution License 2.0 Abstract Class D ampliers have proven a higher power eciency performance against linear classes such as Class A, B and AB. Power losses on Class D ampliers are mainly due to non-ideality of the output transistors, operating as switches, controlled by Pulse Width Modulators. This example describes a method for utilizing both the Enhanced Pulse Width Modulator (epwm) and the Analog-to-Digital Converter (ADC) of the TMS320F2808 digital signal controller as D-Class Audio amplier. The method involves analog full bridge D-class power amplier and analog low-pass ltering the amplied PWM signal to remove high frequency components, leaving only the audio-frequency content. 1 Introduction Class D ampliers have proven a higher power eciency performance against linear classes such as Class A, B and AB. Power losses on Class D ampliers are mainly due to non-ideality of the output transistors, operating as switches, controlled by Pulse Width Modulators. This example describes a method for utilizing both the Enhanced Pulse Width Modulator (epwm) and the Analog-to-Digital Converter (ADC) of the TMS320F2808 digital signal controller as D-Class Audio amplier. The method involves analog full bridge D-class power amplier and analog low-pass ltering the amplied PWM signal to remove high frequency components, leaving only the audio-frequency content. 1.1 Hardware and Software Requirements This example was originally developed using the following hardware and software: MatLab R2008a Code Composer Studio (CCS) v3.3 ezdsp-f2808 board. 1.2 Related Files Powerpoint Presentation ClassD.ppt 1 Simulink Model for Real-Time - ezdspf2808_classd.mdl 2 * Version 1.1: Apr 20, :55 am See the le at < 2 See the le at <

2 OpenStax-CNX module: m Principle of Operation The amplier comprises three main blocks (shown in Figure 1): Figure 1: The Class-D Audio Amplier 2.1 Input Circuit: This block interfaces with the audio source, attenuates it DC component and limits the input voltage to the ADC to the range 0-3.3V. The circuit contains also a DC-DC converter, for the DSP input buer.

3 OpenStax-CNX module: m Figure 2: Input Circuit Schematics 2.2 Digital Signal Controller The TMS320F2808, converts the analog signal to a pair of PWM signals that feed the output stage (Please refer to section ). It operates with 100 MHz. The ADC samples the input signal at a Ksps rate. The epwm, generates PWM signal with a period of µs and duty cycle proportional to the input signal level. The epwm coupled with a D-Class output stage and a second order passive RLC lter, provides a DAC equivalent Sampling the Analog Input The analog signal is converted to PCM values as shown in. The conversion is performed as described in Table 1. The ADC operates in a sampling rate of KHz (100 MHz/1024).

4 OpenStax-CNX module: m Figure 3: Analog to Digital (PCM) Conversion Table 1: Analog to Digital Conversion Input Voltage (Vin) V in < 0V 0 0 V in < 3V 4096 Vin 3, V in 3V 4095 Digital Value(ADCRESULT) Table PCM PWM The PCM values are converted to PWM as shown in Figure 4. A period of msecs (1024 clock cycles) was chosen. The relation PCM Value/Full Range is translated to the duty cycle of the PWM. A duty cycle of 512 (50 %) corresponds to 50% of the full range, for example. In this example sample values in the range will be mapped to duty cycle values (CMPA) in the range , by dividing by 4 (shift right 2 bits), as shown in Figure 5.

5 OpenStax-CNX module: m Figure 4: PWM based Digital to Analog Conversion

6 OpenStax-CNX module: m Figure 5: PCM to Duty Cycle Conversion The Interrupt Service Routine The process described in the previous section is executed in the Interrupt Service Routine (ISR). The ADC conversion is triggered by the epwm block when the PWM period starts (every msecs). The ADC generates an interrupt at the end of conversion. The interrupt service routine updates the PWM duty cycle (CMPA value) on the value of this sample. The new duty cycle will be loaded in the beginning of the next PWM period. The process is described in Figure 6.

7 OpenStax-CNX module: m Figure 6: Timing Diagram 2.3 Output Stage: This module contains the H-bridge, and a Low Pass Filter to remove high frequency components, leaving only the audio-frequency content. This module basically implements a Digital to Analog Converter using a PWM signal generator and a Low Pass Filter as shown in. This method is described in.

8 OpenStax-CNX module: m Figure 7: PWM based Digital to Analog Conversion The basic conguration of a D-Class amplier is the Half-Bridge (H-Bridge) conguration. Two output transistors operate as switches, driven by complementary PWM signals. One of the transistors is o (current through it is close zero), while the remaining one is on (voltage across it is close to zero), keeping the power dissipation very low.

9 OpenStax-CNX module: m Figure 8: H-Bridge Power Topology The full-bridge Class D amplier comprises two half bridges, driven by synchronized PWM signals, having two alternate conduction paths through the load, each one having a pair of transistor conducting while the remaining pair is o.

10 OpenStax-CNX module: m Figure 9: Output Stage Schematics 3 Implementation This section will describe the process of building a Simulink model for code generation according to description in chapter. In the rst part the framework for interrupt handling will be created. The second section will describe the creation of the Interrupt Service Routine. 3.1 Interrupt 1.

11 OpenStax-CNX module: m Figure 10: The "F2808 ezdsp" block

12 OpenStax-CNX module: m Figure 11: The "Hardware Interrupt" Block The Interrupt should be generated at the end of conversion of group A, (CPU Values=1 and PIE Values=1) as shown in Figure 12. Figure 12: The "Hardware Interrupt" Selection Table

13 OpenStax-CNX module: m Figure 13: The Hardware Interrupt Conguration

14 OpenStax-CNX module: m Figure 14: The "Function-Call Subsystem" Block You may also change colors, and name the blocks as shown here.

15 OpenStax-CNX module: m Figure 15: The Class-D Amplier Model

16 OpenStax-CNX module: m PCM to PWM Conversion 1. Figure 16

17 OpenStax-CNX module: m Figure 17: The "ADC" Block The block should be congured to use channel 0 of module A, triggered by epwmxa, and post an interrupt at the end of conversion as shown: (a) (b) Figure 18: The "ADC" Conguration

18 OpenStax-CNX module: m Figure 19: The "epwm" block The blocks should be congured as shown in the following gures:

19 OpenStax-CNX module: m (a)

20 OpenStax-CNX module: m (a)

21 OpenStax-CNX module: m Figure 22: The "Shift Arithmetic" Block

22 OpenStax-CNX module: m Figure 23: The "Shift Arithmetic" Block Conguration

23 OpenStax-CNX module: m Figure 24: The Class D Amplier Model

24 OpenStax-CNX module: m Running the model: 1. Figure 25: The System

25 OpenStax-CNX module: m Figure 26: Voltage Supply 2. Build and run the model "CTRL-B". 3. The amplier should start working, connect your audio source, and enjoy the music. 4 Things to Try This example's objective was to show the use of the F2808 blocks, it is certainly not the best implementation, but it serves as the basis for additional features and enhancements like: Use Oversampling Use the High-Resolution PWM Add Signal Processing (Filtering, Equalization, Gain Control) features to the amplier 5 References 1. "ezdsptm F2808 Technical Reference", Spectrum Digital,

26 OpenStax-CNX module: m David M. Alter, " Using PWM Output as a Digital-to-Analog Converter on a TMS320F280x", TI Application Report SPRAA88, September