A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuits

Transcription

1 Published in IET Computers & Digital Techniques Received on 25th May 2011 Revised on 20th March 2013 Accepted on 16th April 2013 ISSN A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuits Mohammad Hossein Moaiyeri 1,2, Reza Faghih Mirzaee 2, Akbar Doostaregan 2, Keivan Navi 1,3, Omid Hashemipour 1 1 Faculty of Electrical and Computer Engineering, Shahid Beheshti University, GC, Tehran, Iran 2 Nanotechnology and Quantum Computing Laboratory, Shahid Beheshti University, GC, Tehran, Iran 3 Department of Electrical Engineering and Computer Science, University of California, Irvine, CA, USA knavi@uci.edu Abstract: This study presents new low-power multiple-valued logic (MVL) circuits for nanoelectronics. These carbon nanotube field effect transistor (FET) (CNTFET)-based MVL circuits are designed based on the unique characteristics of the CNTFET device such as the capability of setting the desired threshold voltages by adopting correct diameters for the nanotubes as well as the same carrier mobility for the P- and N-type devices. These characteristics make CNTFETs very suitable for designing high-performance multiple-vth circuits. The proposed MVL circuits are designed based on the conventional CMOS architecture and by utilising inherently binary gates. Moreover, each of the proposed CNTFET-based ternary circuits includes all the possible types of ternary logic, that is, negative, positive and standard, in one structure. The method proposed in this study is a universal technique for designing MVL logic circuits with any arbitrary number of logic levels, without static power dissipation. The results of the simulations, conducted using Synopsys HSPICE with 32 nm-cntfet technology, demonstrate improvements in terms of power consumption, energy efficiency, robustness and specifically static power dissipation with respect to the other state-of-the-art ternary and quaternary circuits. 1 Introduction Complementary metal oxide semiconductor (CMOS) has been the predominant technology of the past two decades providing the required dimension scaling for implementing energy-efficient and high-density very large scale integration (VLSI) circuits and systems. The majority of essential applications such as financing, telecommunication, education and even medical care are dependent on CMOS technology. Nevertheless, by the unavoidable scaling down of the feature size of the metal oxide semiconductor (MOS) transistor deeper in nanoscale, the CMOS technology faces many critical challenges and difficulties. Problems such as very high leakage currents, high power density, large parametric variations and decreased gate control hinder the successive dimension scaling of the CMOS technology and reduce its suitability for the near future low-power, high-performance and high-density applications. To overpower these challenges and difficulties, some beyond-cmos nanodevices such as carbon nanotube field effect transistor (CNTFET), quantum-dot cellular automata (QCA) and single electron technology (SET) have been introduced to possibly replace the conventional bulk-cmos technology in the near future [1 3]. These nanodevices benefit from low-power consumption, ballistic transport attributes under low supply voltages and very small sizes that make them very suitable for ultra-low-power, ultra-high-performance and ultra-high-density chip design. Nevertheless, considering these nanotechnologies, CNTFET can be more applicable because of its similarities to MOSFET in terms of inherent electronic characteristics. On account of this similarity, previously designed structures based on CMOS platforms can still be utilised in CNTFET technology without any significant modifications. The remarkable one-dimensional band-structure of the CNTFET device represses backscattering and brings about ballistic transport characteristics, which leads to very high-speed operation [4]. In addition, CNTFET generally has the benefit of a much more high-performance operation, lower power consumption, very high carrier velocity and higher transconductance, in comparison with the MOS transistors. Many CNTFET-based circuits such as full adders [5] and multiple-valued logic (MVL) and arithmetic circuits [2, 6 9] have already been presented in the literature. However, the multiple-valued logic circuits could be of more interest in the CNTFET nanotechnology. This is due to the fact that the most suitable and prevalent method for designing voltage-mode MVL circuits is the multiple-threshold (multiple-vth) design technique and the desired threshold voltage can be acquired by adopting correct diameters for the nanotubes of the CNTFET device [2, 6 9]. Unlike the binary logic, in MVL systems there are more than two authorised logic levels and logical and arithmetic operations can be performed on more than two logic values. As a result, in MVL many logical and arithmetic operations could be executed with higher speed and smaller number of IET Comput. Digit. Tech., 2013, Vol. 7, Iss. 4, pp & The Institution of Engineering and Technology 2013

2 computation stages [8]. The main challenges of the binary logic in designing large and dense chips are the interconnections and pin-out problems that restrict the number of connections inside and outside of the circuits. By utilising MVL, wires convey more information, which leads to savings in the number of interconnections and in the insulation between them, and also pins carry more information that results in saving in the number of pins [10]. In addition, MVL storage permits storing more information per memory cell. Moreover, many real life applications, such as robotics, process control and decision systems can be implemented more efficiently by using MVL systems. Using MVL systems results in chips with more density, smaller area, less complexity and very high-bandwidth parallel and serial data transfer. MVL can be even used to solve the binary problems more efficiently. For instance, the third logic value for testing the binary circuits can be used as a medium for signaling the faulty operation [11]. In spite of these great advantages, from the implementation point of view, MVL designs must be compatible with the existing binary technologies. Several high-performance MVL circuits have already been proposed in the literature that considerably enhanced this area of research [2, 6 9, 12]. However, the common major problem of all these designs is their high static power dissipation which is even higher than the other power components specifically at nanoscale. In general, the total power consumption is classified into four components, that is, dynamic, short circuit, static and leakage power consumptions and can be calculated by (1) [13] P total = P dynamic + P short-circuit + P leakage + P static ( ( ) = V DD f clk V swing, i C load, i a i + i i I short-circuit, i+ i I leakage, i + i I static, i ) where V DD is the power supply voltage, f clk is the system clock frequency, V swing,i is the voltage swing of the node i, C load,i is the load capacitance at node i, α i is the switching activity factor at node i, and I short-circuit,i, I static,i and I leakage,i are the short-circuit, static and leakage currents, respectively. The static power, which is caused by the DC currents and is consumed through the paths from V DD to GND during the stable states of the circuits, is a significant consumed power in MVL circuits, specifically at nanoranges [2]. This problem considerably restricts the suitability of the previously presented MVL circuits for low-power applications, specifically for portable battery-powered systems [13]. In this paper, a universal method for designing MVL circuits with no static power dissipation is proposed for nanoelectronics in which the paths from V DD to ground (GND) are eliminated in the static state of the circuits. This leads to considerably lower power consumption and energy efficiency. In the rest of this paper, Sections 2 and 3 review the CNTFET technology and MVL design, respectively. The new low-power CNTFET-based MVL circuits are proposed in Section 4. Section 5 contains the simulation results and comparisons and finally, Section 6 concludes this paper. (1) 2 A brief review of CNTFETs Carbon nanotubes (CNTs) as rolled sheets of graphite can be categorised into single-walled CNTs (SWCNTs), composed of a single cylinder and multi-walled CNTs, composed of more than one cylinder [14]. The chirality vector of a CNT is specified by the (n, m) pair, called chiral number. This pair indeed determines the formation angle of the carbon atoms along the nanotube. If n m 3k (k [ Z) the SWCNT is semiconductor, otherwise it is conductor [4]. Semiconducting SWCNTs can be used as the channel of the CNTFET device. In addition to the unique characteristics of the CNT material, removing the channel of the transistor from the silicon bulk leads to removal and reduction of many parasitic elements. Moreover, unlike the MOSFET devices, P- and N-type CNTFETs have the same mobility (μ n = μ p ) and as a result same drive currents. This unique feature of the CNTFET device is very consequential for simplifying the design and transistor sizing procedures of complex CNTFET-based circuits [15]. The other great advantage of the CNTFET nanodevice compared with the nanoscale MOSFET is that its I V characteristics are similar to well-tempered classic MOSFET devices. Three different types of CNTFETs have already been introduced in the literature, that is, SB-CNTFET, T-CNTFET and MOSFET-like CNTFET [16]. However, considering these types of CNTFETs, MOSFET-like CNTFET is more suitable for circuit design based on the CMOS architectures, because of more similarity with MOSFET in terms of device structure and inherent characteristics. In addition, the main advantage of MOSFET-like CNTFET is that its source/drain (S/D)- channel junctions have no Schottky barrier, and as a result, it has considerably higher ON current and consequently is very suitable for ultra-high-performance applications. The structure of a MOSFET-like CNTFET is illustrated in Fig. 1. A CNTFET has threshold voltage (Vth), similar to a MOSFET, which is the voltage needed for turning on the device electrostatically through the gate. Another unique property of the CNTFET device is that the desired threshold voltage can be determined for a CNTFET by adopting a proper diameter for its CNTs. This is due to the fact that the bandgap of a CNT, which is a measure of the CNTFET threshold voltage, is directly dependent to its diameter. This practical attribute makes CNTFET more flexible than MOSFET and makes it very suitable for designing Fig. 1 Structure of a MOSFET-like CNTFET 168 IET Comput. Digit. Tech., 2013, Vol. 7, Iss. 4, pp & The Institution of Engineering and Technology 2013

3 voltage-mode MVL circuits. The threshold voltage of a CNTFET is nearly considered as the half bandgap and is calculated by (2) [17] V th E bg 2e = a 0V p ed CNT D CNT (nm) where E bg is the CNT bandgap, e is the unit electron charge, a 0 ( nm) is the carbon-to-carbon bond length in a CNT, V π ( ev) is the carbon π π bond energy in the tight bonding model and D CNT is the diameter of the nanotubes. It can be inferred from (2) that the threshold voltage of a CNTFET is inversely proportional to the diameter of its nanotubes, which is calculated by (3) [17] D CNT = a0 3 (2) n 2 + nm + m n p 2 + nm + m 2 (3) Besides the unique advantages of the CNTFET device, this emerging nanotechnology faces some challenges in terms of VLSI-compatible mass production, based on the current fabrication technologies, such as high-resistance CNT-metal contacts, misaligned and mispositioned CNTs, metallic channel CNTs and relatively high fabrication costs. However, promising efforts are being made to overcome these physical challenges in the recent years. In [18], an effective method has been proposed for considerably reducing the CNT-metal resistance by utilising a graphitic interfacial layer between CNT and metal. In addition, a synthesis procedure for manufacturing SWCNTs with specific (n, m) chirality numbers has been presented in [19]. Post-processing methods to set the desired threshold voltage of multitube CNTFETs has been presented in [20]. In addition, in [21, 22], fabrication of imperfection-immune VLSI-compatible sequential and combinational CNTFET logic circuits has been presented. These logic circuits, such as D-latches and half-adder sum generators, are the basic building blocks of VLSI digital systems. Furthermore, chemical doping of CNTs to fabricate and integrate N- and P-type CNTFETs on the same substrate is an important area of the future research in order to obtain complementary VLSI CNTFET-based circuits [22]. 3 A brief review of MVL design Let us consider an m-valued function F(X) with k variables, where X ={x 1, x 2, x 3,, x k } and each x i can adopt values from M = {0, 1, 2,, m 1}. Therefore the function F(X) is a mapping f:m k M and consequently there are m mk different functions possible in the set f. However, among these possible functions, NOT, NAND and NOR operations seem to be more important as they are the building blocks of many other complex logical and arithmetic circuits. These fundamental logical functions can be defined in an m-valued k-variable system according to (4), (5) and (6) NOT(a) = m 1 a (4) ( ) ( ) NAND a 1, a 2,..., a k = m 1 min a1, a 2,..., a k (5) ( ) ( ) NOR a 1, a 2,..., a k = m 1 max a1, a 2,..., a k (6) The ternary logic is a common MVL, which includes three significant logic levels. These logic levels can be considered as 0, 1 and 2 symbols, which are counterpart to 0, ½ V DD and V DD voltage levels. Three different types of logics are defined for the ternary logic, that is, negative, standard and positive such as negative ternary inverter (NTI), standard ternary inverter (STI) and positive ternary inverter (PTI) [11]. Table 1 demonstrates the truth table of the basic logical functions of the ternary logic. Similar to the ternary logic, the basic logical functions of the quaternary and penternary (five-valued) systems can also be defined according to (5 7). The quaternary logic includes four 0, 1, 2 and 3 logic symbols, which are commonly counterpart to 0, ⅓V DD, ⅔V DD and V DD voltage levels. In addition, the penternary logic comprises five 0, 1, 2, 3 and 4 logic symbols, which are commonly equivalent to 0, ¼V DD,½V DD,¾V DD and V DD voltage levels. Several types of CMOS-based MVL circuits have already been proposed in the literature as the emerging of MOSFET technology [12], [23 33]. However, they suffer from many drawbacks which make them unsuitable for the current and the upcoming technologies. For instance, designs of [12], [23 26] dissipate high static power, designs of [23] and [24] require large off-chip resistors, designs of [23 25], [27] and [28] utilise multiple supply voltages and designs of [26 30] use depletion-mode MOSFETs that have become obsolete. In addition, some new structures for CMOS analog inverter have already been proposed, which could be considered as inverters for any arbitrary radix, including the ternary and quaternary logics [30 33]. However, because of the inability of the analogue inverter to restore the output voltage levels and the absence of noise immunity, an analog inverter cannot truly be used as a classical MVL inverter. In the recent years, some state-of-the-art CNTFET-based MVL circuits have been proposed in the literature. Some CNTFET-based ternary logic circuits have been proposed in Table 1 Truth table of the ternary basic logical functions a 1 a 2 NTI, a 1 STI, a 1 PTI, a 1 NTNAND STNAND PTNAND NTNOR STNOR PTNOR IET Comput. Digit. Tech., 2013, Vol. 7, Iss. 4, pp & The Institution of Engineering and Technology 2013

4 [7]. Despite the advantages of utilising CNTFET transistors, they use large ohmic resistors that are difficult to be implemented on-chip and integrated with CNTFETs and also lead to area wastage and performance degradation. To overcome the above-mentioned difficulties, other ternary logical and arithmetic circuits have been proposed in [4] and [8] in which P-CNTFET active loads have been utilised instead of large ohmic resistors. This technique leads to a better integration, higher performance, less area overhead and larger noise margins, in comparison with the conventional CNTFET-based ternary circuits of [7]. Recently, state-of-the-art CNTFET-based ternary logical and arithmetic circuits has also been proposed in [2], which include all the possible ternary logics, that is, negative, standard and positive, in one structure and outperform the previously proposed CMOS and CNTFET designs in terms of performance, power consumption and robustness. In addition to ternary logic, in [34], high-performance CNTFET-based circuits have been introduced for quaternary logic, which has tried to solve the problems of the previous MOSFET-based quaternary designs. Nevertheless, all of the above-mentioned state-of-the-art MVL circuits [2, 4, 7, 8, 34] also suffer from static power consumption. Indeed, a considerable amount of their average power consumption is the static power consumption [2], which restricts their suitability for ultra-low-power applications [13, 16]. 4 Proposed low-power CNTFET-based MVL circuits 4.1 Fundamentals of the proposed method The basic schema of the proposed technique is shown in Fig. 2a, which is based on PTI and NTI gates. The outputs of the PTI and NTI gates are connected together by means of two capacitors that make a weighting sum of their inputs [35]. The voltage of the connection node of the capacitors is calculated as follows V STI = C NV N + C P V P C N + C P (7) It is notable that in (7), the input capacitance of the next stage capacitance load (C L ), which is composed of very small capacitors of the next stage CNTFETs, is ignored for the simplicity of calculation. By utilising identical capacitances for C P and C N, same weighting factors are obtained. As a result, the output voltage of the capacitors is calculated according to (8) V STI = V N + V P 2 Based on (8), the output voltage of STI will be the mean value of the output voltages of NTI and PTI. Therefore if the input voltage becomes V DD, the output voltages of NTI and PTI will be equal to 0 V and as a result the voltage of STI will also be equal to 0 V. If the input voltage becomes 0 V, the output voltages of NTI and PTI will be V DD and therefore the voltage of STI will also be V DD. Finally, if the input voltage becomes ½V DD, the output voltage of NTI will be equal to 0 V and the output voltage of PTI will be V DD and consequently according to (9) the voltage of STI will be equal to ½V DD. The considerable advantage of this proposed method is the absence of static power dissipation, because there is no path from V DD to the ground and (8) Fig. 2 Basic schema of the proposed technique a Basic schema of the proposed idea b Before applying ΔV P voltage c After applying ΔV P voltage d Final schema equivalent circuit after applying ΔV P voltage 170 IET Comput. Digit. Tech., 2013, Vol. 7, Iss. 4, pp & The Institution of Engineering and Technology 2013

5 consequently no DC current flows, while the circuit operates in the static mode. In the proposed idea, the capacitors perform voltage division by charging and discharging the electrical load. Therefore it may be conceived that the residue charges may affect the output voltage, when inputs change. Some convincing surveys have been carried out through mathematical equations and simulations to investigate the authenticity of the capacitance voltage divider. Fig. 2b demonstrates the capacitance divider (considering the output C L ), with its input voltages taken apart from the capacitors and are shown separately as the voltage sources. Writing a Kirchhoff s voltage law (KVL) relation on the circuit of Fig. 2b results in (9) V CP,0 + V InP,0 = V CN,0 + V InN,0 = V CL,0 (9) By applying a differential voltage ΔV P on one of the inputs, as demonstrated in Fig. 2c, the capacitors of Fig. 2b will be recharged while satisfying (10) Q P = Q N + Q L (10) Writing a KVL relation on the circuit of Fig. 2c results in (11) DV P + V CP,0 + V In P,0 Q P C P = V CN,0 + V In N,0 + Q N C N = V CL,0 + Q L C L (11) By considering (9) and (11), the following equation is Fig. 3 a Ternary inverter b Ternary buffer c Ternary NAND d Ternary NOR Proposed CNTFET-based ternary logic circuits IET Comput. Digit. Tech., 2013, Vol. 7, Iss. 4, pp & The Institution of Engineering and Technology 2013

6 obtained, which is equivalent to Fig. 2d DV P Q P C P = Q N C N = Q L C L (12) Finally, (13) is achieved from the series capacitors that proves the correct functionality of the divider DV STI = C P DV P C P + C N + C L (13) 4.2 Proposed CNTFET-based MVL circuits Based on Table 1, the basic schema of Fig. 2a, and the complementary CNTFET design method, a novel CNTFET-based ternary inverter circuit is proposed, which is demonstrated in Fig. 3a. The transition regions of PTI and NTI of the proposed ternary inverter are set by adopting proper threshold voltages for CNTFETs that are determined by the diameter of the CNTs [2, 4, 6 8]. Transition points can also be set by adopting proper number of nanotubes (N) for the CNTFETs. Based on (2) and (3), for the CNTFETs of the proposed ternary circuits with the diameters of and nm, the chiral numbers would be (10, 0) and (19, 0) and the threshold voltage values ( Vth ) would be and V, respectively. As a result, high-v t N-type and low-vth P-type CNTFETs are utilised for implementing PTI and low-vth N-type and high-vth P-type CNTFETs are used for implementing NTI. According to (8), the STI signal is generated based on the PTI and NTI signals by a voltage division. The capacitor network of the basic idea is implemented by utilising CNTFET capacitors [36]. One plate of a CNTFET capacitor is the gate and the other plate is the source drain substrate junction. The capacitance of a CNTFET capacitor can be expressed by (14) C CNTFET = NC CNT + C gate (14) where N is the number of nanotubes under the gate, C CNT is the capacitance of one carbon nanotube in the CNTFET device and C gate is the capacitance because of the gate size in the CNTFET transistor. Therefore C CNTFET is nearly proportional to N. The great advantage of the proposed ternary inverter is that there is no path from V DD to GND and no DC current during its stable states and consequently it has zero static power dissipation. Based on the proposed method of design, a novel CNTFET-based ternary buffer with no static power is proposed that is demonstrated in Fig. 3b. This ternary buffer generates all the possible types of ternary signals in one structure and includes negative ternary buffer (NTB), standard ternary buffer (STB) and positive ternary buffer (PTB). The proposed ternary buffer gate is indeed a ternary voltage level restorer which can be utilised in larger ternary circuits. Utilising the proposed ternary buffer instead of two cascaded ternary inverters, results in using two less CNTFETs and also shorter critical path. Based on the functionalities presented in Table 1 as well as the idea of Fig. 2a, new ternary NAND and NOR gates with no static power consumption are proposed, which are Fig. 4 a 3-input STNAND b 3-input STNOR Proposed CNTFET-based 3-input ternary logic circuits 172 IET Comput. Digit. Tech., 2013, Vol. 7, Iss. 4, pp & The Institution of Engineering and Technology 2013

7 Fig. 5 Proposed CNTFET-based quaternary and penternary logic circuits a Quaternary inverter b Quaternary NAND c Quaternary NOR d Penternary inverter e Penternary NAND f Penternary NOR composed of CNTFET transistors and capacitors. The proposed ternary NAND and NOR circuits are shown in Figs. 3c and d, respectively. Unlike the previously proposed ternary gates such as [7, 8, 12, 25], in all of the proposed ternary circuits all the negative, standard and positive ternary logics are Fig. 6 Basic operation of the proposed MVL inverters a Quaternary inverter b Penternary inverter IET Comput. Digit. Tech., 2013, Vol. 7, Iss. 4, pp & The Institution of Engineering and Technology 2013

8 implemented in one structure, which leads to using lower number of transistors. In addition, in the proposed designs only two distinct diameters are used, which results in simplicity of the design and better manufacturability compared with the other state-of-the-art ternary designs such as [2, 8] which require CNTFETs with three different diameters. The proposed ternary 2-input NAND and NOR circuits can also be extended to ternary NAND and NOR with more than two inputs by utilising negative and positive TNANDs and TNORs with more than two inputs. For instance, Fig. 4 demonstrates the 3-input STNAND and STNOR that utilise 3-input positive and negative NANDs and NORs with the CMOS style. For designing these ternary circuits also, only two different CNT diameters are required. Another great advantage of the proposed idea is its expandability for designing MVL circuits with any arbitrary number of logic levels such as quaternary logic. Based on (5 7) as well as the proposed universal method of designing MVL circuits, novel CNTFET-based quaternary logic gates are proposed. The proposed quaternary logic gates that are shown in Figs. 5a c are designed based on simple CNTFET-based basic logic gates with the conventional CMOS configurations. The transition points of the basic gates are set by adopting correct diameters for the channels of the CNTFETs. It is notable that for designing the proposed quaternary CNTFET-based circuits only three different diameters are used for the nanotubes, whereas this number of diameters has been used in the previous works for designing ternary logic circuits. For the CNTFETs of the proposed quaternary circuit with the diameters of 0.783, and 2.27 nm, the chirality numbers would be (10, 0), (19, 0) and (29, 0) and the threshold voltage values ( Vth ) would be almost 0.557, and V, respectively. The voltage transfer characteristics (VTCs) of the utilised inherently binary inverters of the proposed QNOT are shown in Fig. 6a, as a case in point. According to Fig. 6a, the output voltage of QNOT is obtained based on (15) in which V Out1, V Out2 and V Out3 are the output voltages of the inverters of Fig. 5a Table 2 Characteristics of the used CNTFET model Parameter Brief description Value L ch physical channel length 10 nm L ss the length of doped CNT source-side 10 nm extension region L dd the length of doped CNT drain-side 10 nm extension region L geff the scattering mean free path in the 100 nm intrinsic CNT channel and S/D regions pitch the distance between the centres of two 20 nm neighbouring CNTs within the same device L eff the mean free path in p +/n + doped CNT 15 nm sub_pitch sub-lithographic (e.g. CNT gate width) 4nm pitch K ox the dielectric constant of high-k top gate 16 dielectric material (HfO 2 ) T_ox the thickness of high-k top gate dielectric 4nm material K sub the dielectric constant of substrate (SiO 2 ) 4 C sub the coupling capacitance between the 40 af/μm channel region and the substrate (SiO 2 ) Efi the Fermi level of the doped S/D tube 6 ev phi_m the work function of source/drain metal 4.6 ev contact phi_s CNT work function 4.5 ev which V Out1, V Out2, V Out3 and V Out4 are the output voltages of the inverters of Fig. 5d V PNOT = V Out1 + V Out2 + V Out3 + V Out4 (16) 4 To the best of our knowledge, this is the first time that the basic penternary logic gates are proposed for nanoelectronics. In addition, for designing the proposed quaternary and penternary circuits only three different CNT diameters, all less than 3 nm, has been used, while this number of diameters has been used for designing ternary logic circuits in the previous works. Table 3 Simulation results of the ternary logic gates V QNOT = V Out1 + V Out2 + V Out3 3 (15) Parameters Delay ( s) Average power consumption ( 10 7 W) Energy consumption ( J) It is notable that the proposed quaternary logic circuits are designed based on the inherently binary inverters, while the previously proposed quaternary logic circuits such as [28, 30] are limited to utilise depletion-type MOSFETs, which has become obsolete. Moreover, designs of [30] require three different supply voltages. Based on the proposed universal method of designing MVL logic circuits, novel CNTFET-based penternary logic gates are also proposed, which are illustrated in Figs. 5d f. It is worth mentioning that for designing the proposed penternary CNTFET-based circuits only three different diameters for the nanotubes of the CNTFETs are used, all less than 3 nm, while this number of diameters has been used in the previously presented works for designing ternary logic circuits. For the CNTFETs of the proposed penternary logic circuits with the diameters of 0.783, and nm the chirality numbers would be (10, 0), (14, 0) and (38, 0), respectively, and consequently the threshold voltage values ( Vth ) are about 0.557, and V, respectively. The VTCs of the utilised inherently binary inverters of the proposed PNOT are shown in Fig. 6b. The output voltage of PNOT is calculated according to (16) in Standard ternary NOTs proposed STI STI of [2] STI of [7] STI of [8] STI of [25] Standard ternary buffers proposed STB STB of [2] STB of [7] STB of [8] STB of [25] Standard ternary NANDs proposed STNAND STNAND of [2] STNAND of [7] STNAND of [8] STNAND of [25] Standard ternary NORs proposed STNOR STNOR of [2] STNOR of [7] STNOR of [8] STNOR of [25] IET Comput. Digit. Tech., 2013, Vol. 7, Iss. 4, pp & The Institution of Engineering and Technology 2013

9 Further, in addition to the absence of static power dissipation, by increasing the number of logic levels in the proposed method of design, the critical paths of the circuits remain unchanged. It is notable that although multi-vth nano-mosfets are available, they cannot be used to implement the proposed method with L ch = 32 nm at 32 nm technology node, because of the very low gain of the nano-mosfet-based binary inverters, in the transition region, compared with their CNTFET-based counterparts [15], which is not sufficient for this application. As illustrated in Fig. 6, the gain of the input binary inverters is a very determining factor for correct functionality, robustness and precision of the proposed MVL designs. In order to increase the gain of the MOSFET binary inverters sufficiently, the channel length of the MOSFETs should increase considerably which leads to significant speed degradation and area wastage. However, the gain of the CMOS binary inverters is still lower than their CNTFET counterparts [34]. Moreover, although on-chip capacitors are available in MOSFET technology, including metal insulator metal capacitor (MIMcap) and MOS capacitor (MOScap) [37], MIMcap has very low density (ff/μm 2 ), specifically in the recent technologies that low-k insulators are used for separating the conducting parts, and MOScap suffers from high non-linearity and is not suitable for MVL and analog design. However, another advantage of using CNTFETs in the proposed method is the possibility of using high-k CNTFET capacitors. 5 Simulation results, analysis and comparison In this section, the proposed MVL logic circuits are examined in various conditions, using Synopsys HSPICE simulator with the Compact simulation program with integrated circuit emphasis (SPICE) Model for 32 nm CNTFET (L ch = 32 nm), including all the possible non-idealities [38 40]. This standard model has been designed for unipolar enhancement-mode MOSFET-like CNTFET devices in which each transistor may include one or more CNTs as its channel. This model also considers a realistic, circuit-compatible CNTFET structure and includes practical Fig. 7 Transient response of the proposed ternary structures IET Comput. Digit. Tech., 2013, Vol. 7, Iss. 4, pp & The Institution of Engineering and Technology 2013

10 Fig. 8 Power and energy consumption of the ternary circuits in the presence of process variations 176 IET Comput. Digit. Tech., 2013, Vol. 7, Iss. 4, pp & The Institution of Engineering and Technology 2013

11 device non-idealities, parasitics, Schottky barrier effects at the contacts, inter-cnt charge screening effects, doped source drain extension regions, scattering (non-ideal near-ballistic transport), back-gate (substrate bias) effect and source/drain and gate resistances and capacitances. The model also includes a full transcapacitance network for more accurate transient and dynamic performance simulations. The parameters of the CNTFET model and their values, with brief descriptions, are listed in Table 2. For testing the ternary inverters and buffers, all the 2 1, 1 0, 0 1, 1 2, 2 0 and 0 2 transitions are considered. For testing the two-input ternary circuits, a complete input pattern with all the 81 possible transitions from an input combination to another is fed to the circuits. In addition, the quaternary and penternary logic circuits are simulated based on the input pattern presented in [28]. The delay of all transitions from one-input to another are measured and the maximum obtained value is reported as the propagation delay of each circuit. To measure the average power consumption accurately and to prevent underestimation, all the possible input combinations for measuring the average power consumption of the circuits are considered. This guarantees that the measured average power consumption is an accurate reading of the power consumption of the circuit [41]. In order to make a compromise between the power consumption and the delay of the circuits, the performance of the circuits can be evaluated by measuring the average energy consumption, which is defined as the multiplication of the average power consumption and the maximum delay. Therefore the energy consumption could be a significant parameter for evaluating the performance of the circuits [42]. Each ternary circuit is simulated by considering a ternary FO 4, composed of four ternary inverters of the same logic style of that circuit, at its output load. The simulation results, including the worst-case delay, the average power consumption and the average energy consumption, are also listed in Table 3 for 0.9 V supply voltage, which is the standard voltage for 32 nm technology node and the best results at each voltage are demonstrated in bold. According to the contents of Table 3, designs presented in [7] have considerably lower performance and higher power consumption, because of utilising large ohmic resistors and their high static power dissipation, while their outputs are around ½V DD and 0 V. Moreover, the proposed ternary circuits outperform the other designs in terms of power consumption and energy efficiency, mostly because of the elimination of static power dissipation, which will be discussed later. Moreover, the transient response of the proposed ternary structures are shown in Fig. 7 in which restoring the voltage levels of non-full-swing input signals at the outputs of the STI and STB circuits is clearly demonstrated. As the proposed CNTFET-based MVL circuits are designed based on the multiple-vth method, the impact of the process variations on the threshold voltages of the CNTFETs should definitely be examined. The most important parameters that determine the threshold voltage value of a CNTFET are the diameter of its nanotubes and the thickness of its gate oxide layer (T_ox). In addition, as the proposed MVL circuits are designed for low-power applications, after checking their correct operation, the most significant parameter, which should be evaluated in the presence of process variations, is the average power consumption. Moreover, for evaluating the performance of the circuits in the presence of process variations, the average energy consumption variation can also be measured. Here on, Monte-Carlo transient analysis with a reasonable number of 30 iterations per simulation is carried out using the HSPICE simulator. Furthermore on each iteration, the calculation is repeated 10 times and the largest deviation is saved as the result of that iteration. The statistical significance of 30 iterations is very high. If a circuit operates correctly for all the 30 iterations, there is a 99% probability that over 80% of all the possible component values operate properly. It is notable that the distribution of the diameter and T_ox is assumed as Gaussian with 8-sigma distribution [43, 44]. The mean values for the diameters are set to the values demonstrated in Fig. 3 and the mean value of T_ox of all CNTFETs is set to 4 nm. Considering the impreciseness of fabrication techniques, a standard deviation from the mean in the range of 0.04 to 0.2 nm is taken into account for each mean diameter value [45]. Furthermore, the value of T_ox is deviated up to 50% of its mean value. The simulation results of STIs and STNORs as examples of the one-input and two-input ternary logic circuits are shown in Fig. 8. It can be inferred from the results that the power and energy consumption of the proposed CNTFET-based ternary logic circuits are less sensitive to the parametric variations, compared with the state-of-the-art designs of [2] and [8], specifically for the larger parametric deviations. As stated before, while the previous state-of-the-art CNTFET-based designs required three different CNT diameters, the number of required CNTFET diameters in Table 4 Simulation results of the proposed quaternary and penternary logic circuits V DD, V 0.8 V 0.9 V 1 V Standard quaternary logic gates delay ( s) proposed QNOT QNOT of [34] proposed QNAND QMIN of [34] proposed QNOR QMAX of [34] Power consumption ( 10 6 W) proposed QNOT QNOT of [34] proposed QNAND QMIN of [34] proposed QNOR QMAX of [34] Energy consumption ( J) proposed QNOT QNOT of [34] proposed QNAND QMIN of [34] proposed QNOR QMAX of [34] Standard penternary logic gates delay ( s) proposed PNOT proposed PNAND proposed PNOR Power consumption ( 10 6 W) proposed PNOT proposed PNAND proposed PNOR Energy consumption ( J) proposed PNOT proposed PNAND proposed PNOR IET Comput. Digit. Tech., 2013, Vol. 7, Iss. 4, pp & The Institution of Engineering and Technology 2013

12 Fig. 9 a Quaternary logic b Penternary logic Transient response of the proposed MVL circuits the proposed ternary designs is only two, which enhances their robustness and manufacturability. Another aspect of the process variations, which should be taken into consideration in the proposed MVL structures, is the possible mismatch between the capacitors, mainly caused by the possible difference between the numbers of the nanotubes under the gate of the CNTFET capacitors. The simulation results prove the correct operation of the proposed circuits and its 25% maximum variation in the energy consumption, when up to 35% difference between the numbers of CNTs of the CNTFET capacitors is taken into account for testing the proposed ternary circuits. The proposed quaternary and penternary circuits, designed based on the proposed universal method, are also simulated at 1, 0.9 and 0.8 V power supply voltages. The simulation results of these designs are listed in Table 4 which indicates the low-power operation and energy efficiency of the novel proposed quaternary and penternary logic circuits. The proposed quaternary logic circuits are also compared with the state-of-the-art high-performance CNTFET-based designs previously proposed in the literature [34]. The other quaternary and penternary logic circuits, as stated in Section 3, have been designed based on depletion transistors that have become obsolete and are not applicable in the recent nanoscale technologies. According to the results, the proposed quaternary logic circuits considerably outperform the design of [34] in terms of average power consumption and energy efficiency, especially at lower 178 IET Comput. Digit. Tech., 2013, Vol. 7, Iss. 4, pp & The Institution of Engineering and Technology 2013

13 Table 5 Average static power consumption (including leakage) of the MVL circuits Ternary designs ( 10 8 W) proposed STI STI of [2] STI of [8] average improvement 88.55% proposed STB STB of [2] STB of [8] average improvement 92.39% proposed STNAND STNAND of [2] STNAND of [8] average improvement 77.22% Proposed STNOR STNOR of [2] STNOR of [8] average improvement 76.95% Quaternary designs ( 10 6 W) proposed QNOT QNOT of [34] improvement 93.76% proposed QNAND QMIN of [34] improvement 94.53% proposed QNOR QMAX of [34] improvement 94.37% Penternary designs ( 10 6 W) proposed PNOT proposed PNAND proposed PNOR voltages. As predicted before, the resistive voltage divided in the designs of [34] leads to high static power consumption. However, because of the absence of any static paths from V DD to GND in the proposed designs, no static power is dissipated and the power consumption is reduced considerably. In addition, the results of the transient analysis of the proposed quaternary and penternary designs at 0.9 V, which authenticate the correct operation of the proposed MVL designs, are demonstrated in Figs. 9a and b, respectively. According to (1), the average power consumption is generally composed of switching, short-circuit, static and leakage components. However in the recent and future circuits, the static and leakage components are becoming very important. Dissimilar to short-circuit and switching powers, static and leakage powers are consumed irrelevant to the switching activity of the circuit. Therefore to measure the static power, the circuits should be exhaustively tested in stand-by mode for all the possible input combinations [46]. Therefore constant inputs should be fed into the circuits to prevent switching activity at the end nodes as well as the intermediate nodes of the circuits. All the possible input combinations should be fed separately into the circuits and the obtained power would be the sum of static and the leakage powers. The average static powers of the circuits are measured at 0.9 V power supply voltage and are reported in Table 5. According to the results, the proposed method improves the average static power of ternary and quaternary logic circuits by more than 82 and 94%, respectively, compared with the previous state-of-the-art MVL circuits. It is notable that the previous designs have high static power because of the high static currents flowing from V DD to GND during their stable states, as a result of resistive voltage dividing. Moreover, designs of [2] have lower static power consumption compared with designs of [8], because of existing auto body biasing in the circuits of [2] during the stable state that the output voltage is ½V DD. In addition, according to the results, the proposed MVL designs have extremely lower static power consumption compared with the other designs, due to the fact that unlike the other designs, there is no path from V DD to GND during the stable states of the proposed circuits. For example, the static current drawn from the power supply of each of the CNTFET-based standard ternary buffers, against the input voltage, is illustrated in Fig. 10. According to Fig. 10, the proposed design (Fig. 3b) has much lower static current specifically when the input voltage is around ½V DD. 6 Conclusion Novel low-power and high-performance MVL circuits have been proposed for nanoelectronics based on the CNTFET devices. The proposed CNTFET-based circuits have been designed with a universal method for designing MVL circuits based on multi-vth nanodevices and have benefited Fig. 10 a STB of [8] b STB of [2] c proposed STB Static current drawn from the power supply against input voltage IET Comput. Digit. Tech., 2013, Vol. 7, Iss. 4, pp & The Institution of Engineering and Technology 2013

14 from the unique properties of CNTFET. The proposed MVL circuits have simple structures and are designed based on the conventional CMOS architecture by utilising inherently binary gates. For designing the proposed circuits, three different CNT diameters, all less than 3 nm, have been used, which improves the feasibility and manufacturability of the designs. To the best of our knowledge this is the first time in the open literature that penternary logic circuits have been proposed for nanoelectronics. The simulation results confirm the authenticity of the proposed method as well as the superiority of the proposed ternary circuits specifically in terms of the static power dissipation in comparison with the other state-of-the-art ternary circuits. 7 Acknowledgment The authors would like to thank Dr. Belmond Yoberd for his literature contribution. 8 References 1 Kim, Y.-B.: Challenges for nanoscale MOSFETs and emerging nanoelectronics, Trans. Electr. Electron. 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