Design of Gates in Multiple Valued Logic

Transcription

1 Proc. of Int. Conf. on Recent Trends in Information, Telecommunication and Computing, ITC Design of Gates in Multiple Valued Logic Shweta Hajare 1, P.K.Dakhole 2 and Manisha Khorgade 3 1 Yashwantrao Chavan College of Engg,Department of Electronics Engg,Nagpur, India shwetahajare29@gmail.com 2 Yashwantrao Chavan College of Engg,Department of Electronics Engg,Nagpur, India pravin_dakhole@yahoo.com 3 R.G.C.E.R,,Department of Electronics & Telecommunication Engg,Nagpur, India manishakhorgade@hotmail.com Abstract Multiple-valued logic (MVL) application in the design of digital devices opens additional opportunities. In this paper we have designed Quaternary latch & quaternary multiplexer. Multiplexer is designed with different threshold voltages. All the circuits were simulated with the Spice tool using TSMC 250 nm technology and have shown improvements in performance and power consumption and propagation delay than their equivalent binary circuits. Index Terms MVL(Multiple valued logic), Quaternary latch, quaternary mux etc. I. INTRODUCTION Multiple-Valued Logic (MVL) is a discipline of discrete p valued systems where p>2, or in other words, nonbinary valued systems. In general sense, both binary-valued and discrete-valued variables with an infinite number of values can be considered as MVL systems Ref [1,2]. MVL circuits have been implemented in bipolar technology such as integrated injection logic (I2L), emitter-coupled logic (ECL), and charge coupled devices (CCDs),in CMOS technology and using quantum devices. The theoretical advantages of multiplevalued logic in reducing the number of interconnections required to implement logical functions have been well established and widely acknowledged. Serious pin out problems encountered in some VLSI circuit designs could be substantially influenced if signals were allowed to assume 4 or more status. Power dissipation is a major problem in VLSI. The dynamic power dissipation is determined mainly by the interconnection capacitance Ref [7]. Therefore, MVL is also useful for low power dissipation. The binary logic is limited due to interconnect which occupies large area on a VLSI chip. With the help of multiple valued logic different combinational circuits are designed Ref [8] and in the past decades several kinds of MVL circuits have been developed in several different technologies from earlier works on bipolar technologies to novel solutions presented using floating gates Ref [9], capacitive logic Ref [10] and quantum devices. There circuits shows somewhat improvements compared to binary circuits, but none of them have at the same time all requirements to be used in VLSI circuits.in this paper in order to match VLSI requirements, this work present a quaternary general purpose circuit of multiplexer & quaternary D-latch structure with the help of Down literal circuits in voltage mode technology with high performance, negligible static and low dynamic consumption using less transistors than the equivalent binary circuit. In this paper circuit presented were designed & simulated using SPICE with MOSIS parameter for a typical 250 nm CMOS process. DOI: 02.ITC Association of Computer Electronics and Electrical Engineers, 2014

2 II. QUATERNARY CIRCUIT DESIGN This circuit is a CMOS circuit operates with four voltage levels corresponding to 0V and other three power supply lines of 1V, 2V and 3V. Figure 1Quaternary NMIN gate Figure 2 Quaternary MIN gate 394

3 A. NMIN/MIN Gate In quaternary logic, binary NAND gate is replaced by NMIN gate & AND gate is replace by MIN gate [5]. The MIN operation sets the output of the MIN circuit to be the lowest value of inputs. MIN gate is equal to AND gate in binary. NMIN gate is not of MIN gate. In binary AND gate, minimum of two inputs of the gate are chosen at the output. NAND gate is not of AND gate. Similarly in quaternary logic gates minimum of two inputs are chosen for MIN gate. The truth table for NMIN given in Table1. NMIN circuit is combination of the inverter and a common binary AND circuit.min circuit is by adding one inverter at the output of NMIN gate as shown in Fig 1& Fig 2.Simulation result of NMIN & MIN gate is shown in Fig 3.& Fig. 4 respectively. TABLE I. TRUTH TABLE OF LOGIC GATES IN QUATERNARY LOGIC A B MIN MAX NMIN NMAX Figure 3 Simulation result of NMIN gate 395

4 Figure 4 Simulation result of MIN gate Figure 5 Quaternary NMAX gate 396

5 Figure 6. Quaternary MAX gate B. NMAX/MAX Gate In quaternary logic, binary NOR gate is replaced by NMAX gate & OR gate is replaced by MAX gate [5]. NMAX gate is not of MAX gate. The MAX operation sets the output of the MAX circuit to be the largest value of inputs. OR gate in binary is equal to MAX gate. NMAX gate is not of MAX gate circuit. The MAX gate is a circuit of multiple inputs and sets the output in the higher value of all entries. NMAX circuit is combination of the inverter and a common binary OR circuit.max circuit is by adding one inverter at the output of NMAX gate as shown in Fig. 5 & Fig.6.Simulation result of NMAX & MAX gate is shown in Fig 7.& Fig. 8 respectively. C. Quaternary Multiplexer Design In digital circuit, the multiplexer is a device that has many input streams and only one output stream. It forwards one of the input streams to the output stream based on the values of one or more "selection inputs" or control inputs. For example, a two-input multiplexer is a simple connection of logic gates whose output is either input A or input B depending on the value of a third input Z which selects the input. Quaternary multiplexer circuit consist of three down literal circuits, three quaternary inverter & six transmission gate [4] as shown in Fig. 9. Simulation result of Quaternary Multiplexer is shown in Fig.10. For a quaternary multiplexer, all inputs and the output are quaternary and it can have four quaternary input streams using only one quaternary control signal. So the quaternary MUX can implement all possible functions of one variable allowed in this logic.the quaternary logic Down literal circuits are designed by using standard CMOS technology with three different Vt (Threshold voltage) for NMOS and three different Vt for PMOS Ref[3] as given in Table2. D. The Quaternary D- Latch The Quaternary D- Latch circuit was designed with MIN gate, NMAX gate and quaternary inverters [6] as shown fig 11. When en is equal to logic high, the latch is open and the output follows the input. Whatever be the input same is the output. 397

6 Figure 7. Simulation result of NMAX gate Figure 8. Simulation result of Quaternary MAX gate 398

7 Figure 9.Quaternary multiplexer Figure10. Simulation result of Quaternary Multiplexer 399

8 The output of MIN gate circuit is the input to the NMAX gate. When en is equal to logic 0, the latch is closed and the output is held constant. Simulation result of Quaternary D-latch is shown in Fig.12. III. CONCLUSION In this paper, we have designed quaternary multiplexer & D-Latch, basic forming circuits were carried out with the Spice tool using TSMC 0.25µm technology with 3 power supply lines and multi-threshold voltage transistors. These circuits were simulated and compared to a binary equivalent circuit. The circuit had proven the high performance and low power consumption with a low area overhead when compared with the equivalent binary circuit Table 3,Table 4,Table 5. The proposed technique can be used to develop extremely low energy circuits, while sustaining the high performance required for many applications. The comparative analysis of gates with different logic system is given in the table shown below. With the help of this basic circuit we can designed full adder, carry look-ahead adder, ripple carry adder, carry select adder. Figure 11. Quaternary D-latch Figure 12. Simulation result of Quaternary D-latch 400

9 TABLE II. THREE DIFFERENT VT (THRESHOLD VOLTAGE) T1 T2 T3 T4 T5 T6 V T Trans PMOS NMOS PMOS NMOS PMOS NMOS Type Circuit type TABLE III. COMPARATIVE ANALYSIS OF DELAY Delay(ns) Binary Ternary Quaternary Inverter Min Max Nmin Nmax TABLE IV. COMPARATIVE ANALYSIS OF POWER CONSUMPTION Circuit type Power Consumption Binary Ternary Quaternary Inverter 0.1nw 0.2nw 27.1pw Min 38.9uw 0.5mw 2.1uw Max 67.1uw 0.68mw 0.4uw Nmin 11.5nw 0.54mw 0.1nw Nmax 67.1uw 0.54mw 0.28uw TABLE V.COMPARISION OF POWER CONSUMPTION Circuit type Quaternary 4:1 Mux 4.96u Binary 8:1 Mux 84 uw Power Consumption Quaternary D-Latch Binary D-Latch 87.9uw 230uw REFERENCES [1] K. C. Smith, The prospects for multi-valued logic: A technology and applications view, IEEE Trans. Computers, vol. C-30, no. 9, pp , Sep [2] K. C. Smith, Multiple-valued logic: a tutorial and appreciation, IEEE Computer, vol.21, pp ,Apr [3] Ricardo Cunha, Henri Boudinov and Luigi Carro Quaternary Look-up Tables Using Voltage-Mode CMOS Logic Design Proceedings of the 37th International Symposium on Multiple-Valued Logic (ISMVL'07)pp.56-56, 2007, May, [4] Vasundara Patel K. S. Quaternary CMOS Combinational Logic Circuits 2009 International Conference on Information and Multimedia Technology [5] Ricardo Cunha G. da Silva, Henri Boudinov, and Luigi Carro, A Novel Voltage-Mode CMOS Quaternary Logic Design IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 6, JUNE 2006 [6] Ricardo Cunha G. da Silva, A Novel Voltage Mode CMOS Quaternary Logic Design, IEEE Transactions on Electron Devices, vol.53, no. 6, June [7] D.Etiemble and M.Israel, Comparison of Binary and Multivalued ICs according to VLSI criteria, Computers, vol. 21, pp , April 1988 [8] E. Dubrova, Multiple-Valued Logic in VLSI: Challenges and Opportunities, Proceedings of NORCHIP'99, pp ,

10 [9] Y. Berg, S. Aunet, O. Mirmotahari, and M. Høvin, Novel Recharge. Semi-Floating-Gate CMOS Logic For Multiple-Valued Systems, proc. of the IEEE International Symposium on Circuits and Systems (ISCAS), May [10] A. Schmid, Y. Leblebici. Realisation of multiple-valued functions using the capacitive threshold logic gate, Proc. Of IEE Computer and Digital Techniques, v. 151, n. 6, pp ,