MC74HC4538A. Dual Precision Monostable Multivibrator (Retriggerable, Resettable)
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1 Dual Precision Monostable Multivibrator (Retriggerable, Resettable) The is identical in pinout to the MC4538. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This dual monostable multivibrator may be triggered by either the positive or the negative edge of an input pulse, and produces a precision output pulse over a wide range of pulse widths. ecause the device has conditioned trigger inputs, there are no triggerinput rise and fall time restrictio. The output pulse width is determined by the external timing components, R x and C x. The device has a reset function which forces the output low and the output high, regardless of the state of the output pulse circuitry. PDIP N SUFFIX CSE 648 MRKING DIGRMS N WLYYWWG Features Unlimited Rise and Fall Times llowed on the Trigger Inputs Output Pulse is Independent of the Trigger Pulse Width ± % Guaranteed Pulse Width ariation from Part to Part (Using the Same Test Jig) Output Drive Capability: LSTTL Loads Outputs Directly Interface to CMOS, NMOS and TTL Operating oltage Range: 3. to 6. Low Input Current:. High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7 Chip Complexity: 45 FETs or 36 Equivalent Gates NL Prefix for utomotive and Other pplicatio Requiring Unique Site and Control Change Requirements; EC ualified and PPP Capable These Devices are PbFree, Halogen Free and are RoHS Compliant SOIC D SUFFIX CSE 75 TSSOP DT SUFFIX CSE 948F HC4538G WLYWW HC45 38 LYW = ssembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G or = PbFree Package (Note: Microdot may be in either location) ORDERING INFORMTION See detailed ordering and shipping information in the package dimeio section on page 2 of this data sheet. Semiconductor Components Industries, LLC, 24 May, 24 Rev. 4 Publication Order Number: /D
2 C X /R X RESET Figure. Pin ssignment 9 C X 2/R X 2 RESET FUNCTION TLE Inputs Outputs Reset H H H L H X L Not Triggered H H X Not Triggered H L,H, H Not Triggered H L L,H, Not Triggered L X X L H X X Not Triggered C X R X TRIGGER INPUTS PIN = PIN 8 = R X ND C X RE EXTERNL COMPONENTS PIN ND PIN 5 MUST E HRD WIRED TO RESET 3 C X 2 R X TRIGGER INPUTS RESET 2 3 Figure 2. Logic Diagram ORDERING INFORMTION NG DG DR2G NL74HC4538DR2G* DTR2G NLHC4538DTR2G* Device Package Shipping PDIP (PbFree) SOIC (PbFree) TSSOP (PbFree) 5 Units / Rail 48 Units / Rail 25 / Tape & Reel 25 / Tape & Reel 25 / Tape & Reel 25 / Tape & Reel For information on tape and reel specificatio, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specificatio rochure, RD8/D. *NL Prefix for utomotive and Other pplicatio Requiring Unique Site and Control Change Requirements; EC ualified and PPP Capable 2
3 MXIMUM RTINGS Symbol Parameter alue Unit DC Supply oltage.5 to 7. I DC Input oltage.5 I.5 O DC Output oltage (Note ).5 O.5 I IK DC Input Diode Current,, Reset C X, R X I OK DC Output Diode Current 25 m I O DC Output Sink Current 25 m I CC DC Supply Current per Supply Pin m I DC Ground Current per Ground Pin m T STG Storage Temperature Range 65 to 5 C T L Lead temperature, mm from Case for Seconds 26 C T J Junction temperature under ias 5 C 2 3 m J Thermal resistance PDIP SOIC TSSOP C/W P D Power Dissipation in Still ir at 85 C PDIP SOIC TSSOP MSL Moisture Seitivity Level F R Flammability Rating Oxygen Index: 3% 35% UL94O (.25 in) ESD ESD Withstand oltage Human ody Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) >2 > >5 mw I Latchup Latchup Performance bove and elow at 85 C (Note 5) 3 m Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.. I O absolute maximum rating must be observed. 2. Tested to EI/JESD Tested to EI/JESD Tested to JESD22C. 5. Tested to EI/JESD78. RECOMMENDED OPERTING CONDITIONS Symbol Parameter Min Max Unit DC Supply oltage (Referenced to ) in, out DC Input oltage, Output oltage (Referenced to ) T Operating Temperature, ll Package Types C t r, t f Input Rise and Fall Time = 2. (Figure 7) = = 6. or (Figure 5) R x External Timing Resistor < 5 4 No Limit C x External Timing Capacitor F Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. The maximum allowable values of R x and C x are a function of the leakage of capacitor C x, the leakage of the HC4538, and leakage due to board layout and surface resistance. For most applicatio, C x /R x should be limited to a maximum value of F/. M. alues of C x >. F may cause a problem during power down (see Power Down Coideratio). Susceptibility to externally induced noise signals may occur for R x >.M. 6. Unused inputs may not be left open. ll inputs must be tied to a highlogic voltage level or a lowlogic input voltage level.. 2. k 3
4 DC CHRCTERISTICS Guaranteed Limits Symbol Parameter Test Conditio 55 to 25 C 85 C 25 C Min Typ Max Min Typ Max Min Typ Max Unit IH Minimum HighLevel Input oltage out =. or. I out IL Maximum LowLevel Input oltage out =. or. I out OH Minimum HighLevel Output oltage in = IH or IL I out in = IH or IL I out 4. m I out 5.2 m OL Maximum LowLevel Output oltage in = IH or IL I out I in I in I CC Maximum Input Leakage Current (,, Reset) Maximum Input Leakage Current (R x, C x ) Maximum uiescent Supply Current (per package) Standby State in = IH or IL I out 4. m I out 5.2 m in = or 6. ±. ±. ±. in = or 6. ± 5 ±5 ±5 n in = or and 2 = Low I out = I CC Maximum Supply in = or Current and 2 = High 25 C 45 C to 85 C 55 C to 25 C (per package) I out = ctive State Pi 2 and 4 = Product parametric performance is indicated in the Electrical Characteristics for the listed test conditio, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditio. 4
5 C CHRCTERISTICS (C L = 5 pf, Input t r = t f = 6. ) Symbol t PLH t PHL t PHL t PLH t TLH, t THL Maximum Propagation Delay Input or to (Figures 6 and 8) Maximum Propagation Delay Input or to N (Figures 6 and 8) Maximum Propagation Delay Reset to (Figures 7 and 8) Maximum Propagation Delay Reset to N (Figures 7 and 8) Parameter Maximum Output Traition Time, ny Output (Figures 7 and 8) C in Maximum Input Capacitance (., Reset) (C x, R x ) Guaranteed Limits 55 to 25 C 85 C 25 C Min Max Min Max Min Max Unit pf 25 C, = 5. C PD Power Dissipation Capacitance (per Multivibrator)* 5 *Used to determine the noload dynamic power coumption: P D = C PD 2 CC f + I CC. pf TIMING CHRCTERISTICS (Input t r = t f = 6. ) Guaranteed Limits Symbol Parameter 55 to 25 C 85 C 25 C Min Max Min Max Min Max Unit t rr Minimum Retrigger Time, Input or (Figure 7) (Note 7) t rec Minimum Recovery Time, Inactive to or (Figure 7) t w Minimum Pulse Width, Input or (Figure 6) t w Minimum Pulse Width, Reset (Figure 7) t r, t f Maximum Input Rise and Fall Times, Reset (Figure 7) or (Figure 7) No Limit 7. t rr () (volts) C x (pf) 3.5 5
6 OUTPUT PULSE WIDTH CHRCTERISTICS (R x = k, C x =. F, C L = 5 pf) Symbol Parameter Output Pulse Width (Note 8) (Figures 6 and 7) Conditio Timing Components Guaranteed Limits 55 to 25 C 85 C 25 C Min Max Min Max Min Max Unit ms Pulse Width Match etween Circuits in the same Package R x = k, C x =. F 5. ± 5. % Pulse Width Match ariation (Part to Part) (Note ) ± % OUTPUT PULSE WIDTH CHRCTERISTICS (R x = k, C x = nf, C L = 5 pf) Symbol Parameter Output Pulse Width (Note 9) Pulse Width Match etween Circuits in the same Package Pulse Width Match ariation (Part to Part) (Note ) Timing Components R x = k, C x = nf Conditio 5. Guaranteed Limits mbient Temperature Min Typ Max Unit 25 C 79 s 55 to 25 C % 55 to 25 C + % Temperature ariance 55 to 25 C +.5 s/ C Power Supply ariance 55 to 25 C 8. s/ 8. = kr x C x and k =.7 for the output pulse width corresponding to R x = k, C x =. F. 9. = kr x C x and k =.79 for the output pulse width corresponding to R x = k, C x = nf..pulse width match variation between ICs (parttopart) is defined with identical R x, C x, and a specific temperature. 6
7 TYPICL CHRCTERISTICS k, OUTPUT PULSE WIDTH CONSTNT (TYPICL) k s k , POWER SUPPLY OLTGE (OLTS) CPCITNCE ( F) Figure 3. Typical Output Pulse Width Cotant, k, versus Supply oltage (For output pulse widths > s: = kr x C x ) s T = 25 C = 5, T = 25 C s OUTPUT PULSE WIDTH () ms ms ms s s M k Figure 4. Output Pulse Width versus Timing Capacitance OUTPUT PULSE WIDTH () (NORMLIZED TO 5 NUMER) R x = M C x =. F R x = k C x = pf T = 25 C , POWER SUPPLY OLTGE (OLTS) Figure 5. Normalized Output Pulse Width versus Power Supply oltage OUTPUT PULSE WIDTH () (NORMLIZED TO 25 C NUMER) = 6 = 3 OUTPUT PULSE WIDTH () (NORMLIZED TO 25 C NUMER) = 5.5 = = T, MIENT TEMPERTURE ( C) Figure 6. Normalized Output Pulse Width versus Power Supply oltage T, MIENT TEMPERTURE ( C) Figure 7. Normalized Output Pulse Width versus Power Supply oltage 7
8 t w(h) 5% t w(l) 5% t PLH t PLH 5% t PHL t PHL 5% Figure 8. Switching Waveform t r t f 9% % t rr 5% t f t f RESET 5% 9% % t TLH t w(l) t rec + t rr t PHL 9% % 5% 5% (RETRIGGERED PULSE) t THL t PLH 9% % 5% Figure 9. Switching Waveform TEST POINT DEICE UNDER TEST OUTPUT C L * *Includes all probe and jig capacitance Figure. Test Circuit 8
9 INPUTS, 2 (Pi 4, 2) Positiveedge trigger inputs. risingedge signal on either of these pi triggers the corresponding multivibrator when there is a high level on the or 2 input., 2 (Pi 5, ) Negativeedge trigger inputs. fallingedge signal on either of these pi triggers the corresponding multivibrator when there is a low level on the or 2 input. Reset, Reset 2 (Pi 3, 3) Reset inputs (active low). When a low level is applied to one of these pi, the output of the corresponding multivibrator is reset to a low level and the output is set to a high level. C X /R X and C X 2/R X 2 (Pi 2 and 4) External timing components. These pi are tied to the common points of the external timing resistors and PIN DESCRIPTIONS capacitors (see the lock Diagram). Polystyrene capacitors are recommended for optimum pulse width control. Electrolytic capacitors are not recommended due to high leakages associated with these type capacitors. (Pi and 5) External ground. The external timing capacitors discharge to ground through these pi. OUTPUTS, 2 (Pi 6, ) Noninverted monostable outputs. These pi (normally low) pulse high when the multivibrator is triggered at either the or the input. The width of the pulse is determined by the external timing components, R X and C X., 2 (Pi 7, 9) Inverted monostable outputs. These pi (normally high) pulse low when the multivibrator is triggered at either the or the input. These outputs are the inverse of and 2. RxCx UPPER REFERENCE CIRCUIT + re, UPPER OUTPUT LTCH M2 M 2 k M3 LOWER REFERENCE CIRCUIT + re, LOWER TRIGGER CONTROL CIRCUIT C C R TRIGGER CONTROL RESET CIRCUIT RESET POWER ON RESET RESET LTCH Figure. Logic Detail (/2 the Device) 9
10 CIRCUIT OPERTION Figure 2 shows the HC4538 configured in the retriggerable mode. riefly, the device operates as follows (refer to Figure ): In the quiescent state, the external timing capacitor, C x, is charged to. When a trigger occurs, the output goes high and C x discharges quickly to the lower reference voltage ( ref Lower /3 ). C x then charges, through R x, back up to the upper reference voltage ( ref Upper 2/3 ), at which point the oneshot has timed out and the output goes low. The following, more detailed description of the circuit operation refers to both the logic detail (Figure ) and the timing diagram (Figure 2). UIESCENT STTE In the quiescent state, before an input trigger appears, the output latch is high and the reset latch is high (# in Figure 2). Thus the output (pin 6 or ) of the monostable multivibrator is low (#2, Figure 2). The output of the triggercontrol circuit is low (#3), and traistors M, M2, and M3 are turned off. The external timing capacitor, C x, is charged to (#4), and both the upper and lower reference circuit has a low output (#5). In addition, the output of the triggercontrol reset circuit is low. TRIGGER OPERTION The HC4538 is triggered by either a risingedge signal at input (#7) or a fallingedge signal at input (#8), with the unused trigger input and the Reset input held at the voltage levels shown in the Function Table. Either trigger signal will cause the output of the triggercontrol circuit to go high (#9). The triggercontrol circuit going high simultaneously initiates two events. First, the output latch goes low, thus taking the output of the HC4538 to a high state (#). Second, traistor M3 is turned on, which allows the external timing capacitor, C x, to rapidly discharge toward ground (#). (Note that the voltage across C x appears at the input of both the upper and lower reference circuit comparator). When C x discharges to the reference voltage of the lower reference circuit (#2), the outputs of both reference circuits will be high (#3). The triggercontrol reset circuit goes high, resetting the triggercontrol circuit flipflop to a low state (#4). This tur traistor M3 off again, allowing C x to begin to charge back up toward, with a time cotant t = R x C x (#5). Once the voltage across C x charges to above the lower reference voltage, the lower reference circuit will go low allowing the monostable multivibrator to be retriggered. UIESCENT STTE TRIGGER CYCLE ( INPUT) TRIGGER CYCLE ( INPUT) RESET RETRIGGER TRIGGER INPUT (PIN 4 OR 2) 7 t rr TRIGGER INPUT (PIN 5 OR ) TRIGGER-CONTROL CIRCUIT OUTPUT R X /C X INPUT (PIN 2 OR 4) ref LOWER 5 UPPER REFERENCE CIRCUIT ref UPPER LOWER REFERENCE CIRCUIT 6 RESET INPUT (PIN 3 OR 3) 2 RESET LTCH 22 OUTPUT (PIN 6 OR ) t rr Figure 2. Timing Diagram
11 When C x charges up to the reference voltage of the upper reference circuit (#7), the output of the upper reference circuit goes low (#8). This causes the output latch to toggle, taking the output of the HC4538 to a low state (#9), and completing the timeout cycle. POWERDOWN CONSIDERTIONS Large values of C x may cause problems when powering down the HC4538 because of the amount of energy stored in the capacitor. When a system containing this device is powered down, the capacitor may discharge from through the input protection diodes at pin 2 or pin 4. Current through the protection diodes must be limited to 3 m; therefore, the turnoff time of the power supply must not be faster than t = C x /(3 m). For example, if = 5. and C x = 5 F, the supply must turn off no faster than t = (5. ) (5 F)/3 m = 2.5 ms. This is usually not a problem because power supplies are heavily filtered and cannot discharge at this rate. When a more rapid decrease of to zero volts occurs, the HC4538 may sustain damage. To avoid this possibility, use an external damping diode, D x, connected as shown in Figure 3. est results can be achieved if diode D x is chosen to be a germanium or Schottky type diode able to withstand large current surges. RESET ND POWER ON RESET OPERTION low voltage applied to the Reset pin always forces the output of the HC4538 to a low state. The timing diagram illustrates the case in which reset occurs (#2) while C x is charging up toward the reference voltage of the upper reference circuit (#2). When a reset occurs, the output of the reset latch goes low (#22), turning on traistor M. Thus C x is allowed to quickly charge up to (#23) to await the next trigger signal. On power up of the HC4538 the poweron reset circuit will be high causing a reset condition. This will prevent the triggercontrol circuit from accepting a trigger input during this state. The HC4538 s outputs are low and the not outputs are high. RETRIGGER OPERTION When used in the retriggerable mode (Figure 4), the HC4538 may be retriggered during timing out of the output pulse at any time after the triggercontrol circuit flipflop has been reset (#24), and the voltage across C x is above the lower reference voltage. s long as the C x voltage is below the lower reference voltage, the reset of the flipflop is high, disabling any trigger pulse. This prevents M3 from turning on during this period resulting in an output pulse width that is predictable. The amount of undershoot voltage on R x C x during the trigger mode is a function of loop delay, M3 conductivity, and DD. Minimum retrigger time, trr (Figure 7), is a function of ) time to discharge R x C x from DD to lower reference voltage (T discharge ); 2) loop delay (T delay ); 3) time to charge R x C x from the undershoot voltage back to the lower reference voltage (T charge ). Figure 5 shows the device configured in the nonretriggerable mode. For additional information, please see pplication Note (N558/D) titled Characterization of Retrigger Time in the HC4538 Dual Precision Monostable Multivibrator. D X C X R X RESET Figure 3. Discharge Protection During Power Down
12 TYPICL PPLICTIONS RISINGEDGE TRIGGER C X R X RISINGEDGE TRIGGER C X R X = RESET = RESET = C X R X C X R X = FLLINGEDGE TRIGGER FLLINGEDGE TRIGGER RESET = RESET = Figure 4. Retriggerable Monostable Circuitry Figure 5. Nonretriggerable Monostable Circuitry = N/C R X C X RESET N/C N/C Figure. Connection of Unused Section ONESHOT SELECTION GUIDE s s s ms ms ms s s MC4528 MC4536 MC4538 MC454 HC4538* *Limited operating voltage (2 6 ) TOTL OUTPUT PULSE WIDTH RNGE RECOMMENDED PULSE WIDTH RNGE 23 HR 5 MIN 2
13 PCKGE DIMENSIONS PDIP CSE 6488 ISSUE U D D 9 8 NOTE 8 b2 TOP IEW e/2 e SIDE IEW E H c END IEW WITH LEDS CONSTRINED NOTE 5 2 NOTE 3 L C SETING PLNE X b. M C M M E M e END IEW NOTE 6 NOTES:. DIMENSIONING ND TOLERNCING PER SME YM, CONTROLLING DIMENSION: INCHES. 3. DIMENSIONS, ND L RE MESURED WITH THE PCK- GE SETED IN JEDEC SETING PLNE GUGE GS3. 4. DIMENSIONS D, D ND E DO NOT INCLUDE MOLD FLSH OR PROTRUSIONS. MOLD FLSH OR PROTRUSIONS RE NOT TO EXCEED. INCH. 5. DIMENSION E IS MESURED T POINT.5 ELOW DTUM PLNE H WITH THE LEDS CONSTRINED PERPENDICULR TO DTUM C. 6. DIMENSION E3 IS MESURED T THE LED TIPS WITH THE LEDS UNCONSTRINED. 7. DTUM PLNE H IS COINCIDENT WITH THE OTTOM OF THE LEDS, WHERE THE LEDS EXIT THE ODY. 8. PCKGE CONTOUR IS OPTIONL (ROUNDED OR SURE CORNERS). INCHES MILLIMETERS DIM MIN MX MIN MX b b2.6 TYP.52 TYP C D D.5.3 E E e. SC 2.54 SC e L M 3
14 PCKGE DIMENSIONS SOIC CSE 755 ISSUE K 9 8 P 8 PL.25 (.) M S NOTES:. DIMENSIONING ND TOLERNCING PER NSI YM, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS ND DO NOT INCLUDE MOLD PROTRUSION. 4. MXIMUM MOLD PROTRUSION.5 (.6) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DMR PROTRUSION. LLOWLE DMR PROTRUSION SHLL E.27 (.5) TOTL IN EXCESS OF THE D DIMENSION T MXIMUM MTERIL CONDITION. T SETING PLNE G D PL K C M R X 45 J F MILLIMETERS INCHES DIM MIN MX MIN MX C D F G.27 SC.5 SC J K M 7 7 P R (.) M T S S SOLDERING FOOTPRINT 8X 6.4 X.2 X PITCH 8 9 DIMENSIONS: MILLIMETERS 4
15 PCKGE DIMENSIONS.5 (.6) T.5 (.6) T L. (.4) T SETING PLNE U U S 2X L/2 PIN IDENT. S D C 4 G 4X K REF. (.4) M T U S S 8 7 U H N J J TSSOP4 DT SUFFIX CSE 948G ISSUE N F DETIL E DETIL E.25 (.) K K M ÇÇÇ ÉÉÉ 7.6 SECTION NN SOLDERING FOOTPRINT W NOTES:. DIMENSIONING ND TOLERNCING PER NSI YM, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION DOES NOT INCLUDE MOLD FLSH, PROTRUSIONS OR GTE URRS. MOLD FLSH OR GTE URRS SHLL NOT EXCEED.5 (.6) PER SIDE. 4. DIMENSION DOES NOT INCLUDE INTERLED FLSH OR PROTRUSION. INTERLED FLSH OR PROTRUSION SHLL NOT EXCEED.25 (.) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DMR PROTRUSION. LLOWLE DMR PROTRUSION SHLL E.8 (.3) TOTL IN EXCESS OF THE K DIMENSION T MXIMUM MTERIL CONDITION. 6. TERMINL NUMERS RE SHOWN FOR REFERENCE ONLY. 7. DIMENSION ND RE TO E DETERMINED T DTUM PLNE W. MILLIMETERS INCHES DIM MIN MX MIN MX C.2.47 D F G.65 SC.26 SC H J J K K L 6.4 SC.252 SC M PITCH 4X.36 4X.26 DIMENSIONS: MILLIMETERS ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, coequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specificatio can and do vary in different applicatio and actual performance may vary over time. ll operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any licee under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicatio intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should uyer purchase or use SCILLC products for any such unintended or unauthorized application, uyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless agait all claims, costs, damages, and expees, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/ffirmative ction Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PULICTION ORDERING INFORMTION LITERTURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. ox 53, Denver, Colorado 827 US Phone: or Toll Free US/Canada Fax: or Toll Free US/Canada orderlit@oemi.com N. merican Technical Support: Toll Free US/Canada Europe, Middle East and frica Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative /D
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