T4302. Power MOSFET. 68 A, 30 V, N Channel DPAK/IPAK

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1 NTD Power MOSFET 68, V, NChannel DPK/IPK Features Ultra Low R DS(on) Higher Efficiency Extending Battery Life Logic Level Gate Drive Diode Exhibits High Speed, Soft Recovery valanche Energy Specified I DSS Specified at Elevated Temperature DPK Mounting Information Provided These Devices are PbFree and are RoHS Compliant pplications DCDC Converters Low Voltage Motor Control Power Management in Portable and Battery Powered Products: i.e., Computers, Printers, Cellular and Cordless Telephones, and PCMCI Cards MXIMUM RTINGS (T C = 5 C unless otherwise noted) Rating Symbol Value Unit tosource Voltage V DSS Vdc GatetoSource Voltage Continuous V GS ± Vdc Thermal Resistance JunctiontoCase Total Power T C = 5 C Continuous T C = 5 C (Note ) Continuous T C = C Thermal Resistance Junctiontombient (Note ) Total Power T = 5 C Continuous T = 5 C Continuous T = C Pulsed Current (Note ) Thermal Resistance Junctiontombient (Note ) Total Power T = 5 C Continuous T = 5 C Continuous T = C Pulsed Current (Note ) R JC P D ID I D R J P D ID I D I DM R J P D ID I D I DM Operating and Storage Temperature Range T J, T stg 55 to 5 Single Pulse tosource valanche Energy Starting (V DD = Vdc, V GS = Vdc, Peak I L = 7 pk, L = 5. mh, R G = 5 ) Maximum Lead Temperature for Soldering Purposes, /8 in from case for seconds C/W W C/W W C/W W C E S 7 mj T L 6 C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.. When surface mounted to an FR board using the minimum recommended pad size.. When surface mounted to an FR board using.5 sq. in. drain pad size.. Pulse Test: Pulse Width = s, Duty Cycle = %.. Current Limited by Internal Lead Wires. V (BR)DSS G DPK CSE 69C (Surface Mount) STYLE Gate Y WW T G MRKING DIGRMS & PIN SSIGNMENTS YWW T G D R DS(on) TYP V 7.8 V S Source NChannel IPK CSE 69D (Straight Lead) STYLE Gate YWW T G = ssembly Location* = Year = Work Week = Device Code = PbFree Package I D MX 68 Source * The ssembly Location code () is front side optional. In cases where the ssembly Location is stamped in the package, the front side assembly code may be blank. ORDERING INFORMTION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. Semiconductor Components Industries, LLC, July, Rev. 9 Publication Order Number: NTD/D

2 NTD ELECTRICL CHRCTERISTICS ( unless otherwise noted) Characteristic Symbol Min Typ Max Unit OFF CHRCTERISTICS Source Breakdown Voltage (V GS = Vdc, I D = 5 ) Positive Temperature Coefficient Zero Gate Voltage Current (V GS = Vdc, V DS = Vdc, ) (V GS = Vdc, V DS = Vdc, ) V (BR)DSS GateBody Leakage Current (V GS = ± Vdc, V DS = Vdc) I GSS ± ndc I DSS 5. Vdc mv/ C dc V ON CHRCTERISTICS Gate Threshold Voltage Vdc (V DS = V GS, I D = 5 dc) Negative Temperature Coefficient GS(th) Static Source OnState Resistance R DS(on) (V GS = Vdc, I D = dc) (V GS = Vdc, I D = dc) (V GS =.5 Vdc, I D = 5. dc) Forward Transconductance (V DS = 5 Vdc, I D = dc) gfs Mhos DYNMIC CHRCTERISTICS Input Capacitance C iss 5 pf Output Capacitance (V DS = Vdc, V GS = Vdc, f =. MHz) C oss 6 8 Reverse Transfer Capacitance C rss 5 SWITCHING CHRCTERISTICS (Note 6) TurnOn Delay Time t d(on) ns Rise Time (V DD = 5 Vdc, I D =. dc, t r 5 5 V GS = Vdc, TurnOff Delay Time R G = 6. ) t d(off) 85 Fall Time t f 55 9 TurnOn Delay Time t d(on) ns Rise Time (V DD = 5 Vdc, I D =. dc, t r V GS = Vdc, TurnOff Delay Time R G =.5 ) t d(off) 55 9 Fall Time t f 75 TurnOn Delay Time t d(on) 5 ns Rise Time (V DD = Vdc, I D = dc, t r 5 V GS = Vdc, TurnOff Delay Time R G =.5 ) t d(off) Fall Time t f 58 Gate Charge Q T 55 8 nc (V DS = Vdc, I D =. dc, V GS = Vdc) Q gs (Q) 5.5 Q gd (Q) 5 BODYDRIN DIODE RTINGS (Note 5) Diode Forward OnVoltage (I S =. dc, V GS = Vdc) (I S = dc, V GS = Vdc) (I S =. dc, V GS = Vdc, ) Reverse Recovery Time (I S =. dc, V GS = Vdc, di S /dt = / s) V SD Vdc t rr 9 65 ns t a t b 9 Reverse Recovery Stored Charge Q rr. C Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 5. Indicates Pulse Test: Pulse Width = sec max, Duty Cycle %. 6. Switching characteristics are independent of operating junction temperature.

3 NTD TYPICL CHRCTERISTICS 5 V GS = V 6 V DS > = V I D, DRIN CURRENT (MPS) V GS =. V V GS =.6 V V GS = 5 V V GS = 7 V V GS = V V GS =.8 V V GS =.8 V V GS =. V V GS =. V V GS =. V I D, DRIN CURRENT (MPS) 5 T J = C T J = 55 C V DS, DRINTOSOURCE VOLTGE (V) Figure. OnRegion Characteristics 5 6 V GS, GTETOSOURCE VOLTGE (V) Figure. Transfer Characteristics R DS(on), DRINTOSOURCE RESISTNCE ( ) I D = 6 8 V GS, GTETOSOURCE VOLTGE (V) R DS(on), DRINTOSOURCE RESISTNCE ( ).5..5.E+.E+ V GS =.5 V V GS = V.E+.E+.E+ 5.E+ 6.E+ I D, DRIN CURRENT (MPS) Figure. OnResistance vs. GateToSource Voltage Figure. OnResistance vs. Current and Gate Voltage R DS(on), DRINTOSOURCE RESISTNCE (NORMLIZED) I D = 8.5 V GS = V T J, JUNCTION TEMPERTURE ( C) I DSS, LEKGE (n) V GS = V T J = 5 C T J = C V DS, DRINTOSOURCE VOLTGE (V) Figure 5. OnResistance Variation with Temperature Figure 6. ToSource Leakage Current vs. Voltage

4 NTD TYPICL CHRCTERISTICS C, CPCITNCE (pf) 6 5 V DS = V V GS = V C iss C rss Ciss V GS, GTETOSOURCE VOLTGE (V) C oss.5 C rss I D = V GS V DS 5 6 GTETOSOURCE OR DRINTOSOURCE VOLTGE (V) Q g, TOTL GTE CHRGE (nc) V D Q Q Q T V GS 5 5 V DS, DRINTOSOURCE VOLTGE (V) Figure 7. Capacitance Variation Figure 8. GatetoSource and tosource Voltage vs. Total Charge t, TIME (ns) V DD = V I D = 8.5 V GS = V t f t d(off) t r t d(on) R G, GTE RESISTNCE ( ) Figure 9. Resistive Switching Time Variation vs. Gate Resistance I S, SOURCE CURRENT (MPS) V GS = V V SD, SOURCETODRIN VOLTGE (V) Figure. Diode Forward Voltage vs. Current

5 NTD TYPICL CHRCTERISTICS ID, DRIN CURRENT (MPS). V GS = V SINGLE PULSE T C = 5 C R DS(on) LIMIT THERML LIMIT PCKGE LIMIT V DS, DRIN-TO-SOURCE VOLTGE (VOLTS) s ms ms dc I S t p di/dt t a t rr t b I S.5 I S TIME Figure. Maximum Rated Forward Biased Safe Operating rea Figure. Diode Reverse Recovery Waveform Rthja(t), EFFECTIVE TRNSIENT THERML RESISTNCE. DUTY CYCLE D =.5 MOUNTED TO MINIMUM RECOMMENDED FOOTPRINT P (pk) t t DUTY CYCLE, D = t /t Figure. Thermal Response Various Duty Cycles R J (t) = r(t) R J D CURVES PPLY FOR POWER PULSE TRIN SHOWN RED TIME T t T J(pk) - T = P (pk) R J (t) SINGLE PULSE. E-5 E- E- E- E- E+ E+ E+ E+ t, TIME (seconds) ORDERING INFORMTION Device Package Type Package Shipping NTDG DPK 69C (PbFree) 75 Units / Rail NTDG IPK 69D (PbFree) 75 Units / Rail NTDTG DPK 69C (PbFree) 5 Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8/D. 5

6 NTD PCKGE DIMENSIONS DPK (SINGLE GUGE) CSE 69C ISSUE E L E b D B DETIL C c H Z Z NOTES:. DIMENSIONING ND TOLERNCING PER SME Y.5M, 99.. CONTROLLING DIMENSION: INCHES.. THERML PD CONTOUR OPTIONL WITHIN DI- MENSIONS b, L and Z.. DIMENSIONS D ND E DO NOT INCLUDE MOLD FLSH, PROTRUSIONS, OR BURRS. MOLD FLSH, PROTRUSIONS, OR GTE BURRS SHLL NOT EXCEED.6 INCHES PER SIDE. 5. DIMENSIONS D ND E RE DETERMINED T THE OUTERMOST EXTREMES OF THE PLSTIC BODY. 6. DTUMS ND B RE DETERMINED T DTUM PLNE H. 7. OPTIONL MOLD FETURE. L b e b TOP VIEW NOTE 7 c SIDE VIEW.5 (.) M C L GUGE PLNE BOTTOM VIEW L L DETIL ROTTED 9 CW H BOTTOM VIEW LTERNTE CONSTRUCTION C SETING PLNE INCHES MILLIMETERS DIM MIN MX MIN MX b b b c c D E e.9 BSC.9 BSC H L L. REF.9 REF L. BSC.5 BSC L L.. Z.55.9 SOLDERING FOOTPRINT* STYLE : PIN. GTE. DRIN. SOURCE. DRIN SCLE : mm inches *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 6

7 NTD PCKGE DIMENSIONS IPK CSE 69D ISSUE C V B R C E NOTES:. DIMENSIONING ND TOLERNCING PER NSI Y.5M, 98.. CONTROLLING DIMENSION: INCH. S T SETING PLNE F G K D PL J. (.5) M T H Z INCHES MILLIMETERS DIM MIN MX MIN MX B C D E F G.9 BSC.9 BSC H J K R S V Z.55.9 STYLE : PIN. GTE. DRIN. SOURCE. DRIN ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. listing of SCILLC s product/patent coverage may be accessed at SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/ffirmative ction Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICTION ORDERING INFORMTION LITERTURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 56, Denver, Colorado 87 US Phone: or 886 Toll Free US/Canada Fax: or 8867 Toll Free US/Canada orderlit@onsemi.com N. merican Technical Support: Toll Free US/Canada Europe, Middle East and frica Technical Support: Phone: 79 9 Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative NTD/D