High-Speed Low-Power MCML Nanometer Circuits with Near-Threshold Computing

Transcription

1 JOURNL OF COMPUTER, VOL. 8, NO., JNUR High-peed Low-Power Nanometer Circuits with Near-Threshold Computing Jianping Hu, Haiyan Ni, and inshui Xia Faculty of Information cience and Technology, Ningbo University, Ningbo City, China bstract In this paper, the standard cells of the high-speed low-power circuits with near-threshold computing are developed. The basic standard cells include buffer/inverter, ND/NND, XOR/XNOR, multiplexer, and full adder. The layout, abstract design and standard-cell characters of near-threshold basic cells are described at a NCU FreePDK 45nm technology. The 2-bit multiplier is verified by using the cells. For normal supply voltage, the basic gates can save more energy and have better performance than the traditional CMO counterparts at GHz or higher operation frequencies. Near-threshold computing for circuits is investigated by scaling down the supply voltage. The results show that the power consumption of circuits that operate on near-threshold regions can be reduced without performance degrading. Index Terms nanometer circuit, near-threshold computing, MO current-mode logic, low power, high-speed operating I. INTRODUCTION MO current mode logic () techniques could be used to realize high-speed circuits []. Therefore, is usually used for high-speed applications such as highspeed processors and Gbps multiplexers for optical transceivers [, 2]. The circuits designed with the techniques can operate over a wide range of frequencies [3]. Moreover, has low noise level due to constant current flowing through supply rails and low crosstalk because of small logic swing. nother interesting advantage of this technique is that their speed and power consumption can be simply adjusted by altering the bias current of the gates without the need for resizing the devices. Therefore, is very suitable for mixed mode integrated circuits in order to reduce the digital inference between the analog and digital blocks. has large static power consumption due to its constant operation current. Recently, the low power designs have obtained quite some attentions [4-7]. P. Heydari and G. Caruso presented the methodologies for the low-power design of -based buffer chain and ring oscillators, respectively [4, 5]. Mohab H. nis et al. proposed the multi-threshold (MT) technology that allows the reduction of the minimum supply voltage of the two-level circuits, thus to lower the power dissipations of the circuits [6]. However, the analysis for MT presented in [6] was based on inaccurate long-channel modeling equations, which is inappropriate for today s nanometer CMO technologies. In [7], H. Hassan et al. presented a comprehensive MT analytical formulation based on the IM3v3 model. In this work, the standard cells of the high-speed lowpower circuits with near-threshold computing are developed. The basic standard cells include buffer/inverter, ND/NND, XOR/XNOR, multiplexer, and full adder. The layout, abstract design and standardcell characters of near-threshold basic cells are described at a NCU FreePDK 45nm technology. The 2- bit multiplier is verified by using the proposed cells. Near-threshold computing for circuits is investigated by scaling down the supply voltage. The results show that the power consumption of circuits that operate on near-threshold regions can be reduced without performance degrading. II. OPERTION OF CIRCUIT T NORML UPPL VOLTGE The basic buffer/inverter and its bias circuit are shown in Fig.. The inverter is composed of three main parts: the load transistors and, the full differential pull down switch network consisting of N and N2, and the current source transistor. The load transistors are designed to operate at a linear region with the help of the control voltage produced by the bias circuit, which also controls the output logic swings [8]. The pull-down network (PDN) NMO N and N2 are used to perform logic operation. The NMO is used to provide the constant current source, which is mirrored from the current source in the bias circuit. In the, the two signals and are generated from the bias circuit to ensure the proper operating for output voltage swings and to provide the constant bias current. Figure. uffer/inverter and its bias circuit. doi:.434/jcp

2 3 JOURNL OF COMPUTER, VOL. 8, NO., JNUR 23 is a type of differential logic with differential input logic tree. Therefore, the design of the PDN is similar to other differential logic styles such as DCVL and DL [9]. The complex logic functions can be realized by replacing N and N2 of the buffer/inverter shown in Fig. with NMO logic trees. The ND2/NND2, XOR2/XNOR2 and 2- MUX are shown in Fig. 2. Fig. 2 (a) is also called as universal logic gate, since it can realize the basic two-input logic functions (ND2/NND2, and OR2/NOR2). The additional transistor N5 improves the symmetry of the universal gate, thus to improve the performance of the gate in high-speed applications []. The more complex logic functions can be also realized by replacing N and N2 with NMO logic trees, which is similar to DCVL circuits. The three-input ND3/NND3 and XOR3/XNOR3 based on techniques are shown in Fig. 3. The operation of is performed in the current domain. The pull down network switches the constant current between two branches, and then the load converts the current to output voltage swings. The high and low digital logic levels are V OH = V and V OL = V - I R D, respectively, where R D is the PMO load resistance. The logic swing ΔV = V OH - V OL = I R D. V N3 N4 b N5 V N N2 b (a) ND2/NND2 (a) ND3/NND3 V b b (b) XOR2/XNOR2 V (b) XOR3/XNOR3 Figure 3. three-input gates. Db D D Db b (c) 2-MUX Figure 2. two-input basic gates. III. L OF CIRCUIT ND RE COMPRION In order to show energy efficiency and performance of the circuits, the basic gates have been realized with the NCU FreePDK 45nm technology. Full-custom layouts are drawn. Fig. 4 shows the layout of the two-input basic gates including uffer/inverter, ND2/NND2, XOR2/XNOR2 and 2- MUX.

3 JOURNL OF COMPUTER, VOL. 8, NO., JNUR 23 3 V VP V The layouts of the three-input ND3/NND3 and XOR3/XNOR3 are also realized, which are shown in Fig. 5. Fig. 6 shows the layout of the -bit full adder based on. IN N N2 INb In Inb V V b V P VN C Cb V V (a) uffer/invertwer V VP b V b C Cb b V N N3 N4 N b N5 N2 V b b b V (a) ND3/NND3 V P (b) ND2/NND2 VN C Cb C V V VP V b b Cb C b b b b b b (b) XOR3/XNOR3 V N VN Figure 5. The layouts of three-input gates. (a) ND3/NND3, and (b) XOR3/XNOR3. (c) XOR2/XNOR2 V P V VP Db V D D Db b b V b b b b b Co Cob Ci Cib VN (d) 2-MUX Figure 4. The layouts of two-input basic gates. V N Figure 6. The layout of -bit full adder based on.

4 32 JOURNL OF COMPUTER, VOL. 8, NO., JNUR 23 The layout areas among NCU FreePDK45nm OU_OC library, Nangate 45nm Open Cell library, and Cell library have been compared, as shown in Table I. TLE I. L RE COMPRION MONG NCU FREEPDK45NM OU_OC LIRR, NNGTE 45NM OPEN CELL LIRR, ND CELL LIRR Cell NCU FreePDK45nm osu_soc library rea (μm μm) Nangate 45nm Open Cell Library Library Inverter NND ND NND ND XOR XOR MUX Full adder IV. POT-L IMULTION OF CIRCUIT T NORML UPPL VOLTGE The optimization performance metrics of the gates mainly include propagation delay, power dissipation and power-delay product [-3]. Due to the operating constant current whenever it is either in activate mode or in standby mode, the power consumption of a gate is independent of the switching frequency, and it can been written as P = V I, () where V is the supply voltage, and I is the bias current of the gate. The delay time of a gate can be calculated assuming that, at each transition, the whole I, ideally, flows through one branch of the differential pair and charges the total load capacitance C, is given by t d C ΔV =.69 RC =. 69, (2) I Where I is the operating constant current, R is the equivalent resistance of one branch of the load PMO transistor, C is identical load capacitance on an output node, and ΔV is the output voltage swing that is generated from the bias circuit. The power-delay product is independent of the switching frequency and can be calculated as PDP = P t =. 69V ΔV C. (3) d For given source voltage V and bias current I, the power dissipation of gates is a constant value. It is independent of both the operation frequencies and fanouts. Therefore, the power of gates is also independent of the logic function. The power dissipation of conventional CMO circuits can be expressed as P CMO 2 = fv C, (4) L where f is operation frequency of conventional CMO circuits, and C L is load capacitance of conventional CMO circuits. The power dissipation of CMO circuits depends on the operation frequency linearly. Therefore, there exists a cross-frequency, above which a circuit is more power efficiency than the conventional one. It is importance to estimating the cross-frequency for using effectively circuits from the power efficiency point of view. There is a simple method to estimate the cross-frequency according to the power dissipations of the and conventional CMO gates. When PCMO=P, the cross-frequency f c can be derived as I f c =. (5) VCL It is assumed that the and conventional CMO circuits operate in the same supply voltage. ccording to (5), the cross-frequency f c can be estimated. The power dissipation and power-delay product can be optimized from () (3). n optimization has been carried out for the basic cells at the NCU FreePDK 45nm technology. Post-layout simulations have been carried out using HPICE, and full parasitic extraction is done. Fig. 7 shows comparison results of the energy dissipation of the basic gates per operating cycle among the NCU FreePDK45nm OU_OC library, Nangate Open cell library, and cell library. The operation frequency is 2GHz, and the supply voltage is.v. From Fig. 7, it can be seen that the power dissipation of basic gates is the smallest among the three cell libraries. Moreover, the power dissipations of all basic gates such as inverter, ND2/NND2, MUX2, and XOR2/XNOR2 are almost the same, and independent of their logic structure. The power dissipation of the XOR2/XNOR2 gates based on and conventional CMO circuits at different operation frequencies is shown in Fig. 8 at the NCU FreePDK 45nm technology and.v supply voltage. s the operation frequency rises from KHz to 2GHz, the power dissipations of the traditional CMO basic cells increase rapidly, while the cell keeps a constant value. From Fig. 8, the cross-frequency f c is about GHz. When the cells operate at higher frequencies than GHz, their power dissipation is lower than the traditional CMO cells. This character of circuits makes it fit for high-speed applications.

5 JOURNL OF COMPUTER, VOL. 8, NO., JNUR Nangate NCU FreePDK45 FreePDK45, the XOR2 based on attains about 46.5% and 87.% energy savings, respectively. 8 Nangate NCU FreePDK ND2 ND3 MUX2 XOR2 F 2 Figure 7. The energy dissipation comparisons of and conventional CMO basic gates at 2GHz and.v supply voltage upply voltage (V) Figure 9. The power dissipation of XOR2 based on and conventional CMO circuits at different supply voltages. Figure 8. The power dissipation of XOR2 based on and conventional CMO circuits at different operation frequencies and.v supply voltage. V. NER-THREHOLD COMPUTING FOR CIRCUIT Power dissipation of the circuits is equal to V I, where V is the supply voltage and I is the current flowing through the constant current source. Therefore, the power dissipation of the circuits can be saved by reducing either V or I. Reducing I would results in the increase of delay time and the decrease of the logic swings. Therefore, reducing the supply voltage is an effective method to lower the power consumption of the circuits. HPICE simulations have been carried out for the circuits by varying the source voltage from.v to.6v. Fig. 9 shows the energy dissipations of XOR2 based on and conventional CMO circuits at different supply voltages. From the curves, we can see that the energy per operation cycle dissipated in the XOR2 cell is lowest among the three circuits. Compared with the XOR2 used in Nangate and NCU VI. 2-IT MULTIPLIER Cell-based design flow has been widely used for digital chip designs with commercial ED tools. In order to realize a low-power chips, standard cell libraries should be constructed. The design of the standard cells could be carried for cells. The GD database can be generated by using the stream out function of IC54. Then, the auto place and route (P&R) library is created using this GD database. The synthesis library is generated by using the liberty NCX and HPICE. fter the layout design, the abstract view should be created in library Exchange Format (LEF) for standard cells. The generated abstracts are based on physical layout and logical data, process technology information. It is used in place of full layouts to improve the performance of place-and-route tools, such as Cadence Encounter. The LEF (Library Exchange Format) tech file can be read by the place-and-route tools. Therefore, LEF tech files should be generated for standard cells. To perform characterization, Liberty NCX should be used to run circuit simulations for the library cells to determine the cell behavior. The library can then be used for timing, power, and noise analysis with various tools such as DesignCompile and PrimeTime. For a characterization task, the template file must specify the PICE model file name, the PICE netlist directory, and the PICE simulator executable. The input and output library names should be also specified. fter the characterization, we can get a library in the liberty format (.lib) that can be used for timing and power analysis with various tools such as Design Compile. We can use the Library Compile tool from ynopsys capture this liberty (.lib) file and translates them into ynopsys internal database (.db) format for synthesis.

6 34 JOURNL OF COMPUTER, VOL. 8, NO., JNUR 23 In order to estimate effectiveness of the proposed cells, the 2-bit multiplier is verified by using the cells. The structure of the 2-bit multiplier is show in Fig.. Fig. and Fig. 2 show the schematic of the 2-bit multiplier. The layout of the 2-bit multiplier using cells is shown in Fig. 3. HPICE pre-layout and post-layout simulations are carried out for the 2-bit multiplier. Full parasitic extraction is done for post-layout simulations. The prelayout and post-layout simulated waveforms are shown in Fig. 4. From Fig. 4, the 2-bit multiplier based on the cells has the correct logic function. Figure 2. The schematic of the 2-bit multiplier with the bias circuit. V P b 2 2b 3b 3 b V b b b b V N Figure. The structure of the 2-bit multiplier. Figure 3. The layout of the 2-bit multiplier using the proposed cells. Pre layout Post layout Figure. The schematic of the 2-bit multiplier. Voltage (V) n n Time (s) 5n 2n Figure 4. The simulation waveforms of the 2-bit multiplier. 3 2

7 JOURNL OF COMPUTER, VOL. 8, NO., JNUR VII. CONCLUION is usually used for high-speed applications. The design methods of the high-speed low-power MO have been addressed in this paper. The layout implementations of basic gates are also presented at a NCU FreePDK 45nm technology. Full-custom layouts are drawn, and full parasitic extraction is done. The post-layout simulations are carried out. The results show that the basic gates can save more energy and have better performance than traditional CMO implementations used in Nangate and NCU FreePDK45 libraries at GHz or higher operation frequencies. In order to show energy efficiency and performance of the circuits in low-voltage applications, nearthreshold computing for circuits is investigated by scaling down the supply voltage from.v to.6v. The post-layout simulations show that the power consumption of circuits that operate on nearthreshold regions can be reduced without performance degrading. CKNOWLEDGMENT Project is supported by the Key Program of National Natural cience of China (No. 63), National Natural cience Foundation of China (No. 6749), cientific Research Fund of Zhejiang Provincial Education Department (No. Z298632), and Ningbo Natural cience Foundation (No. 262). REFERENCE [] M. amashina, H. amada, n MO current mode logic () circuit for low-power sub-ghz processor, IEICE Transactions on Electronics, vol. E75-C, no. 3, pp.8 87, 992. [2]. Tanabe,.8 m CMO -Gb/s multiplexer/demultiplexer ICs using current mode logic with tolerance to threshold voltage fluctuation, IEEE Journal of olid tate Circuits, vol. 36, no.6, pp , 2. [3] D. omasekhar and K. Roy. LVDCL: a high fan-in, high performance, low-voltage differential current switch logic family, IEEE Transactions on Very Large cale Integration (VLI) ystems, vol. 6, no. 4, pp , Dec [4] P. Heydari, Design and analysis of low-voltage currentmode logic buffers, In Proceedings of International ymposium on Quality Electronic Design, pp , 23. [5] G. Caruso,. Macchiarella, design methodology for low-power ring oscillators, 27 European Conference on Circuit Theory and Design, pp , 27. [6] M. H. nis, M. I. Elmasry, Power reduction via an MTCMO implementation of MO current mode logic, IEEE International IC/OC Conference, pp.93 97, 22. [7] H. Hassan, M. nisa and M. Elmasrya, Low-power multithreshold analysis, design, and variability, Microelectronics Journal, vol. 37, no., pp. 97-4, 26. [8] J. M. Musicer, J. Rabaey, MO current mode logic for low power low noise CORDIC computation in mixedsignal environments, In Proceedings of International ymposium on Low Power Electron, pp.2 7, 2. [9] D. omasekhar and K. Roy, Differential current switch logic: a low power DCV logic family, IEEE Journal of olid-tate Circuits, vol.3, no. 7, pp.98 99, July 996. [] O. M. bdulkarim and M. hams, symmetric MO current-mode logic universal gate for high speed applications, In Proceedings of the 7th CM Great Lakes ymposium on VLI, pp , 27. [] M. lioto, G. Palumbo, Design strategies for source coupled logic gates, IEEE Transactions on Circuits and ystems I: Fundamental Theory and pplications, vol. 5, no. 5, pp , 23. [2] H. Hassan, M. nis, and M. Elmasry, MO current mode circuits: analysis, design, and variability, IEEE Transactions on Very Large cale Integration (VLI) ystems, vol. 3, no. 8, pp , 25. [3] O. Musa, M. hams, n efficient delay model for MO current-mode logic automated design and optimization, IEEE Transactions on Circuits and ystems I: Regular Papers, vol. 57, no. 8, pp , 2. Jianping Hu was born in 96. He received the.. degree in Electrical and Electronic Engineering from Dalian Maritime University, Dalian, China, in 982. He received the M.. degree in IC Design from University of Electronic cience and Technology of China, Chengdu, China, in 988. He has been a teacher at Ningbo University ince 988. He is currently a professor in Faculty of Information cience & Technology at Ningbo University, Ningbo City, China. His current research interests focus on low-power digital nanometer circuits and analog integrated circuits. Prof. Hu got Ningbo Progress Prize in cience and Technology in 29. Haiyan Ni was born in 977. He received the.. degree in Electronic cience and Technology Engineering from Ningbo University, Ningbo, China, in 2. He is currently a M.c. student in Circuit & ystem at Ningbo University, Ningbo, China. His current research interests focus on lowpower digital integrated circuits and IC design. inshui Xia was born in 963. He received the.. degree in physics from Hangzhou University, Hangzhou, China, in 984. He received the M.. degree in semiconductor physics from Hangzhou University, Hangzhou, China, in 99. He received his doctoral degree from Napier University, Edinburgh, United Kingdom, in 23. He is currently a professor in Faculty of Information cience & Technology at Ningbo University, Ningbo City, China. His current research interests focus on ED design tools and logic synthesis. Prof. Xia got Zhejiang Progress Prize in cience and Technology in 2.