IEEE Std Mixed Signal Test Bus and Its Test Methodology. IEEE Std Test Methodology NCU EE

Transcription

1 IEEE Std Mixed Signal Tet Bu and It Tet Methodology P.

2 Content. IEEE Std. 49. Boundary Scan 2. IEEE Std Mixed Signal Tet Bu 3. Paraitic Effect Modeling and Removal 4. Analog Teting in a Noiy Environment 5. Crotalk Effect Modeling and Removal 6. Tet Signal Shaping P.2

3 Bibliography Mixed Analog Digital SoC Teting Analog Signal Metrology ATE Related Deign and Tet Application High Speed Serial Link and Communication Circuit Phone: X 4465 Fax: URL: P.3

4 Reference IEEE Std. 49. Tet Acce Port and Boundary Scan Architecture IEEE Std Mixed Signal Tet Bu C.C. Su, Y.T. Chen, and S.J. Jou, "Intrinic Repone for Analog Module Teting Uing Analog Tetability Bu," ACM Tranaction on Deign Automation of Electronic Sytem, Vol. 6, No. 2, April 200, pp C.C. Su and Y.T. Chen, "Intrinic Repone Extraction for the Analog Tet Bu Paraitic Effect Removal," IEEE Tran. On CAD, IEEE Tran. On Computer- Aided Deign of Integrated Circuit, Vol. 9, No. 4, April 2000, pp Y.T. Chen and C.C. Su, "Tet Waveform Shaping in Mixed Signal Tet Bu by Pre-Equalization," Proc. 200 VLSI Tet Sympoium VTS 200, Marina Beach, Lo Angle, U.S.A. to appear. Y.T. Chen and C.C. Su, Crotalk Effect Removal for Analog Meaurement in Analog Tet Bu, Proc IEEE VLSI Tet Sympoium VTS 2000, Montreal, Canada, May 2000, pp P.4

5 Reference C.C. Su, and Y.T. Chen, Analog Metrology and Stimulu Selection in a Noiy Environment, 999 Aian Tet Sympoium, Nov. 999, pp Y.T. Chen and C.C. Su, Analog Module Metrology Uing MNABST- P49.4 Tet Chip, Proc. IEEE Aian Tet Sympoium, C.C. Su, Y.T. Chen, and S.J. Jou, ``Paraitic Effect Removal for Analog Meaurement in P49.4 Environment," Proc. 997 IEEE Int'l Tet Conference, 997. C.C. Su, Y.R. Cheng, Y.T. Chen, and S. T, ``Analog Signal Metrology for Mixed Signal IC," Proc. 997 IEEE Aia Tet Sympoium, 997. C.C. Su, Yue-Tang Chen, Shyh-Jye Jou, and Yuan-Tzu Ting, ``Metrology for Analog Module Teting Uing Analog Tetability Bu," Proc. 996 Int'l Conf. on Computer Aided Deign, 996. C.C. Su, S.S. Chiang, S.J. Jou, ``Impule Repone Fault Model and Fault Extraction for Functional Level Analog Circuit Diagnoi," Proc. Int'l Conference on Computer Aided Deign, San Joe CA USA, pp P.5

6 49. - Baic Architecture Internal Logic TDI MISC R Intruction R Bypa R M U X TDO TMS TAP Controller TCK P.6

7 IEEE Signal MTM-Bu Mater MTM-Bu Slave MTM-Bu Slave n MMD: MTM Mater Data M2S MSD: MTM Slave Data S2M MPR: MTM Paue Requet S2M MCTL: MTM Control M2S MTCK: MTM Tet Clock 2MS P.7

8 IEEE Architecture Digital BM D Pin Internal A Bu 49. TAP TDI TDO TMS TCK IC Core P.8 A B M A B M TBIC TAP Controller AT AT2 Analog BM A Pin Analog TAP

9 Parametric Tet Environment IC Under Tet IC IC2 ICn CUT AT wire egment AT2 P.9

10 IR Extraction - Repone Meaurement Direct Loop Back? xt wt ht w2t yt Source Sink wt ht w2t Zinh Zin2 Y S = X S W S H S W2 S Z + Z Z + Z o inh oh in2 P.0

11 Simulation - SPICE - Different Waveform bt ht Extracted Intrinic Repone P.

12 Tet Environment P.2

13 Tet Environment - Meaurement P.3

14 Stimulu - Square Wave Selection Chart Tranfer Function Harmonic of Square Wave Combination of the Above Two Hz SQ at 2KHz P.4

15 Tet Reult - SNR = 36 db f x = 00Hz f = 02.4kHz M = 3.KHz P.5

16 P.6 IEEE Std Tet Methodology IR Extraction - Crotalk Meaurement C W H X C W C W H W H X W Y b b b b + = C W Y X C W Y W H X W b b b = W W2 C2 C2 H b xt yt Tet Repone of the buffer inertion x t

17 Simulation - Length 600 cm bt ht SNR=6.0 Extracted Intrinic Repone SNR=23.0 P.7

18 Previou Meaured Reult - ATS 98 MNABST- RS = 400 Ω fo = 8.84MHz fs =. 26MHz P.8

19 Tet Environment k Invere Filter xk Channel n k Σ y k CUT AD 8 K K 5.9p 5.9p AD 8 3K 5K 5K AD 8 3K 3K 3K HS = A vo + Q S w o + S w o 2 w o = 2pX0MHz A vo = 2 Q = P.9