Note: To reduce ripple,vcc2 5V should be supplied by regulator IC7805.

Transcription

1 1.SCOPE VHF/ TUNER,ANTENNAL LOOP THROUGH 4QAM(QPSK), 16,32,64,128 and 256QAM DEMODULATOR FOR DVB-C SYSTEM. Loop Through output via passive allocator 2.GENERAL S 2-1. RECEIVING FREQUENCY RANGE 51~858MHz(I 2 C PLL CONTROLLER FROM OUTSIDE) 2-2. SUPPLY VOLTAGE :B1 + 5V +/-0.25V ( DC Ripple <10mV) B2,B3,B4 +3.3V +/-0.1V ( DC Ripple <10mV) Note: To reduce ripple,vcc2 5V should be supplied by regulator IC CONSUMPTION CURRENT :B1 5V 40mA B2 3.3V 240mA B3 3.3V 180mA B4 3.3V 30mA 2-4. OPERATION AND STORAGE TEMPERATURE 0~50 O C CONDITIONS FOR GUARANTEE HUMIDITY 85% OR LESS 3.TEST CONDITIONS 3-1. TESTING AMBIENT CONDITIONS DEFINED AS TEMPERATURE OF 25+/-2 O C AND HUMIDITY OF 65+/-5% RH. NOTE : THAT TEMPERATURES OF 5~30 O C AND HUMIDITY OF 45~85% MAY BE REGARDED AS STANDARD. Aug. 29,

2 NO ITEM CONDITION MIN TYP MAX NOTES 1. GENERAL S 1.1 Receiving frequency range MHz 1.2 RF input impedance F CONNECTOR 75 OHM 1.3 RF output impedance F CONNECTOR 75 OHM 1.4 L.O PLL synthesizer IC MT2060 Address 0xC6 1.5 PLL synthesizer crystal +/- 50 ppm 16 MHz 1.6 1st intermediate frequency SEE 6.3 table MHz 2nd intermediate frequency BW 8 MHz 2. Humidity Operating less than 85% Storage less than 95% 2.1 Temperature Operation 0 o C to 55 o C Storage -20 o C to 75 o C% Aug. 29,

3 NO ITEM TEST CONNDITION Supply voltage Ambient humidity Ambient temperature Test circuit CONDITION B1+5V B2,B3,B4 3.3V 20 O C to 30 O C 60% to 70% MIN. TYP. MAX. NOTES Noise Figure RF AGC Range IF AGC Range Gain taper VSWR IF Rejection Image Rejection RF input oscillator leakage Phase noise offset 1KHz offset 10KHz offset 100KHz 1% cross modulation input Channel +/-2Channel level 60uV 0~3.3V 0~3.3V <890 MHz <1800 MHz <2150 MHz VHF HIGH VHF HIGH VHF HIGH VHF HIGH uv uv uv c/hz c/hz c/hz c/hz c/hz c/hz uv uv Aug. 29,

4 NO ITEM CNODITION NIM. TYP. MAX. NOTES. 4.4 B+1=5V Loop through specification Output VSWR 51MHz to 858MHz 3 75 OHM Gain variation +3 Noise figure -1 9 Spurious at loop through 6 26 uv 2nd order intermodulation rd order intermodulation F1+F2(200/500MHz) -50 Isolation RF out to IF test F1+F2+F3(600/620/625) -20 Isolation RF out to RF in -20 Loop through specification 4.5 B+1=0V Output VSWR 51MHz to 858MHz 3 75 OHM Gain Loss 2 5 Electrical Characteristics QAM Demodulator ST FEC DVB-C Annex A & C 5.1 Roll-off factor 0.13, Input sensivitity 64QAM 40 uv nominal ber of Msymb/s 256QAM MAX Input Level 64QAM 80 uv 256QAM 80 uv 5.4 Performance with AWGN 16QAM 18.3 nominal ber of Msymb/s 32QAM 21.3 Wanted signal 63uV 64QAM MHz 128QAM QAM Out DATA Format Serial,parallel 5.6 SYMBOL RATE Msps Aug. 29,

5 6.0MT2060 ADDRESS FIELD Table 1 Address Field MSB LSB Address Byte R/W Table 2 Serial Communications Register Map REGISTER MSB LSB ADDRESS B7 B6 B5 B4 B3 B2 B1 B0 DEF Part/Rev 00 PART REV 0x63 LO1C 1 01 LNABAND NUM1(5-2) 0x3F LO1C 2 02 DIV1 0x74 LO2C 1 03 FM1CA FM1SS NUM1(1-0) NUM2(3-0) 0x00 LO2C 2 04 NUM2(11-4) 0x08 LO2C 3 05 DIV2 NUM2(12) 0x93 LO Status 06 L1LK TAD1 L2LK TAD2 xx FM Freq 07 FMF xx Misc Status 08 FMCAL TEMP xx Misc Ctrl FMCG 0 GP02 GP01 0 0x20 Reserved 0A x1E Reserved 0B VGAG 0x31x LO1 Byte1 0C V1CSE xFF LO1 Byte2 0D 1 0 V1CS 0x80 Reserved 0E xFF Reserved 0F x00 Misc Ctrl x2C Misc Ctrl3 11 LOTO x42 Table 3 MT2060 Register Descriptions(Rev Code 3 or higher) FIELD REGISTER R/W BITS DEFAULT DESCRIPTION PART Part/Rev R 4 0x06 Part Code REV Part/Rev R 4 0x03 Revision Code LNABAND LO1C 1 R/W 4 0x03 LOW Noise Amplifier Band Number NUM1 LO1C 1,LO2C 1 R/W 6 0x03C LO 1 FracN Numerator DIV1 LO2C 2 R/W 8 0x74 LO 1 Divider FM1CA LO2C 1 R/W 1 0x00 Calibration Start Bit FM1SS LO2C 1 R/W 1 0x00 Calibration Single-Step Bit NUM2 LO2C 1,2,3 R/W 13 0x1080 LO 2 FracN Numerator DIV2 LO2C 3 R/W 7 0x59 LO 2 Divider L1LK LO Status R 1 xx LO 1 Lock Detect TAD1 LO Status R 3 xx LO 1 Tune Line ADC Calue L2LK LO Status R 1 xx LO 2 Lock Detect TAD2 LO Status R 3 xx LO 2 Tune Line ADC Calue FMF FM Freq R 8 xx Estimated First IF Center Frequency Offset(see Section 2.3) FM1CAL Misc Status R 1 0x00 Calibration Done Bit TEMP Misc Status R 2 xx On-Chip Temperature Sensor FMCG Misc Ctrl 1 R/W 2 0x03 Mixer 1 Cap Gain GPO Misc Ctrl 1 R/W 2 0x00 General-Purpose Output V1CSE LO 1 Byte 1 R/W 1 0x01 LO 1 VCO Automatic Capacitor Select Enable V1CS LO 1 Byte 1 R/W 6 0x00 LO 1 Capacitor Selection Value LOTO Misc Ctrl 3 R/W 4 0x04 LO Timeout VGAG Reserved 0x0B R/W 2 0x01 VGA Gain Range select Table 4 LNA Band Settings fin range (MHz) LNABAND Aug. 29,

6 6.1 TUNING STEPS Table 9 Tuning Steps STEP PROCESS 1 Calculate f LO1 =f IN +f IF1 = =1475.0MHz and f LO2 Since f LO1 is already a multiple of 250KHz,it does not need rounding. f LO2 =f LO1 -f in -f OUT = = MHz Since f LO2 is already a multiple of 50.0KHz, it does not need rounding. 2 Avoid Spurs Use the procedurss outlined in Aplication Note AN-00079, Avoidong LO-Related Spurs in Dual-Conversion Micro Tuner TM Products, to detect and adjust for LO-Related spurs. The spur-avoid procedure detects a spur at: f SPUR = MHz=(8 x f LO1 )-(10xf LO2 ) As a result, it adjusts the LO frequencies so that: f LO1 =f LO1 +4.0x250KHz = MHz f LO2 =f LO2 +4.0x250KHz= MHz This places the IF1 center requency at MHz 3 Choose Use Table 4 on page 5 to determine the correct LNABAND setting for an LNABAND input frequency of 384 MHz LNABAND = 0x9 4 Calculate DIV 1 =floor(f LO1 /16MHz)=floor(1476MHz/16MHz)=92 MT2060 NUM 1 =(64x(f LO1 (mod f REF )))/f REF registers =(64x1476MHz(mode 16MHz)))/16MHz =(64x4MHz)/16MHz=16 DIV 2 =floor(f LO2 /16MHz)=floor( MHz/16MHz)=74 NUM 2 =floor(8192x(f LO2 (mode 16MHz)/16MHz)+0.5) =floor(8192x( mhz(mode 16MHz)/16MHz)+0.5) =floor(8192x(0.85mhz/16mhz)+0.5) =floor(8192x( )+0.5)=floor(435.7)=435 5 Write MT2060 To summarize the calculations, the values to be written via the serial bus Registers 1-5 are: (order is) DIV 1 =92=0x5C important NUM 1 =16=0x10 DIV 2 =74=0x4A NUM 2 =435=0x01B3 Therefore,using the MT2060 register map information starting on page 13 and the instructions in Table2, Writing MT2060 Regusters, the registers are written as: Register Value 0x0C = 0xFF 0x01 = 0x94 0x02 = 0x5C 0x03 = 0x03 0x04 = 0x1B 0x05 = 0x MT2060 Initialization Steps STEP PROCESS 1 Write MT2060 Register Value registers. 0x0B = 0x31 Aug. 29,

7 6.3 The 1st IF filter is inside MT2060 chipset. We find the best frequency of MT2060 with RF Network Analyzer and write in EEPROM which is built-in in the silicon tuner. To get the best sensitivity,the user should read the value of the 1st IF filter from EEPROM and use it for equation of LO1 & LO2. TABLE 5 (Read 1st IF Frequency value) Aug. 29,

8 Aug. 29,