COMTECH TECHNOLOGY CO., LTD. MDVBT-7K8E SPECIFICATION

Transcription

1 1.SCOPE The MDVBT-7K8E is intended for the reception of DVB-T compliant MPEG2 signals (full TES compliant) in combination with the tuner, all functions are integrated to deliver a corrected stream given DVB-T encoded signal (2k or 8k mode) with 7MHz or 8MHz bandwidth. 2.GENERAL S 2-1. RECEIVING FREQUENCY RANGE VHF HI :177.5~226.5MHz :474~862MHz (I 2 C PLL CONTROLLER FROM OUT SIDE) 2-2. Temperature Range Storage Temperature : -20 o C ~ + 80 o C Operation Temperature : 0 o C ~ + 50 o C 2-3. Weight : 20.6g 2-4 Holding strength of ant jack Initial Inserting Force Extracting Force After 5 Cycles :Max. 5.0 kg :Min. 0.7 kg 3.TEST CONDITIONS 3-1. Test conditions : All data held under following conditions : +25+/-2 o C / Humidity : 45 ~ 65% RH 3-2. SUPPLY VOLTAGE :B1,B2, 5V +/-2% Ripple < 7mV B3 1.8V +/-2% Ripple < 7mV B4 3.3V +/-2% Ripple < 7mV Jan. 22,

2 4.Electrical Specification NO ITEM CONDITION MIN TYP MAX NOTES 4-1. GENERAL S 4-2. Receiving frequency range MHz Mergin frequency MHz RF input impedance IEC CONNECTOR 75 OHM 4-5 L.O PLL synthesizer IC TDA6651 Address 0xC0 4-6 PLL synthesizer crystal +/- 30 ppm 4.0 MHz 4.7 1st intermediate frequency DVB-T MHz 3 BW 8 MHz 4-8 AGC voltage input external 0V to 5V 0V min gain Current 5V max gain 20uA max 4-9 CONSUMPTION CURRENT :B1 5V 110 ma B2 5V 30 ma B3 1.8V 180 ma B4 3.3V 3 ma 4-10 IF Test circuit Noise Figure AGC Range AGC voltage 5V to 0.5V Gain taper VSWR IF Rejection Image Rejection RF input oscillator leakage Phase noise offset 1KHz offset 10KHz offset 100KHz 1% cross modulation input Channel +/-2Channel level 60uV VHF LOW <890 MHz <1800 MHz uv uv c/hz c/hz c/hz c/hz c/hz c/hz uv uv Jan. 22,

3 NO. ITEM CONDITION MIN. TYP. MAX. NOTES. 5.0 Electrical Characteristics Control refer to DiB7000PB data sheet 5.1 C/N in AWGN 8K 64QAM R7/ MHz,G1/4,RF=50m 8K 64QAM R2/ RS uncorrected error=0 8K 64QAM R1/ K 16QAM R3/ K 16QAM R2/ K QPSK R1/ Sensitivity in AWGN 8K 64QAM R7/8-72 m 8MHz,GI=1/4 8K 64QAM R2/3-76 m RS uncorrected error=0 8K 64QAM R1/2-80 m 8K 16QAM R3/4-81 m 8K 16QAM R2/3-84 m 8K QPSK R1/2-91 m 5.3 C/N in 0 Echo 8K 64QAM R3/ MHz,658MHz,G1/4,RF=-50m 8K 64QAM R2/ Crition:Picture Quality 5.4 Echo Outside Guard Interval 8K 64QAM R=3/4 GI=1/4 -/+260uS 15 (PATH LOSS) RS uncorrected error=0 8K 64QAM R=2/3 GI=1/8 -/+260uS 12 (PATH LOSS) 8MHz,658MHz,RF=-50m 5.5 Frequency Offset 8K,8MHz,64QAM,R2/3, KHz G1/8,-60m 5.6 Immunity to Digital ACI 8K,64QAM,R=3/4,GI=1/4(N+/-1) 28 8MHz,658MHz 8K,64QAM,R=2/3,GI=1/8(N+/-1) 28 RS uncorrected error=0 5.7 Mobile Performance 2K,16QAM,R=3/4,GI=1/4 300 km/h RF Level=-50m,658MHz 8K,64QAM,R=1/2,GI=1/4 105 km/h 8MHz,C/N=OFF 8K,64QAM,R=2/3,GI=1/4 80 km/h Average Packet Error Rate <5x10-3 Jan. 22,

4 Notice: To gain good sensitivity under 64QAM, code rate: 7/8 please supply PIN 3, B1 5V respectively; Please do not share voltage with other system. PIN 1 (TU) is for engineering test purpose. For regular application, please do not connect. PIN 8 (RESET) has IF output for engineering tuning purpose. For regular application, please connect 2.2K resistor near PIN 8 and 1nF capacitor to ground. PIN 2 (ANT B+), for regular application, please do not connect. If there is ANT (ANT + RF AMP), please supply proper voltage to ANT. Notice:The current should not be over 100mA. To prevent ANT DC short, current protection circuit is necessary if PIN 2 is supplied with voltage. PCB circuit will be burned out if the current is over 300mA. Jan. 22,

5 5.0 Programming of tuner PLL The tuner control (frequency selection and band switching) is done via the I 2 C bus. One address byte and four data bytes are needed to fully program the tuner. A PLL lock flag can be read from the tuner during READ -mode. I 2 C-bus data format, WRITE -mode: NAME BYTE MSB LSB ACK Address byte R/W=0 A Prog.Divider Byte N14 N13 N12 N11 N10 N9 N8 A Prog.Divider Byte 2 3 N7 N6 N5 N4 N3 N2 N1 N0 A Control Data Byte D/A= R2 R2 R0 A 4 1 D/A=0 0 0 ATC AL2 AL1 AL0 Control Data Byte2 5 CP2 CP1 CP0 SP5 SP4 SP3 SP2 SP1 A A=acknowledge Timing of program sequences: Because of the Tuner-PLL frequency divider setting time of min. 50usec.,the occurrence of any other I 2 C traffic start condition present within that periode on the Bus will disturb the divider and result in a not peoperly tuned tuner VCO. Each time the Tuner-PLL frequency divider has been programmed, a 50usec wait becomes necessary before continuing the I 2 C bus traffic. Following table demonstrates a correct program sequence: Jan. 22,

6 Description of used symbols: R/W N14 to N0 D/A R2,R1,R0 ATC AL2,AL1,AL0 CP2,CP1,CP0 SP5...SP1 :Read / Write bit ; Bit = 0 => Write mode Bit = 1 => Read mode :LO frequency divider bits :D/A = 1 => follwing 6 bits contain test and reference divider ratio data :D/A = 0 => follwing 6 bits contain AGC setting data :reference divider bits (see table:reference Divider Settings) :AGC time constant data bit; only valid with int.agc loop active ATC = 1 => enables fast tuning speed during channel search mode ATC = 0 => recommended after channel acquisition;nomal mode :AGC Take-Over-Point bits (see table:internal AGC loop TOP) :PLL charge pump current selection bits(see table:charge Pump Settings) :Switch ports; bit = 1 => port V out is ON bit = 0 => port V out is OFF (see table:band and SAW-filter selection table) N14 to N0: programmable divider bits divider ratio: N=N14x2 14 +N13x N1x2 1 +N0 How to calculate the divider ratio N : (f input +f IF Hz 4x10 6 N= whereby f ref = [Hz]=62.5kHz f ref Hz 64 (1) 4x10 6 f ref = [Hz]=166.67kHz 24 (1) Note (1) :divider ratio to be set with Bits;R2...R0 (see table below) Do not set the divider ratio as such that the tuner is tuned into extreme conditions i.e.far below or far above the specified ranges. Jan. 22,

7 R2,R1,R1: PLL reference divider settings (Control Data Byte 1 ): PLL step size PLL ref. divider ratio R2 R1 R0 50.0kHz kHz kHz AL2,AL1,AL0: AGC Take-Over-Point bits(control Data Byte 1 ): AL2 AL1 AL0 Typical TOP Level Remarks TOP = 124uVpp TOP = 121uVpp TOP = 118uVpp TOP = 115uVpp TOP = 112uVpp TOP = 109uVpp I AGC = 0 External AGC(1) V AGC = 3.5V Loop disabled(2) Note 1: The tuner internal AGC current sources are disabled (default mode after power on reset). Note 2: The tuner internal AGC detector is disable. With no external AGC voltage applied to the tuner, the RF-gain is always set to maximum. Jan. 22,

8 CP2,CP1,CP0:PLLcharge pump current settings Note: during search tuning it is recommended to set the PLL to a moderate charge pump. To enable best oscillator phase nosie performance during digital signal processing, the PLL charge pump current should be set to conditions as given with following table. In analog applications the PLL charge pump current must be set to max. 60uA! CP2 CP1 CP0 Typical CP current Recommendations ua ua ua To be used during search tuning and for 50 khz, 62 khz PLL step sizes ua VH : 161MHz - 254MHz U : 446.1MHz - 584MHz ua ua VH : 254.1MHz - 384MHz U : 584.1MHz - 794MHz ua VH : >384.1MHz U : >794.1MHz SP5...SP1:Band selection table SP5 SP4 SP3 SP2 SP1 VHF Hi band X X band X X I 2 C- bus data format, RADE - mode: Name MSB LSB Address byte R/W=1 A Status byte POR FL 0 1 AGC A A : Acknowledge POR = power-on-reset-flag ; POR = 1 on power-on FL = in-lock-flag ; FL = 1 when PLL is phase locked AGC = internal AGC flag ; AGC = 1 when internal AGC is active Jan. 22,

9 6. Electorstic discharge 6.1 Test Each front-end must be capable of normal performance following its subjection to the following tests: MIL STD 883C HBM Test is performed with a voltage discharge from a 100 PF capacitor over a 1500 OHM series resistance in the discharge path. There is a direct contact between the test probe head and the unit under test, using the test points and conditions detailed below: o Test to pins 1 through 22: 3 successive ESD discharges of +/-2 KVDC between each pin and the front-end frame. IEC Test is performed with a voltage discharge from a 150 PF capacitor over a 330 OHM series resistance in the discharge path. There is a direct contact between the test probe head and the unit under test, using the test points and conditions detailed below: o Test for antenna input socket +/-8 KVDC o Test for antenna output socket +/-5 KVDC 6.2 Handling Anyone handling a front-end must wear a properly grounded anti-static discharge bracelet to minimize ESD damage. After each front-end is aligned and tested, it will be packed with anti-static material prior to transportation and storage. This package is to remain in place until the front-end is assembled and soldered onto the receiver main board. Jan. 22,

10 7 Reliability test procedure & conditions Note:Room temperature = 25 o C +/- 2 o C 7.1 Heat load test o Measure the DUTs at room temperature o Load the DUTs into chamber of the following conditions: Temperature = 60 o C Period = 500 hrs Cycle = 1.5 hrs on; 0.5 hrs off Quantity = 10 pcs o Cool-down 0,5 hr at room temperature, then measured the DUTs within 1 hr o The test shall be continued to 1000 cycles for information only 7.2 Humidity load test o Measure the DUTs at room temperature o Load the DUTs into chamber of the following conditions: Temperature = 40 +/- 5 o C Period = 24 hrs Cycle = constantly on Quantity = 24 pcs o Cool-down 0.5 hr at room temperature, then measured the DUTs within 1 hr o Load the DUTs again into chamber of the following conditions: Temperature = 40+/-5 o C Humidity = 90 to 95% Period = 500 hrs Cycle = 1.5 hrs on; 0.5 hr off Quantity = 20 pcs o Cool down 0.5hr at room temperature, then measured the DUTs within 1 hr Jan. 22,

11 7.3 Cold test o Measure the DUTs at room temperature o Load the DUTs into chamber of the following conditions: Temperature = -2 +/-5 o C Period = 500 hrs Cycle = constantly on Quantity = 10 pcs o Warm up for 2 hrs at room temperature, then measured the DUTs within 1 hr 7.4 Thermal shock o Measure the DUTs at room temperature o Load the DUTs into chamber of the following conditions: Temperature = -25 o C for 60 min Period Power Quantity 80 o C for 60 min = 200 cycles = power off = 10 pcs o Cool-down 0,5 hr at room temperature then measured the DUTs within 1 hr 7.5 Temperature cycle test o Measure the DUTs at room temperature o Load the DUTs into chamber of the following conditions: Temperature = -5 o C for 16 hrs then 60 o C for 8 hrs Period = 500 hrs Cycle = constantly on Quantity = 10pcs o Cool down 0.5 hr at room temperature, then measured the DUTs within 1 hr o Load the DUTs again into chamber of the following conditions: Temperature = 40 +/- 5 o C Humidity = 90 to 95% Period = 500 hrs Cycle = 1.5 hrs on; 0.5 hrs off Quantity = 10 pcs o Cool down 0.5 hr at room temperature, then measured the DUTs within 1hr Jan. 22,

12 7.6 Vibration test o Frequency: o Vertical amplitude: o Duration: o Quantity: 3.5 Hz 15 to 25 mm 1 hr 1 carton 7.7 Drop test o Packaged apparatus: <or = 50 kg o Height: depend on weight o 1 corner + 3 edge + 6 faces Drop on the weakest corner ( point G ) Drop on the shortest edge on contact with point G Drop on average edge in contact with point G Drop on the longest edge in contact with point G Drop flat wise on the side of minimum surface Drop flat wise on the side of opposite minimum surface Drop flat wise on the side of avarage surface Drop flat wise on the side of opposite avarage surface Drop flat wise on the side of maximum surface Drop flat wise on the side of opposite maximum surface o Quantity :1 carton 7.8 Life test o Measure the DUTs at room temperature o Load the DUTs into chamber of the following conditions: Temperature = 60 o C Period = 500 hrs Cycle = constantly on Quantity = 20 pcs o Cool down 0.5 hr at room temperature, then measure the DUTs within 1hr Jan. 22,

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