MHZ APPLICATION EXAMPLE

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Randell Hill
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1 Preliminary PT4306 Compact MHz OOK/ASK Receiver DESCRIPTION The PT4306 is a compact, fully integrated OOK/ASK receiver for MHz frequency band. It requires few external components. The PT4306 consists of a low-noise amplifier (LNA), image-rejection mixer (IRM), built-in channel-select filter (CSF), OOK/ASK demodulator, data filter, and data slicing comparator. The local oscillator (LO) sub-system incorporates a monolithic VCO, 32 feedback divider, loop filter and fast start-up reference oscillator to form a complete phase-locked loop-based frequency synthesizer for single channel applications. FEATURES Normal operating of 4.6 ma at MHz Requires few external components Achieves sensitivity of 112 dbm (peak ASK signal level) Supply voltage range: 2.4 to 5.5 V Supports data rates up to 10 Kb/s Wide input dynamic range with automatic gain control handling Image-rejection ratio of 25 db The PT4306 is available in an 8-pin SOP package and is specified over the temperature range from 40 to +85 C. APPLICATIONS Automotive Remote Keyless Entry (RKE) Remote control Garage door and gate openers Suitable for applications that must adhere to either the European ETSI or the North American FCC (Part 15) regulatory standards BLOCK DIAGRAM XIN 8 VSS 1 PLL Reference Oscillator I Q CSF (BPF) Limiter 7 CTH ANT 2 LNA IRM Buffer Amplifier RSSI Data Filter (LPF) 6 DO VREG 3 On-Chip Regulator 4 5 VDD5 EN Tel: Fax: F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan

2 MHZ APPLICATION EXAMPLE U MHz 10 pf 1.5 pf 1 VSS XIN 8 Etched Inductor on PCB 39 nh VDD5 100 nf 2 ANT 3 VREG PTC PT4306-S CTH 7 DO 6 4 VDD5 EN 5 47 nf VDD5 PRE1.0 2 January 2015

3 EVALUATION BOARD SCHEMATIC U1 C5 C1 1 VSS XIN 8 L2 L1 VDD5 R1 C2 2 ANT 3 VREG PTC PT4306-S CTH 7 DO 6 4 VDD5 EN 5 C4 VDD5 R2 C3 BILL OF MATERIALS Part Value Unit Description L1 39 n H Antenna input matching, coil inductor L2 56 n H Antenna ESD protection, coil inductor (optional) C1 1.5 p F Antenna input matching C2/C3 100 n F Power supply de-coupling capacitor C4 47 n F C TH, affects coding type and start-up time C5 10 p F Dependent upon crystal oscillator vendor; for frequency fine-tuning (optional) R1 10 Ω Power supply de-coupling resistor (optional) R2 1.2 M Ω For reducing data output noise (optional) X MHz Crystal with C Load = 10 pf, for reference oscillator U1 PT4306 IC U1 Receiver chip Notes: 1. L1 and C1 are the components for input matching network. They may need to be adjusted for different PCB layout and antenna requirements. 2. The value of C4 depends upon the data rate and coding pattern. 3. The optional components may be used depending upon specific application requirements. PRE1.0 3 January 2015

4 ORDER INFORMATION Valid Part Number Package Type Top Code PT4306-S 8 Pins, SOP, 150 mil PT4306-S PIN CONFIGURATION VSS 1 8 XIN ANT VREG 2 3 PT4306-S 7 6 CTH DO VDD5 4 5 EN PIN DESCRIPTION Pin No. Pin Name I/O Description 1 VSS G Ground 2 ANT I RF input connected to antenna via a matching network 3 VREG P Regulated core voltage 4 VDD5 P 5 V regulator input 5 EN I Chip enable (tie HIGH to enable the chip) 6 DO O Data output 7 CTH I/O Connection for data slicing threshold capacitor 8 XIN I Reference oscillator input PRE1.0 4 January 2015

5 FUNCTION DESCRIPTION POWER SUPPLY PT4306 The PT4306 provides an internal voltage regulator (pin 3) to supply the core blocks, and it has to be connected with a bypassing capacitor, placed as close as possible. The VDD5 pin (pin 4) should connect to the external supply voltage and should incorporate series-r, shunt-c filtering. The PT4306 chip can operate in the supply voltage range from 2.4 V to 5.5 V. RF FRONT-END The RF front-end of the receiver employs a super-heterodyne configuration that down-converts the input radio frequency (RF) signal to an intermediate frequency (IF) signal. According to the block diagram, the RF front-end consists of an LNA and an image rejection down-conversion mixer, and the in-phase (I) and quadrature (Q) local oscillator (LO) signals for the mixer are generated from the PLL frequency synthesizer. A special feature of the PT4306 is its integrated double-balanced image-rejection mixer (IRM), which eliminates the need for a costly front-end SAW filter for many applications. The advantages of not using a SAW filter include simplified antenna matching, less board space, and lower BOM cost. The mixer cell consists of a pair of double-balanced mixers that perform an I-Q down-conversion of the RF input to the IF band with high-side injection (i.e. frf = flo fif). The image-rejection circuit then combines these signals to achieve an image-rejection ratio typically over 25 db. High-side injection is mandatory (e.g. low-side injection may not be selected) due to the nature of the on-chip image rejection implementation. The IF output of IRM is connected to a buffer amplifier to drive the succeeding IF-band, channel-select filter (CSF). The ANT pin can be matched to 50 Ohm with an L-type circuit. Inductor L1 and capacitor C1 values may be different from table depending on PCB material, PCB thickness, ground configuration, and the length of traces used in the layout. ANTENNA PIN ESD PROTECTION The PT4306 IC provides the ESD protection level (Human Body Mode) better than 4 KV at the ANT pin. However, higher ESD protection level may still be required at the system level for some applications. Achieving an enhanced ESD protection level may need to rely on the external components. Changing L1 from SMD type to coil type could enhance ESD protection level up to 1 KV, and adding a shunt coil inductor L2 of 56 nh (can either use an etched inductor on PCB) in front of C1 may help to further improve ESD protection. C1 2 ANT Etched Inductor on PCB L2 L1 PRE1.0 5 January 2015

6 REFERENCE OSCILLATOR PT4306 All timing and tuning operations on the PT4306 are derived from the internal one-pin Colpitts reference oscillator. When a crystal is used, the minimum oscillation voltage swing is 300 mv PP. As with any super-heterodyne receiver, the mixing product between the internal LO (local oscillator) frequency, f LO, and the incoming transmit frequency, f TX, must ideally equal the IF center frequency, f IF. The following equations may be used to compute the appropriate f LO for a given f TX : f LO = f TX (352 / 351) for MHz band. Hence, f IF = f TX 351. Using the above equations, frequencies f TX and f LO are computed in MHz. High-side LO injection results in an image frequency above the frequency of interest. For a given value of f LO, the equation below may be used to compute the reference oscillator frequency, f REFOSC : f REFOSC = f LO 32. So that the f REFOSC is MHz for the PT4306 chip (high-side LO mixing). PHASE-LOCKED LOOP (PLL) The PT4306 utilizes an integer-n PLL to generate the receiver LO. The PLL consists of a voltage-controlled oscillator (VCO), reference crystal oscillator, asynchronous 32 fixed-modulus divider, charge pump, loop filter and phase-frequency detector (PFD). All components are integrated on-chip. The PFD compares two signals and produces an error signal that is proportional to the difference between the input signal phases. The error signal passes through a loop filter that provides a loop bandwidth of approximately 200 KHz, and is used to control the VCO. The VCO output frequency is fed back through the fixed-modulus frequency divider to one input of the PFD. The other input to the PFD comes directly from the reference crystal oscillator. Thus, the VCO output frequency, which is used as the LO frequency, is phase-locked to the reference frequency and f REFOSC = (f TX + f IF ) 32 = f LO 32. The block diagram below illustrates the basic elements of the PLL. CHANNEL-SELECT FILTER PT4306 embeds a channel-select filter (CSF) with a bandwidth of approximately 380 KHz. The CSF utilizes a sixth-order active filter for the low-if architecture. An automatic frequency tuning circuit is also included on-chip and its absolute reference clock is derived from the reference crystal oscillator. The automatic frequency tuning circuit centers the pass-band of the CSF at the IF frequency (f IF ). PRE1.0 6 January 2015

7 ASK DEMODULATOR PT4306 The OOK/ASK demodulation is done by comparing the received signal strength indicator (RSSI) signal level. The RSSI signal is decimated and filtered in the data filter and the data decision is then completed by the slicing comparator. The RSSI is implemented as a successive compression log amplifier following by the internal CSF. The log amplifier achieves ±3 db log linearity; the RSSI output level has the dynamic range of around 60 db without turning on the automatic gain control (AGC) circuitry and of over 85 db when the AGC circuitry is turned-on. The RSSI slope is approximately 11 mv /db. DATA FILTER The data filter (post-demodulator filter) is utilized to remove additional unwanted spurious signals after the OOK/ASK demodulator. The data filter is implemented as a 2 nd -order low-pass Sallen-Key filter. The data filter bandwidth (BW DF ) has be fixed to 5 KHz. According to the application requirement, the shortest pulse-width of the data pattern should be set according to the following equation BW DF = 0.65 / Shortest pulse-width DATA SLICER The purpose of the data slicer is to take the analog output of the data filter and convert it to a digital signal. Extraction of the DC value of the demodulated signal for purposes of logic-level data slicing is accomplished using the external threshold capacitor C TH and the on-chip resistor R TH, shown in the block diagram. Slicing level time constant values vary somewhat with decoder type, data pattern, and data rate, but typical values range from 2 ms to 20 ms. Optimization of the value of C TH is required to maximize range. The first step in the process is selection of a data-slicing-level time constant. This selection is strongly dependent on system issues including system decode response time and data code structure. The effective resistance of R TH is 32.5 K Ω and a τ of 3x the period of longest LOW or HIGH bit stream is recommended. Assuming that a slicing level time constant τ has been established, capacitor C TH may be computed using equation C TH = τ / R TH A standard ±20 % X7R ceramic capacitor is generally sufficient. DATA SQUELCHING During quiet periods (no signal), the data output (DO pin) varies randomly with noise. Most decoders can discriminate between this random noise and actual data, but for some systems, the random toggling does present a problem. There are two possible approaches to reduce this output noise: 1. Implement analog squelch by raising the demodulator threshold. 2. Add an output filter in order to filter the (high frequency) noise glitches on the data output pin. The simplest solution is add analog squelch by introducing a small offset, or squelch voltage, on the CTH pin so that noise does not trigger the internal slicer. Usually 20 mv to 30 mv is sufficient and may be achieved by connecting a several mega-ohm resistor from the CTH pin to the internal supply voltage. The squelch-offset requirement does not change as the local noise strength changes from installation to installation. Introducing squelch will reduce both sensitivity and the receiving dynamic range. Only an amount of offset sufficient to quiet the output should be introduced. Typical squelch resistor is around 1.2 M. The circuit drawn below shows an application example of analog squelch, where R4 is the squelch resistor. The demodulated data then enters into a quasi-mute state as the RF input signal becomes very small (when there is no RF PRE1.0 7 January 2015

8 signal received or the RF signal is too small) and the DO output remains mostly at a logic LOW level. If the environment is very noisy, the value of R4 may be reduced to achieve better immunity against noise, but at the cost of loss of sensitivity. From Data Filter R TH Data Slicer VREG 3 7 R2 CTH 6 DO C2 C4 SENSITIVITY AND SELECTIVITY In digital radio systems, sensitivity is often defined as the lowest signal level at the receiver input that will achieve a specified bit error ratio (BER) at the output. The sensitivity of the PT4306 receiver is typically 112 dbm (ASK modulated with 2 Kb/s, 50% duty cycle square wave) to achieve a 0.1% BER (with input was matched to a 50 Ω signal source). The selectivity is governed by the response of the receiver front-end circuitry, the CSF (on-chip active IF filter), and the data filter. Note that the CSF provides not only channel selectivity, but also the interference rejection. Within the pass band of the receiver, no rejection for interfering signals is provided. POWER-DOWN CONTROL The chip enable (EN) pin controls the power on/off behavior of the PT4306. Connecting EN to HIGH sets the PT4306 to its normal operation mode; connecting EN to LOW sets the PT4306 to standby mode. The chip consumption current will be lower than 1 A in standby mode. Once enabled, the PT4306 relies on an internal fast start-up circuit to achieve a start-up time < 4 ms to recover received data at 3-dB above the minimum received RF input level. The following figure exhibits the system start-up time in the conditions of Temp=27ºC, f RF = MHz, P RF = 109 dbm, C TH = 47 nf and D RATE = 2 Kb/s. The EN pin is triggered every 500 ms. PRE1.0 8 January 2015

9 ANTENNA DESIGN PT4306 For a λ/4 dipole antenna and operating frequency, f (in MHz), the required antenna length, L (in cm), may be calculated by using the formula L 7132 f For example, if the frequency is MHz, then the length of a λ/4 antenna is 16.4 cm. If the calculated antenna length is too long for the application, then it may be reduced to λ/8, λ/16, etc. without degrading the input return loss. However, the RF input matching circuit may need to be re-optimized. Note that in general, the shorter the antenna, the worse the receiver sensitivity and the shorter the detection distance. Usually, when designing a λ/4 dipole antenna, it is better to use a single conductive wire (diameter about 0.8 mm to 1.6 mm) rather than a multiple core wire. If the antenna is printed on the PCB, ensure there is neither any component nor ground plane underneath the antenna on the backside of PCB. For an FR4 PCB (ε r = 4.7) and a strip-width of 30 mil, the length of the antenna, L (in cm), is calculated by L 4 c f PCB LAYOUT CONSIDERATION r where c is the speed of light (3 x10 10 cm/s). Proper PCB layout is extremely critical in achieving good RF performance. At the very least, using a two-layer PCB is strongly recommended, so that one layer may incorporate a continuous ground plane. A large number of via holes should connect the ground plane areas between the top and bottom layers. Note that if the PCB design incorporates a printed loop antenna, there should be no ground plane beneath the antenna. Careful consideration must also be paid to the supply power and ground at the board level. The larger ground area plane should be placed as close as possible to all the VSS pins. To reduce supply bus noise coupling, the power supply trace should be incorporate series-r, shunt-c filtering as shown below. Power Supply R 10 C 100n C' 47p 4 VDD5 PRE1.0 9 January 2015

10 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Min. Max. Unit Supply Voltage Range V DD V Analog I/O Voltage V Digital I/O Voltage V Operating Temperature Range T A C Storage Temperature Range T STG C PACKAGE THERMAL CHARACTERISTIC Parameter Symbol Condition Min. Typ. Max. Unit From Chip Conjunction Dissipation to Rja External Environment T A = 27 C C/W From Chip Conjunction Dissipation to Rjc Package Surface PRE January 2015

11 ELECTRICAL CHARACTERISTICS Nominal conditions: V DD5 = 5.0 V, V SS = 0 V, f RF = MHz, CE = HIGH, T A = +27 C. Parameter Symbol Conditions Min. Typ. Max. Unit General Characteristics Supply Voltage V DD5 Supply voltage applied to VDD5 pin only V Current Consumption I DD ma Standby Current I STBY CE = LOW 1 μa Operating Frequency Range f RF MHz Maximum Receiver Input Level P RF,MAX dbm ASK 2, D RATE = 2 Kb/s, Sensitivity 1 Peak power level S IN dbm OOK, D RATE = 2 Kb/s, Peak power level Data Rate D RATE 2 10 Kb/s System Start-Up Time T STUP ms RF Front-End Image Rejection Ratio IRR db LO Leakage L LO Measured at antenna input 80 dbm IF Section IF Center Frequency f IF MHz IF Bandwidth BW IF 380 KHz RSSI Slope SL RSSI mv/db Receive Modulation Duty Cycle DUTY % Demodulator Post-Demodulator Filter Bandwidth BW DF 5.0 KHz CTH Leakage Current I ZCTH T A = +85 C ±100 na Phase-Locked Loop Reference Frequency f REFOSC MHz Reference Signal Voltage Swing 3 V REF Peak-to-peak voltage (V PP ) V VCO Frequency Range f VCO MHz Divider Ratio DIV 32 Digital/Control Interface Input-High Voltage V IH For CE pin 0.8 V DD5 V Input-Low Voltage V IL For AGCDIS, CE, FDIV, SELA and SELB pins 0.2 V DD5 V Output Current I OUT Source current at 0.8 V DD5 480 Sink current at 0.2 V DD5 600 μa Output-High Voltage V OH DO pin, I OUT = 1 A 0.9 V DD5 V Output-Low Voltage V OL DO pin, I OUT = +1 A 0.1 V DD5 V Output Rise/Fall Times t R / t F DO pin, C LOAD = 15 pf 2 μs Notes: 1. Packet Error Rate (PER) < 1e-2 with one byte packet of A5 hex. 2. AM 99% with square-wave modulation 3. Depends on the ESR of crystal PRE January 2015

12 EVALUATION BOARD LAYOUT PCB area is 16 mm mm with HC-49US crystal <Top Side> <Bottom Side> PRE January 2015

13 PACKAGE INFORMATION 8 Pins, SOP, 150MIL Symbol Min. Nom. Max. A A A b c e 1.27 BSC. D E E L θ 0º - 8º Notes: 1. Refer to JEDEC MS-012 AA 2. Unit: mm PRE January 2015

14 IMPORTANT NOTICE Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and to discontinue any product without notice at any time. PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No circuit patent licenses are implied. Princeton Technology Corp. 2F, 233-1, Baociao Road, Sindian Dist., New Taipei City 23145, Taiwan Tel: Fax: PRE January 2015

DESCRIPTION FEATURES APPLICATIONS BLOCK DIAGRAM. PT MHz / MHz PLL Tuned Low Power FSK Receiver

DESCRIPTION FEATURES APPLICATIONS BLOCK DIAGRAM. PT MHz / MHz PLL Tuned Low Power FSK Receiver 315 MHz / 433.92 MHz PLL Tuned Low Power FSK Receiver DESCRIPTION The PT4305 is a PLL-tuned FSK receiver for short-range wireless data applications in the 315 MHz and 434 MHz frequency bands. The PT4305