Design of Padless MOUSE System with MEMS Accelerometers and Analog Read-Out Circuitry

Transcription

1 Design of Padless MOUSE System with MEMS Accelerometers and Analog Read-Out Circuitry Seungbae Lee, Gi-Joon Nam, Junseok Chae, and Hanseup Kim Department of EECS University of Michigan Ann Arbor, MI Abstract A hybrid two-dimensional position sensing system is designed for mouse applications. The system measures the acceleration of hand-movements which are modulated and converts them into two-dimensional location coordinates. To achieve this, the system consists of four major components: 1) MEMS accelerometers, 2) CMOS analog read-out circuitry, 3) an acceleration magnitude extraction module and 4) a 16-bit RISC microprocessor. An unique verification method is conducted on the designed system using a specialized instruction. Mechanical and analog simulation shows that designed padless mouse system can detect acceleration as small as 5.3 mg., and thus it is applicable to mouse system. I. INTRODUCTION Most of commercial MOUSE systems are built employing a ball or optical technique to provide cursor positions. For example, a ball mouse system detects physical rolling movements of the ball, which are affected by a non-flat or obstructed surface. An optical mouse system avoids these environmental factors by detecting the reflection of light instead of physical contacts on reflective supplementary pad. Both types of mouse require a special surface limiting the working space and freedom of user s movements. Obviously, a more desirable mouse system will be the one that is not restricted by any circumstantial factors. In this paper, we describe a novel mouse system design which detects two-dimensional positions without any contacts on additional components such as pads. The system consists of four major components: 1) MEMS (Micro Electro Mechanical Systems) accelerometers, 2) CMOS analog read-out circuitry, 3) an acceleration magnitude extraction module, and 4) a 16-bit RISC microprocessor. Figure 1 presents the block diagram of overall hybrid mouse system. Two MEMS accelerometer devices are employed to measure X and Y-axis acceleration of the movements from the user's hand. These acceleration values are pulse-width modulated by the CMOS analog read-out circuitry and will be converted into (X, Y) coordinates on the screen by performing integral operations on a 16-bit RISC microprocessor. In this design, we present a hybrid configuration system, which means each component is not based on the same substrate and thus has to be interfaced with each other by means of external connection such as wire bonding. MEMS device is designed in S.O.G. (licon On Glass) configuration, the MEMS Process (U of M) + Analog Circuit Process (U of M) + Digital Circuit Process (MOSIS) X-direction MEMS Accelerometer Read Out Analog Circuit Feedback magnitude extractor a x dt (X,Y) Y-direction MEMS Accelerometer Read Out Analog Circuit Feedback magnitude extractor a y dt screen Figure 1. Block diagram for the hybrid MOUSE system.

2 analog readout circuit is designed in a 2-poly 1-metal process, and the digital microprocessor is designed in a 1-poly 2-metal MOSIS process. More interestingly, the system can be handily extended into a three-dimensional position detection system by adding an additional MEMS accelerometer to measure Z-axis directional movement. The rest of this paper is organized as follows. Section II presents the overall system architecture and explains each module in detail. Section III describes the verification and testing methodology for our system. Section IV presents statistical data of the final design and Section V describes the future work relevant to monolithic implementation of all the components. Finally, concluding remarks are given in Section VI. II. SYSTEM OVERVIEW 2.1 System Requirements and Constraints Two system requirements stand out for consideration: speed and accuracy. Generally the speed of physical reaction from a human is remarkably slow compared to the speed of a modern microprocessor and it is reported that the magnitude of an action is at most order of 10-2 seconds [1]. nce the mouse system must be able to generate (X, Y) coordinate values faster than this rate, the target clock frequency was chosen to be 100 khz, which provides 500 instructions per coordinate calculation. In terms of movement accuracy, the finest acceleration from a human s hand is bigger than 10 mg. (g=9.8m/s 2 ). One of the most important figure of merit in MEMS accelerometer is the sensitivity which is defined as the capacitance variation per gravity change. The capacitance change due to acceleration input is detected and converted to voltage in analog read-out circuits. Accordingly, together with MEMS accelerometer s sensitivity, the gain and equivalent input noise of analog read-out circuits determine the overall minimum detectable acceleration. Taken this into account, the analog read-out circuits and MEMS accelerometer are designed to detect acceleration as small as 5 mg., implying that potentially our system can catch any smallest movement a human being can perceive. Consequently, our system specification proves that it is fast and precise enough to reflect a variety of movements from a user. As far as power concerned, small power can be estimated due to small operation frequency. However, power will become one of big issues when padless system is to be also wireless because of the large power transmitter needs. 2.2 Design Methodology As shown in Figure 2, comb structure was chosen for MEMS accelerometer design because it gives more sensitivity due to large sensing capacitance depending the number of comb fingers. The device dimensions were obtained by optimization with smaller size and larger sensitivity. After Figure 2. S.O.G MEMS accelerometer. optimization, its functionality was verified using ANSYS. For the analog read-out circuit design, switched capacitor circuits were chosen since they make it easier to interface between analog and digital parts. All the analog circuit designs were simulated on HSPICE environment and laid out using Mentor Graphics software. Considering the challenges and difficulties that can be encountered in VLSI design, a strict design methodology was established. First, the system was hierarchically specified in a top-down fashion so that a module at a higher level is decomposed into several sub-modules in the next lower level (top-down specification). After all the necessary modules were identified, each module was carefully designed from the bottom and linked together to form a super-module at a higher level (bottom-up design). Every module was fully tested for functionality followed by LVS (Layout vs. Schematic) and parasitic extraction for layout and timing verification. After all three verification procedures were satisfied modules were instantiated and used at a higher level of the design hierarchy. The majority of modules- the datapath of the microprocessor, analog circuitry and MEMS device - were fully custom designed while some modules of the microprocessor controller were designed using Verilog HDL. The layout was designed with the objectives of low power and easy modification in mind. Proper pitch matching was maintained for every cell in the datapath. In order to reduce cross-coupled parasitic capacitance, polysilicon and metal-2 paths were run vertically while metal-1 was used only for horizontal runs. These efforts benefited to produce a fully functional and fast system that occupies small area. 2.3 Operational Overview Figure 1 shows an operational block diagram of the mouse system. When a user moves the mouse in an arbitrary direction, the acceleration is decomposed into X- and Y-axis acceleration component and each of them is measured by a corresponding MEMS accelerometer". The actual acceler-

3 ation value is represented by differential capacitance between two capacitors in the MEMS device. This capacitance value is used in two different ways. First it is fed back to the MEMS device to reset it so that we can measure the next acceleration without any bias. Second, the capacitance value is fed into CMOS analog read-out circuitry that modulates it into digital pulse-width modulated output voltage. The polarity of the pulse (either positive or negative) determines the direction of the acceleration and the width of the pulse is proportional to the magnitude of the input acceleration. An "acceleration magnitude extractor" changes the generated pulse width into the units of system clock frequency, which will be used by a microprocessor to calculate the exact position coordinate values on the screen. The MEMS accelerometer was designed and fabricated in university of Michigan with MEMS technology. The analog CMOS circuitry was also designed and fabricated in university of Michigan with single metal/double poly process. Digital circuits for microprocessor was designed by MOSOS process with double metal and one poly. In the next section, each module is explained in details. 2.4 MEMS Accelerometer Considering a sensing method, there are three different types of MEMS accelerometer. The first type is a piezoelectric device which uses a piezoelectric material to sense an acceleration [2]. The second type is a tunneling device which utilizes tunneling as a sensing method [3]. The last one is a capacitive accelerometer which measures capacitor changes to detect acceleration [4, 5]. For our mouse system, we have used a capacitive accelerometer since it provides high sensitivity, good DC response, low drift, low temperature sensitivity, low-power dissipation, and a simple structure [6]. A schematic top view of MEMS accelerometer is shown in Figure 5. The device utilizes conventional comb drive structure, and it generates two capacitance signal C left and C right which are transferred to the analog readout circuitry. There are several MEMS accelerometers with comb drive configuration. In this design, S.O.G. (licon On Glass) configuration is chosen in order to take advantage of robustness and the simplicity of design. Figure 2 shows the structure of a S.O.G. lateral accelerometer [4]. A MEMS accelerometer consists of two major components: a proof mass and sensing electrodes. A proof mass is connected to a frame which is anchored to a glass substrate with suspension beams. nce the proofmass is suspended over recess on a glass substrate with serpentine suspesion beams, it is free to move with a response to external acceleration. On the other hand, electrodes are attached to the glass substrate to be stationary. When external forces are applied to the accelerometer (by the user s hand movement, for example), the proof mass moves against the forced Figure 3. Fabrication process sequence direction due to an inertia force while the electrodes are stationary. The movements cause capacitance variations between the comb fingers which form parallel plate capacitors, denoted as C. One side of the comb fingers generates a positive variation ( + C 2 ), and the other side produces a negative one ( C 2 ) simultaneously. The total capacitance change is the difference between these two values [( C 2) ( C 2) ]. Therefore, the external acceleration is converted to the differential capacitance variation which can be expressed as: C ( pf g) 9.8 M = C k d s 0 (eq. 1) where M is the mass of a proof mass, C s is the rest capacitance, d 0 do is the sensing gap distance, and k is the spring constant of suspension beams [5]. From (eq. 1), it can be expected that heavy accelerometer with large number of comb fingers and flexible(i.e., small spring constant) structure generates good sensitivity, although it is difficult to fabricate such accelerometers. With device dimensions of 2.1 mm width, 2.4mm length and 100 µm height polysilicon proof mass, it gives 0.78 pf/g sensitivity. For the twodimensional mouse system, two lateral accelerometers are required for sensing X and Y-axis accelerations. The fabrication process is a 5 step process requiring only 3 masks. Figure 3 shows the cross section of the wafer for each fabrication step. In the first step, a recess is formed on the glass substrate (a). Then, the glass wafer with recess is anodically bonded to a silicon wafer (b). Next, the silicon wafer is thinned to desired thickness with CMP (Chemical Mechanical Polishing) (c). Finally, metal contacts are evaporated (d) and followed by Deep RIE etch (e). Figure 4 shows SEM (Scanning Electron Microscope) picture of a MEMS accelerometer taken after fabrication.

4 anchors proofmass sensing electrodes Figure 4. Top view of a MEMS accelerometer. 2.5 CMOS Analog Read-Out Circuits suspension beams fingers The detected acceleration, which represents a differential capacitance variation from the MEMS accelerometer, is modulated to pulse-width by the analog read-out circuitry shown in Figure 5. In general, the lateral accelerometer presented in Section 2.4 can be operated either in open-loop mode or closed-loop mode. In closed-loop operational mode, the overall performance such as linearity, dynamic range, and bandwidth are improved [5]. In our design, an electromechanical oversampled modulator is used because it provides direct digital output and force feedback control of the proof mass simultaneously over a wide dynamic range. Among various classes of electromechanical modulators, a switched capacitor front-end type, shown in Figure 5 (a), is chosen because it is insensitive to the input parasitic capacitance. An efficient gain and offset compensated integrator is obtained by using an offset-storage C O, so called correlated double sampling (CDS) technique[7]. This circuit uses a single-ended charge integrator to read out the capacitance variation, and the static comparator forms the loop quantizer. Finally, a digital flip-flop samples the output from the comparator and synchronizes its bit stream with the system clock. nce the proof mass can be modeled as a second order system, closed loop system becomes unstable. To prevent this instability, simple lead compensator, H c (z), is inserted in the feedback path. There are basically three clock phases in the switched-capacitor interface circuit. During the first phase (φ 1 ), the sense capacitors formed between electrodes and proofmass, are reset and the OP-amp offset voltage is stored on C O. In the second phase (φ 2 ), sense capacitors, C right and C left, are charged through V+ and V-. The charge difference between C right and C left is integrated on the feedback capacitor, C i, while the comparator quantizes the charge. In this phase, the offset voltage stored in C O is substracted and thus the output voltage of OP-amp is compensated for the non-ideal OP-amp offset voltage. The amplitude of OP-output voltage corresponds to the magnitude of applied acceleration. For example, if the MEMS device gets positive acceleration, then the proofmass is closer to the left anchor of MEMS accelerometer and C left is bigger than C right. nce C left is connected to the negative reference voltage (V-), the negative net charge is sampled to an integrator, generating positive OP-amp output voltage. The capacitance sensitivity defined as the OP-amp output voltage due to input capacitance change ( C )is calculated by: V O C = ( V+ V - ) C i (eq. 2) From this (eq. 2), the capacitance sensitivity is approxi- Integrator V+ V- φ 4 φ 1 C right C left φ 4 φ 1 φ 1 φ 2 C φ o 1 φ 4 φ 1 Comparator C i Bit Stream d q FF clk φ 1 φ 2 φ 3 Reset Sense Feedback Compensation 2-z -1 MEMS Accelerometer φ 3 Compensator φ 2 H c (z) = 2-z -1 Flip-Flop (a) gma-delta electro mechanical modulator circuit schematics φ 4 10 µsec (b) clock phases Figure 5. gma Delta Electro Mechanical Modulator with clock phases

5 Switches Op-Amp Buffer Integrator Output Capacitor Comparator D-flipflop PWM gnal Clock Generator Figure 6. HSPICE simulation for analog read-out circuit. mately 0.33 V/pF. The quantized output is also latched at the end of this phase. In the last phase (φ 3 ), the output of the flipflop is fed back to the MEMS accelerometer to place the proof mass in the nulling position by electrostatic forces. If the proofmass gets positive accelerations, then the output of comparator will be positive because of its voltage inversion. This supply voltage is applied to proof mass to make the proofmass get back to the nulling position by electrostatic forces. The additional phase (φ 4 ) is used for the control and sensing of the proofmass. The output of the latch forms pulse bit streams for the next module. Figure 6 shows the HSPICE simulation result of modulation of acceleration magnitudes into the corresponding digital pulse bit streams (PWM signal). As the acceleration changes, capacitance differences between proof mass and electrodes are sensed and the corresponding charge is integrated with a 90-degree phase lag. The integrated charges are reflected to the voltage at the output and passed through the comparator generating a PWM signal. The layout for analog read-out circuit shown in Figure 7 is composed of all the components such as switches, amplifier, comparator, D- flip flop and clock generator. 2.6 Noise Analysis of Closed Loop System There are several noise sources that come from switched capacitor circuit as well as MEMS accelerometer and affect the performance of overall system. In other words, these noise sources determine the minimum detectable input acceleration (or resolution). In an oversampled electromechanical sigma-delta system, higher sampling rates reduces the quantization noise, and also result in 3 db signal-tonoise ratio improvement for each doubling of the sampling frequency. From the sensitivity of accelerometer and capacitance sensitivity, the equivalent input noise in terms of acceleration can be calculated. Followings describe each noise source. Brownian noise: Figure 7. Layout for gma-delta analog readout circuitry. (die size: 4.5mm x 2.6mm) The primary mechanical noise source for the device is due to the Brownian motion of gas molecules between comb fingers. The total noise equivalent acceleration (TNEA) [ m ( s 2 Hz) ] [6] is TNEA 4K B TD = = M 4K B Tw r QM (eq. 3) where K B is the Boltzmann constant and T is the temperature in kelvin. From (eq. 3), it is seen that MEMS accelerometer has smaller Brownian noise with larger-q and heavier proof mass. Plugging in device data into this equation, we can calculate the Brownian motion noise around 10 µg Hz Amplifier noise: The readout circuitry utilizes correlated double sampling to reduce the input CMOS amplifier flicker noise. However, the amplifier thermal noise is amplified by the ratio of total input capacitors including parasitics to the integrating capacitor. The noise at the output of amplifier can be expressed by integrating the total noise power and divide it by effective noise bandwidth, which is half of sampling frequency. Therefore, the amplifier output noise voltage due to thermal noise in OP-amp is expressed as: V Amp C T 16 kt 1 out = [ V Hz ] (eq. 4) 3 C i C out where C T is the total input capacitance including parasitics, C out is the capacitance of OP-amp output node, f s is the sampling frequency. From this equation, the equivalent input acceleration noise due to amplifier thermal noise is about 0.7 µg Hz. f s

6 KT/C noise: A major noise source in switched capacitor circuits is KT/ C noise which is generated by the CMOS switch thermal noise. The rms voltage noise from thermal switch noise can be calculated by the integration of the bandwidth of switch s RC filter. This rms value is KT/C as the noise name suggests. The voltage noise power density due to this switch thermal noise is expressed as: V SC kt 2 out = [ V Hz ] (eq. 5) C i f s This KT/C voltage noise is converted to the equivalent input acceleration noise as 0.3 µg Hz. Mass residual motion noise: The proof mass is being rebalanced by a pulse train and thus it has a residual motion with small ac amplitude. The amplitude of this motion can be shown [8] to be approximately equal to x = 4 a max /(πf s ) 2 = 8.0x10-9 [m] with a max =20g and f s =100kHz. This residual motion corresponds to equivalent rms 78 mg acceleration in this MEMS accelerometer. This acceleration can be randomized due to the varying input and hence it can be considered to be noise distributed uniformly from dc to the proof mass residual motion frequency, f s /4. This noise is then equivalent to 500 µg Hz. Dead Zone Noise: Assuming that the input of the accelerometer is zero, the feedback voltage generates a max with frequency f s /4 because of electrostatic force. Therefore, input signal must be large enough to break this dead-zone pattern. The minimum rms input acceleration for this is a dead-zone = 8a max (f r /f s ) 2 = 160 µg, and should be countered as noise. Total noise and Minimum detectable acceleration: nce all of the noise sources considered here are uncorrelated, the total noise is obtained simply by summing all the noise sources as 530 µg Hz. Therefore, the minimum detectable acceleration is same as the one calculated by integrating this input acceleration density over bandwidth of interests, ~100 Hz. The resultant minimum detectable acceleration is 5.3 mg, which is below the range of smallest acceleration a human can generate/perceive. From the noise source consideration, we can see that the mass residual noise dominates with order of magnitude. however, this mass residual motion noise can be significantly reduced by just increasing sampling frequency at the cost of power consumption and complexity. 2.7 Magnitude Extractor The modulated pulse bit stream from the CMOS analog Y axis t 1 t 2 t 0 t 3 X axis of X t0 t1 t2 Time read-out circuit is converted into binary data for further processing. Two types of data should be extracted from the pulse bit streams: 1) the polarity and 2) the magnitude. The polarity information indicates the direction of acceleration, and can be handily extracted by observing the sign of pulse bit streams. For example, Figure 8 illustrates the movements of the mouse and corresponding acceleration values on both X- and Y-axis. It also shows the possible PWM (Pulse Width Modulation) bit streams. If the value of the pulse is 5 volts (digital value "1"), the acceleration is toward the positive direction, and vice versa. The width of bit pulse streams is proportional to the magnitude of acceleration. The extraction of correct magnitude of acceleration can be achieved via two binary flags (flip-flops) and a binary counter as shown in Figure 9. The "c" flag is set to the polarity of current input pulse bit stream synchronized by the system clock while "p" flag value is the one shifted from "c" flag flip-flop in the previous clock cycle. The comparator compares the two flag values and whenever two flag values differ-- e.g., the polarity of input stream changes--, it loads the current value of binary counter into the buffer register called " Register" and at the same time, it resets the counter. While "c" and "p" flag flip-flops have the same value, the counter keeps increasing or decreasing based on the value of "c" flag 0 of Y 0 t0 t1 t2 t3 t3 PWM Pulse PWM Pulse Time Figure 8. Movements of a mouse and corresponding accelerations in X- and Y-axis. Load Modulated Bit Stream C flag Comparator P flag Up-Down Counter Register N flag Reset To µprocessor Figure 9. Magnitude Extractor.

7 flip-flop. Thus, the magnitude of generated values is proportional to the degree of the acceleration of movements, and the polarity of the input bit steams determines the direction of user s movements. In other words, the positive value of the counter corresponds to the positive acceleration while the negative value indicates the reverse acceleration. The "acceleration register" always keeps some static values specifying the previous acceleration magnitude and the control microprocessor only accesses this register to calculate the current position of cursor. Whenever the acceleration register loads a new value from the counter, the "n" flag flipflop is set to "1" indicating that the new value has been loaded. The control microprocessor keeps polling "n" flag flip-flop to decide whether it should fetch a new acceleration value or not. The layout for acceleration magnitude extractor is assembled together with core microprocessor shown in Figure Core Control Microprocessor The core control microprocessor is designed to filter the acceleration output from analog read-out circuits within the bandwidth of interests to remove the quantization noise folded at higher frequency and other noises. This can be done with simple FIR low pass filter with ~100 Hz cut-off frequency. Also, microprocessor calculates the position coordinates based upon the magnitude values of the acceleration from the acceleration extract module. The processor is based on RISC concepts and is implemented as a two-stage pipeline (Figure 10). It uses a 16-bit word and address space Instruction Memory PC FETCH Instruction Reg. Displacement Addr. A Addr. B/WR Immediate Decode Registers (a x,a y ) Register File EXECUTE Data Memory Figure 10. Core microprocessor architecture. PC Screen and all instructions are single word. In addition to the basic instructions such as arithmetic and logical operations, two application specific instructions are implemented which will be described below. The main part of the application program consists of two procedures: 1) polling and 2) integration. For the polling procedure, a special instruction is defined called LCNT (Load Counter Value). When LCNT is executed, the core control microprocessor examines the value of the "n" flag ALU Shifter flip-flop in the previous acceleration extract module. If the value of the flip-flop is "1", the value of the acceleration register is transferred into one of registers in the datapath module, which will be integrated for coordinate calculation. At the same time, the "n" flag flip-flop is reset to "0" by the microprocessor to indicate the completion of a transferring operation. The transferred acceleration magnitude value should be integrated twice so that it is transformed into position coordinates as shown in the following equation: t 2 t 1 t 2 t 1 v = ( a) dt, p = ( v) dt = ( a) dt (eq. 6) where vap,, represent velocity, acceleration and position coordinate respectively. In stead of implementing the integration operation, it is performed via two normal addition instructions: v = v+ a and p = p + v. nce the system has abundant instruction cycles per coordinate calculation as pointed out in Section 2.1, this system design decision is justified. The other implemented application-specific instruction is called SROUT. SROUT is the instruction which ships out calculated coordinate values to 16-bit system interface bus. To minimizes the interface with outside circuitry, instruction memory (ROM) as well as data memory (RAM) have been integrated into the core microprocessor module, which helped a lot to reduce the number of pins. Both ROM and RAM are the sizes of 256 words. Thanks to the simplicity of application program, 256 words were big enough to contain the entire application program. 2.9 Timing Scheme and Critical Paths The general timing strategy of the core microprocessor is based on two stage-pipelined operations. The clocking in this micro controller is predominantly positive edge-triggered except the program counter. The program counter is a negative edge-triggered component to allow enough instruction memory access time between t 1 and t 2 as illustrated in Figure 11. At time t 2, an instruction is loaded into the t 1 t 2 t 3 t 4 Instruction Memory Access Decoding Execution PC Incremented Instruction Fetch Control gnal Stabilized Register File Write Back instruction register, and between t 2 and t 3, the newly fetched instruction is decoded. In our design, every control signal is latched (as shown at time t 3 ) to provide stabilized control t 2 t 1 Figure 11. Timing strategy.

8 signals for safe execution of the instruction during the next clock cycle from t 3 to t 4. In other words, the entire clock period is dedicated to execute one instruction. Finally at time t 4, the result of the execution is written back to either the register file or the data memory. The rationale behind this timing strategy is to distribute major timing loads to different clock cycles evenly resulting in the reduced clock period. Our microprocessor design does not have separate MAR (Memory Address Register) and MDR (Memory Data Register) because both of instruction memory (ROM) and data memory (RAM) are integrated together with the processor. Thus, the executions of memory access instructions (Load/ Store) are very similar to those of register transfer instructions (Mov/Movi), which simplifies the system architecture. Through extensive simulation, the paths from the register file to ALU were determined to be critical because the register file is the largest component and the ALU has a ripplecarry adder in it (Figure 12). The ALU delay time is Figure 12. Timing delay for the critical path. ns which is measured from the rising clock edge to the point when the calculated data is valid on the system data bus. This critical path permits a maximum clock frequency of approximately 18 MHz, which is well above the target frequency of 100 khz. Recalling that the application target frequency dictates the maximum critical delay, the ripple-carry adder showed adequate performance in this regard and a faster ALU was not necessary. III. VERIFICATION AND TESTING 3.1 Verification and Testing Methodology Verification and simulation were performed using the Mentor Graphics Tools. Mentor Quicksim Pro and gnalscan were used for functional verification of initial transistor level and Verilog modules respectively. Parasitics were extracted from the layout, and Accusim used for the detailed delay and loading effects. Timing information from the parts generated in Epoch [14] was extracted automatically during the import process to Design Architect. Once the functional models were properly back annotated, timing verification was performed in Quicksim Pro. In order to verify the physical design, full mask LVS was performed by importing the custom datapath into Epoch and generating a netlist for the entire core that included the custom and Epoch-synthesized parts. 3.2 Design for Testability Two primary features were added to assure the testability of the system. The first design-for-testability feature is scannable registers. The program counter and the instruction register are the most critical sections of the core since they determine the instructions that are executed internally. Therefore, a scan-chain testing design has been implemented for these registers. Once scan mode is set by asserting high at the testing mode input pin, input data for both of registers are loaded, specified operations are performed, and the outputs of operations can be scanned out serially. The second feature is the special testing instruction SROUT (which is the same one with the application specific instruction described in Section 2.8). This instruction ships out the specified register value to 16 bit output pins (SOUT[15:0]) allowing us to observe any arbitrary register values of the register file during the testing mode. Thanks to these two design-for-testability features, the contents of both of instruction and data memory were verified efficiently. By applying instruction addresses at the program counter and observing the values of instruction register via scan-chain testing mode, the correctness of the instruction memory (ROM) were verified. For the data memory (RAM), we verified them by moving contents of a specific memory location into one of the register in the register file and transferring them to the system interface bus via SROUT instruction. Indeed, all the important digital modules were able to be verified with the help of the special instruction SROUT and the scan-chain design. IV. FINAL DESIGN STATISTICS MEMS accelerometer was designed to have characteristics such as sensitivity with 0.78 pf/g, dimensions as 2.1mm

9 x 2.4mm x 100 µm (= width x length x height), and sensing capacitance of 16.4 pf. The analog circuit has estimated power of 3 mw, capacitance sensitivity as 0.3 V/pF, and die size of 4.5mm x 2.6mm. Mechanical and analog simulation shows that the designed padless mouse system can detect acceleration as small as 5.3 mg, which is a high enough resolution for mouse applications. The core control microprocessor shown in Figure 13 contains two distinct components; the custom datapath and the control module generated in Epoch as described previously. The important design statistics for microprocessor are as follows. The total transistor number is 53634, and the die size is 5573 by 5761 µm. Although maximum achievable clock speed is 18.1 MHz, its operation frequency is same as sampling frequency of analog switched capacitor sigma-delta read-out circuits. The power consumption is estimated as 10 µw at 100 khz operation frequency. V. MONOLITHIC IMPLEMENTATION The hybrid two dimensional position detection system has been proposed to combine MEMS accelerometers and digital circuits by means of switched capacitor circuits using wire bonding. Due to the wire being bonded, however, these different modules in a system must interface with each other at board level. This not only limits the size of a system, a mouse in this paper, but also contributes capacitive or resistive parasitics that may degradate the system performance [15]. To circumvent these drawbacks of hybrid system, a system-on-chip (SOC) design and fabrication, where all the modules are fabricated in single wafer, are considered as a ROM Y ACC X ACC CONTROL RAM DATA PATH Figure 13. Microprocessor layout. (5.6mm x 5.8mm) monolithic implementation. In other words, all the necessary modules such as MEMS accelerometers, the analog read-out circuit and the microprocessor are to be integrated on the same wafer without any interfaces between them. The only major interface with outside circuits-other than VDD, GND, clock and reset signals- is the parallel data bus which transfers positional coordinates calculated from the microprocessor. nce they are fabricated on the same wafer eliminating complex steps for the interface, the overall costs are greatly reduced. With all these advantages over hybrid system, however, monolithic system has several problems such as noise between analog and digital circuits, interconnections between MEMS devices and analog circuits, and so on. One of the main factor for a noise problem in monolithic system stems from the fact that the analog and digital circuits are sharing the same substrate. Although substrate has high resistance, it is not a complete isolator and thus voltage variations in digital parts are capacitively coupled to analog circuits and thus may cause malfunctions of a system. This noise problem due to the substrate coupling can be solved by using licon-on-insulator (SOI) which isolates one module from the other by etching the substrate boundaries of each module and making it isolated both physically and electrically. And more, MEMS accelerometers and analog circuitry can be connected to each other by making deep trenches. It is reported that the silicon substrate underneath interconnection materials such as metals can be removed in the process of deep trench etching because of a sidewall etching effect [16]. The detailed fabrication process flow for monolithic implementation combining MEMS devices, analog and digital circuits are basically post CMOS fabrication, presented in Figure 14. The usual CMOS processes are done using SOI start-wafer as shown in Figure 14(a) and (b). After CMOS processes, deep trenches are made for the formation of proofmass of MEMS accelerometer as well as isolation between analog and digital circuitry as given in Figure 14(c). Figure 14(d) presents the release step by removing O 2 with BHF to suspend the proofmass. During release, the O 2 between analog/digital circuitry are also etched away. Figure 15 shows the mask level MEMS structure. Close-up view shows a interconnection line, contacts, suspension beams, and etch holes which help releasing proofmass during BHF etch process. VI. CONCLUSION In this paper, we presented a novel two-dimensional position detection system for padless mouse applications that do not require any contacts for proper mouse operation. The design requirements were carefully examined and the systematic design methodology was established. The final system consists of four major components: 1) MEMS

10 O 2 (a) SOI wafer interconnection device. Also, we wanted to point out that the system could simply be extended to three-dimensional position detection system by additionally integrating a MEMS accelerometer device along another direction. Finally, we discussed a SOI implementation possibility of the mouse system design for future work. Analog Circuitry O 2 (b) Analog/Digital CMOS process Anchors Proofmass + Elctrodes Figure 14. Process flow of monolithic implementation. accelerometer, 2) Analog read-out circuit, 3) magnitude extraction module and 4) 16-bit RISC microprocessor. Each module was carefully designed, laid out, and verified through extensive simulation. The calculated and simulated minimum detectable acceleration is 0.3 mg, which is applicable to mouse system. We were able to address diverse interesting issues concerning VLSI design methodology such as SoC (System-on-Chip) design and DFT (Design-for-Testability). It was emphasized that the presented system needs no additional components other than the implemented chip itself unlike the conventional mouse Trenches O 2 (c) Deep trench etching Accelerometer O 2 (d) Release Interconnection Contact Etch hole Digital Circuitry Suspension beams Sensing gap Figure 15. MEMS accelerometer for monolithic implementation. REFERENCES [1] HUMAN.PP.HTM [2] L. M. Roylance and J. A. Angell, "A batch-fabricated silicon accelerometer," IEEE Trans. Electron Devices, vol. ED-26, pp , Dec [3] C. Yeh and K. Najafi, "A low-voltage bulk-silicon tunneling based microaccelerometer," Tech. Dig. IEEE Int. Electron Devices Meeting (IEDM), Washington, DC. Dec pp [4] J. S. Chae, H. Kulah, K. Najafi, "A High Sensitivity licon- On-Glass Lateral µg Microaccelerometer.", Nanospace 2000, Houston, TX. [5] N. Yazdi, K. Najafi, " An All-licon ngle-wafer Fabrication Technology for Precision Micro Accelerometers", Proc. Transducers 97, pp [6] N. Yazdi, F. Ayazi, and K. Najafi, "Micromachined inertial sensors", Proceedings of the IEEE, Vol 86, pp , Aug [7] Christian C. Enz and Gabor C. Temes, "Circuit Techniques for Reducing the Effects of Op-Amp Imperfections: Autozeroing, Correlated Double Sampling, and Chopper Stabilization", Proceedings of the IEEE, vol. 84, No.11, Nov [8] B. Boser and R.T. Howe, "Surface Micromachined Accelerometers", IEEE, J. Solid-State Circuits, vol.31, no.3, pp , March [9] Ying-Che Tseng, "AC floating body effects and the resultant analog circuit issues in submicron floating body and bodygrounded SOI MOSFET's" in IEEE Electron Device Letters, vol. 46, pp , August1999. [10] Srinath Krishnan, Jerry G. Fossum, "Grasping SOI Floating- Body Effects," IEEE Circuits and Devices Magazine, July 1998, pp [11] Ghavam G. Shahidi, et al., "Partially-Depleted SOI Technology for Digital Logic," Proceedings of ISSCC, San Francisco, Feb , 1999, pp [12] Ching-Te Chuang, Pong-Fei Lu, and Carl J. Anderson, "SOI for Digital CMOS VLSI: Design considerations and Advances," Proceedings of the IEEE, Vol.86, No. 4, April 1998, pp [13] K. K. Das and R. B. Brown, "Evaluation of Circuit Approaches in Partially-Depleted SOI-CMOS, SOI Conference, Oct. 2-5, 2000, Wakerfield, MA. [14] Epoch, Epoch: Online Manuals, Cascade Design Automation Corporation, Online, [15] Weste, N.H.E. and K. Eshraghian, Principles of CMOS VLSI Design: A System Perspective, 2nd ed., Addison-Wesley Publishing Company, Massachusetts, [16] H. Xie, et al., Post-CMOS Processing for High-Aspect-Ratio Integrated licon Microstructures, Proc. Solid-State Sensor and Actuator Workshop 2000, Hilton Head, pp