NCP308. Low Quiescent Current, Programmable Delay Time, Supervisory Circuit

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Low Quiescent Current, Programmable Delay Time, Supervisory Circuit The NCP308 series is one of the ON Semiconductor Supervisory circuit IC families. It is optimized to monitor system voltages from 0.

1 Low Quiescent Current, Programmable Delay Time, Supervisory Circuit The NCP308 series is one of the ON Semiconductor Supervisory circuit IC families. It is optimized to monitor system voltages from V to 5.5 V, asserting an active low open drain output, together with Manual Reset () Input. The part comes with both fixed and externally adjustable versions. Features Wide Supply Voltage Range.6 to 5.5 V Very Low Quiescent Current.6 A Fixed Threshold Voltage Versions for Standard Voltage Rails Including 0.9 V,.2 V,.25 V,.5 V,.8 V,.9 V, 2.5 V, 2.8 V, 3.0 V, 3.3 V, 5.0 V Adjustable Version with Low Threshold Voltage V (min) High Threshold Voltage Accuracy: 0.3% typ Support Manual Reset Input ( ) Open Drain Output (Push pull Output upon Request) Flexible Delay Time Programmability:.25 ms to 0 s Temperature Range: 40 C to +25 C Small TSOP 6 and WDFN6 2 x 2 mm, Pb Free packages These are Pb Free Devices Typical Applications DSP or Microcontroller Applications Notebook/Desktop Computers PDAs/Hand Held Products Portable/Battery Powered Products FPGA/ASIC Applications TSOP 6 CASE 38G WDFN6 CASE 5BR ORDERING INFORMATION MARKING DIAGRAMS XXXAYW See detailed ordering and shipping information in the ordering information section on page 9 of this data sheet. XXX, XX= Specific Device Code A =Assembly Location Y = Year W = Work Week M = Date Code = Pb Free Package XX M (Note: Microdot may be in either location) VIN VIN NCP308XXADJ R DSP/ Processor DSP/ Processor nf (Optional) R2 (Optional) (Optional) Figure. Typical Application Circuit for Adjustable Versions Figure 2. Typical Application Circuit for Fixed Versions Semiconductor Components Industries, LLC, 202 November, 202 Rev. 2 Publication Order Number: NCP308/D

2 NCP308SNADJ/NCP308MTADJ Adjustable Versions NCP308SNXXX/NCP308MTXXX Fixed Versions 90k 90k + Control Logic and Timer R + Control Logic and Timer Vref R2 Vref Figure 3. Functional Block Diagrams of Adjustable and Fixed Versions Figure 4. Pin Connections Diagram (Top View) Table. PIN OUT DESCRIPTION Name TSOP 6 Pin Number WDFN6 Description 6 Supply Voltage. A 0.uF ceramic capacitor placed close to this pin is helpful for transient and parasitic. 5 2 Sense Input, this is the voltage to be monitored. If the voltage at this terminal drops below the threshold voltage V IT, then is asserted. does not necessary monitor, it can monitor any voltage lower than. 4 3 Reset Delay Time Setting Pin. Connecting this pin to through a 40 k to 200 k resistor or leaving it open results in fixed reset delay times. Connecting this pin to a ground referenced capacitor ( 00 pf) gives a user programmable reset delay time. See the Setting Reset Delay Time section for more information. 3 4 Manual Reset input, low asserts. is internally tied to by a 90 k pull up Resistor. 6 Output, is an Active low open drain N Channel MOSFET output, it is driven to a low impedance state when is asserted (either the input is lower than the threshold voltage (V IT ) or the pin is set to a logic low). will keep low (asserted) for the reset delay time after both is above V IT and is set to a logic high. A pull up resistor from 0k to M should be used on this pin. See Figure 5 for behavior of depends on, and conditions. 2 5 Ground terminal. Should be connected to PCB ground reference EXP PAD Exposed Pad Exposed pad, under WDFN6 package, connect it to ground plane for better thermal dissipation. 2

3 Uncertain State V DD V DD(min) 0.0 V td tp2 td V IT + V HYS V IT tp td 0.7 V DD 0.3 V DD Figure 5. Timing Diagram Showing and Reset Timing Table 2. TRUTH TABLE > V IT L N L L Y L H N L H Y H 3

4 Table 3. MAXIMUM RATINGS Rating Symbol Value Unit Input voltage range, V DD V DD 0.3 to V voltage range V,, Current through pin I 0.3 to V DD pin voltage 0.3 to V pin current 5 ma Thermal Resistance Junction to Air TSOP 6 WDFN6 R JA Human Body Model (HBM) ESD Rating are (Note ) ESD HBM 2000 V Charged Device Model (CDM) ESD Rating are (Note ) ESD CDM 500 V Latch up Current: (Note 2) All pins, except digital pins Digital pins () I LU ±00 ±0 Storage Temperature Range T STG 65 to + 50 C Maximum Junction Temperature T J 40 to +50 C Moisture Sensitivity (Note 3) MSL Level Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.. This device series contains ESD protection and passes the following tests: Human Body Model (HBM) +/ 2.0 kv per JEDEC standard: JESD22 A4 Charged Device Model (CDM) 500 V per JEDEC standard: JESD22 C0. 2. Latch up Current per JEDEC standard: JESD78 class II. 3. Moisture Sensitivity Level (MSL): per IPC/JEDEC standard: J STD 020A. V ma C/W ma 4

5 Table 4. ELERICAL CHARAERISTICS.6 V V DD 5.5 V, R pullup = 00 k, C L = 50 pf, over operating temperature range (T J = 40 C to +25 C), unless otherwise specified. Typical values are at T J = +25 C. Symbol Parameter Conditions Min Typ Max Unit V DD Supply Voltage Range 40 C < T J < +25 C V V DD (min) Minimum V DD Guaranteed Output Valid (Note 4) V I DD Supply Current (Current into pin) V DD = 3.3V, not asserted,, open A V DD = 5.5V, not asserted,, open V OL Low level output voltage of.3v V DD <.6V, I OL = 0.4 ma 0.3 V V IT % V HYS Negative going threshold voltage accuracy.6v V DD 5.5V, I OL =.0 ma ± % T J = +25 C C < T J < +85 C.0 ± Hysteresis on.6v V DD 4.2V %V IT V IT 4.2V V DD 5.5V R Internal pull up resistance 90 k I Input current at pin NCP308XXADJ V = V IT 0 na Fixed versions V = 5.5 V 0 I OH leakage Current V = 5.5 V, not asserted 300 na C IN Input capacitance, any pin pin V IN = 0 V to V DD 5 pf Other pins V IN = 0 V to 5.5 V 5 V IL logic low input V DD V V IH logic high input 0.7 V DD V DD V tw Input pulse width to assert t D Reset delay time C T = Open C T = V DD C T = 00 pf C T = 80 nf V IH =.05 V IT, V IL = 0.95 V IT 20 s V IH = 0.7 V DD, V IL = 0.3 V DD 50 (Guaranteed by design and characterization) ms t P Propagation delay from to V IH = 0.7 V DD, V IL = 0.3 V DD 50 ns t P2 Propagation delay from to 4. The lowest supply voltage () at which becomes active. 5. NCP308XX: XX = MT (WDFN6 package) or SN (TSOP 6 package). V IH =.05 V IT, V IL = 0.95 V IT 20 s 5

6 TYPICAL OPERATING CHARAERISTICS I DD ( A) C +85 C (ms) C +25 C +85 C +25 C C 40 C V DD (V) Figure 6. Supply Current vs. Input Voltage (nf) Figure 7. Timeout Period vs. NORMALIZED TIMEOUT PERIOD (%) TEMPERATURE ( C) Figure 8. Normalized Timeout Period vs. Temperature TRANSIENT DURATION BELOW V IT ( s) OVERDRIVE (%V IT ) Figure 9. Maximum Transient Duration at Sense vs. Sense Threshold Overdrive Voltage NORMALIZED V IT (%) TEMPERATURE ( C) Figure 0. Normalized Sense Threshold Voltage (V IT ) vs. Temperature V OL LOW LEVEL VOLTAGE (V) V DD =.6 V V DD = 3.3 V V DD = 5.5 V CURRENT (ma) Figure. Low Level Voltage vs. Current 6

7 DETAILED DESCRIPTION The NCP308 microprocessor supervisory product family is designed to assert a signal when either the pin voltage drops below V IT or the Manual Reset input () is driven low. The output remains asserted for a programmable delay time after both and voltages return above the respective thresholds. A broad range of voltage threshold and reset delay time options are available, allowing NCP308 series to be used in a wide range of applications. Reset threshold voltages can be factory set from 0.82 V to 3.3 V or from 4.4 V to 5.0 V, while the NCP308XXADJ can be used for any voltage above V using an external resistor divider. Flexible delay time can be easily got with pin according to Table 5: Table 5. DELAY TIME SETTING TABLE pin Configuration = = Open Connecting a capacitor between pin and (Capacitor value > 00 pf) Delay Time (td) 300 ms (fixed) 20 ms (fixed).25 ms ~ 0 s, depends on capacitor value (Refer to the Setting Reset Delay Time Section) Output The output is typically connected to the control pin of a microprocessor. For Open Drain output versions, a pull up resistor must be used to hold this line high when is not asserted. The output is active once V DD is over V DD (min), this voltage is much lower than most microprocessors functional voltage range. remains high as long as is above its threshold (V IT ) and the Manual Reset input () is logic high. If either falls below V IT or is driven low, is asserted. Once is again logic high and is above (V IT + V HYS ), the pin goes to a high impedance state after delay time (td). The open drain structure of is capable to allow the reset signal for the microprocessor to have a voltage higher than V DD (up to 5.5 V). The pull up resistor should be no smaller than 0 k as a result of the finite impedance of the line. Input The input should be connected to the monitored voltage directly. If the voltage on this pin drops below V IT, then is asserted. The comparator has a built in hysteresis to prevent erratic reset operation. It is good practice to put a nf to 0 nf bypass capacitor on the input to reduce its sensitivity to transients and layout parasitic. The NCP308XXADJ can be used to monitor any voltage rail down to V by the circuit shown in Figure 2. The new V IT can be derived from resistor divider network of R and R2 by: V IT R R2 V IT (eq. ) nf (Optional) VIN R R2 NCP308XXADJ Figure 2. Using NCP308XXADJ to Monitor a User Defined Threshold Voltage (Optional) Manual Reset Input () The Manual Reset input () allows a processor or other logic circuits to initiate a reset. A logic low on causes to assert. After returns to a logic high and is above its reset threshold, is de asserted after the delay time set by pin. is internally tied to V DD by a 90 k resistor so this pin can be left unconnected if will not be used. Figure 3 shows how can be used to monitor multiple system voltages (e.g. I/O supply voltage of some DSP/processors should be setup before core voltage, and DSP/processor can only start after both I/O and core voltages setup). 7

8 .2 V 3.3 V Vcore VIO DSP/ Processor NCP308XX20 NCP308XX330 Figure 3. Using to Monitor Multiple System Voltages Setting Reset Delay Time The NCP308 has three options for setting the reset delay time as shown in Table 5. Figure 4 shows the configuration for a fixed 300 ms typical delay time by tying to V DD ; a resistor from 40 k to 200 k must be used. Figure 5 shows a fixed 20 ms delay time by leaving the pin unconnected. Figure 6 shows a user defined program time between.25 ms and 0 s by connecting a capacitor between pin and ground. 3.3V 3.3 V 50k Figure 5. Delay Time Fixed to 20 ms when is Open 3.3 V Figure 4. Delay Time Fixed to 300 ms when Connected to by Resistor Figure 6. Delay Time Set by Capacitor The capacitor should be 00 pf for NCP308 to recognize that the capacitor is present. The capacitor value for a given delay time can be calculated using the following equation: 8

9 (nf) td(s) (s) 75 (eq. 2) Parasitic capacitances of pin should be considered to avoid reset delay time deviation or error. Immunity to Sense Pin Voltage Transients NCP308 is relatively immune to short negative transients on pin. Sensitivity to transients is dependent on threshold overdrive, as shown in the Maximum Transient Duration at Sense vs. Sense Threshold Overdrive Voltage graph (Figure 9) in Typical Operating Characteristics section. ORDERING INFORMATION Device Status (Note 6) Threshold Voltage (V IT ) NCP308SNADJTG Active V Adjustable Version NCP308SN090TG Under Request 0.84 V 0.9 V 090 NCP308SN20TG Under Request.2 V.2 V 20 NCP308SN25TG Under Request.6 V.25 V 25 Nominal Monitored Voltage Marking Package Shipping ADJ NCP308SN50TG Under Request.40 V.5 V 50 NCP308SN80TG Under Request.67 V.8 V 80 NCP308SN90TG Under Request.77 V.9 V 90 NCP308SN250TG Under Request 2.33 V 2.5 V 250 NCP308SN280TG Active 2.6 V 2.8 V 280 NCP308SN300TG Active 2.79 V 3.0 V 300 NCP308SN330TG Active 3.07 V 3.3 V 330 NCP308SN500TG Active 4.65 V 5.0 V 500 NCP308MTADJTBG Active V Adjustable Version NCP308MT090TBG Under Request 0.84 V 0.9 V AC NCP308MT20TBG Active.2 V.2 V AD NCP308MT25TBG Under Request.6 V.25 V AE AA TSOP 6 (Pb Free) 3000 / Tape & Reel NCP308MT50TBG Under Request.40 V.5 V AF NCP308MT80TBG Active.67 V.8 V AG NCP308MT90TBG Under Request.77 V.9 V AH NCP308MT250TBG Under Request 2.33 V 2.5 V AJ NCP308MT280TBG Under Request 2.6 V 2.8 V AK NCP308MT300TBG Under Request 2.79 V 3.0 V AL NCP308MT330TBG Under Request 3.07 V 3.3 V AM NCP308MT500TBG Under Request 4.65 V 5.0 V AN WDFN6 (Pb Free) 3000 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD80/D. 6. The marketing status are defined as below: Active: Products in production and recommended for new designs; Under Request: Device has been announced but is not in production. Samples may or may not be available. 9

10 PACKAGE DIMENSIONS TSOP 6 CASE 38G 02 ISSUE U E D ÉÉÉ 2 3 NOTE 5 e 0.05 A b E A c L H M DETAIL Z DETAIL Z L2 GAUGE PLANE C SEATING PLANE NOTES:. DIMENSIONING AND TOLERANCING PER ASME Y4.5M, CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.5 PER SIDE. DIMENSIONS D AND E ARE DETERMINED AT DATUM H. 5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE. MILLIMETERS DIM MIN NOM MAX A A b c D E E e L L BSC M 0 0 RECOMMENDED SOLDERING FOOTPRINT* 6X X PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 0

11 PACKAGE DIMENSIONS WDFN6 2x2, 0.65P CASE 5BR ISSUE O PIN ONE REFERENCE 0.0 C 0.0 C 0.05 C D ÍÍÍ ÍÍÍ TOP VIEW DETAIL B A3 A B E A EXPOSED Cu L MOLD CMPD DETAIL B ALTERNATE CONSTRUIONS L DETAIL A ALTERNATE CONSTRUIONS L NOTES:. DIMENSIONING AND TOLERANCING PER ASME Y4.5M, CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.5 AND 0.25 mm FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS DIM MIN MAX A A A REF b D 2.00 BSC D E 2.00 BSC E e 0.65 BSC L L X 0.05 C NOTE 4 DETAIL A A SIDE VIEW D2 3 L C SEATING PLANE RECOMMENDED MOUNTING FOOTPRINT*.72 6X 0.45 E e 6 4 BOTTOM VIEW 6X b 0.0 M C 0.05 M C A B NOTE 3 PACKAGE OUTLINE 6X PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 563, Denver, Colorado 8027 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative NCP308/D

NCP308, NCV308. Low Quiescent Current, Programmable Delay Time, Supervisory Circuit

NCP308, NCV308. Low Quiescent Current, Programmable Delay Time, Supervisory Circuit Low Quiescent Current, Programmable Delay Time, Supervisory Circuit The NCP308 series is one of the ON Semiconductor Supervisory circuit IC families. It is optimized to monitor system voltages from 0.405