Erik P. DeBenedictis. Sandia National Laboratories. Ph. D., California Institute of Technology, Computer Science, September 1982.

Transcription

1 Erik P. DeBenedictis Sandia National Laboratories EDUCATION Ph. D., California Institute of Technology, Computer Science, September Thesis: "Techniques for Testing Integrated Circuits" M. S., Carnegie-Mellon University, Electrical Engineering, May Thesis: "Multilevel Simulator." B. S., California Institute of Technology, Electrical Engineering, June EMPLOYMENT HISTORY Sandia National Laboratories, September 2001 to present, Albuquerque, NM, Principal Member of Technical Staff NetAlive Corporation, December 1991 to July 2001, Redwood City, CA, Co-founder and CEO ncube Corporation, March 1990 to November 1991, Foster City, CA, Senior Scientist Ansoft Corporation, November 1988 to February 1990, Pittsburgh, PA, Project Manager AT&T Bell Laboratories, February 1983 to November 1988, Holmdel, NJ, Member of the Technical Staff Yale University, Computer Science Department, August 1987-July 1989, New Haven, CT, Research Affiliate PATENTS 9,720,851 Method and apparatus for managing access to a memory (assigned to Sandia) 2,226,560 (Canada) Method and apparatus for controlling connected computers without programming (assigned to NetAlive) 6,144,984 Method and apparatus for controlling connected computers without programming (assigned to NetAlive) 693,585 (Australia) Method and apparatus for controlling connected computers without programming (assigned to NetAlive) 5,625,823 Method and apparatus for controlling connected computers without programming (assigned to NetAlive) 4,845,744 Method of overlaying virtual tree networks onto a message passing parallel processing network (assigned to Lucent Technologies) 4,766,534 Parallel processing network and method (assigned to Lucent Technologies) 4,404,676 Partitioning method and apparatus using data-dependent boundary-marking code words (assigned to Pioneer Electronics, Japan) AWARD

2 1988 Gordon Bell Award, second place or honorable mention. Granted for performance speedup on a multiprocessor with a demonstration of generality (5-way collaboration). See the entry document, the presentation and "Soft News," IEEE Software, vol. 05, no. 3, pp , May/Jun, 1988 WORKSHOPS PRODUCED The First-Tenth Workshop on Fault-Tolerant Spaceborne Computing Employing New Technologies, usually the week after memorial day, Albuquerque NM. Frontiers of Extreme Computing, October 23-27, 2005, Santa Cruz, CA see overview document SAND P. Frontiers of Extreme Computing 2007/Zettaflops Workshop, October 21-25, 2005, Santa Cruz, CA The Path to Extreme Supercomputing, October 12, 2004, Santa Fe, NM Sandia Petaflops Workshop, June 18, 2002, Albuquerque, NM PUBLICATIONS Vetter, Jeffrey S., Erik P. DeBenedictis, and Thomas M. Conte. "Architectures for the Post-Moore Era." IEEE Micro 37.4 (2017): 6-8. DOI: /MM DeBenedictis, Erik P. "Computer Design Starts Over." Computer 50.8 (2017): DOI: /MC Castrillon-Mazo, Jeronimo, et al. "Wildly Heterogeneous Post-CMOS Technologies Meet Software (Dagstuhl Seminar 17061)." Dagstuhl Reports. Vol. 7. No. 2. Schloss Dagstuhl-Leibniz-Zentrum fuer Informatik, DOI: /DagRep Conte, Thomas M., et al. "Rebooting Computing: The Road Ahead." Computer 50.1 (2017): DOI: /MC Deng, Bobin, et al. "Computationally-redundant energy-efficient processing for y'all (CREEPY)." Rebooting Computing (ICRC), IEEE International Conference on. IEEE, DOI: /ICRC Agarwal, Sapan, et al. "Energy efficiency limits of logic and memory." Rebooting Computing (ICRC), IEEE International Conference on. IEEE, October 17-19, Conte, Thomas M., et al. "Rebooting Computing Developing." Mondo Digitale (2016) Hsu, Jeremy. "Three paths to exascale supercomputing." IEEE Spectrum 53.1 (2016): DOI: /MSPEC Note: This guy rewrote my article, with permission, but not necessarily with permission to switch the author Lu, Yung-Hsiang, et al. "Rebooting Computing and Low-Power Image Recognition Challenge." Computer- Aided Design (ICCAD), 2015 IEEE/ACM International Conference on. IEEE, November 2, Conte, Thomas M., Elie Track, and Erik DeBenedictis. "Rebooting Computing: New Strategies for Technology Scaling." Computer (2015): DeBenedictis, Erik P., et al. "Optimal adiabatic scaling and the processor-in-memory-and-storage architecture (OAS+ PIMS)." Nanoscale Architectures (NANOARCH), 2015 IEEE/ACM International Symposium on. IEEE, DOI: /NANOARCH DeBenedictis, Erik, and Hans Zima. "Millivolt switches will support better energy-reliability tradeoffs." Energy Efficient Electronic Systems (E3S), 2015 Fourth Berkeley Symposium on. IEEE, October 1-2, 2015.

3 Rothganger, Fred, et al. "Training neural hardware with noisy components." Neural Networks (IJCNN), 2015 International Joint Conference on. IEEE, DOI: /IJCNN Agarwal, Sapan, et al. "Energy Scaling Advantages of Resistive Memory Crossbar Based Computation and Its Application to Sparse Coding." Frontiers in Neuroscience 9 (2016): 484. DOI: /fnins Marinella, Matthew J., et al. "Development, Characterization, and Modeling of a TaOx ReRAM for a Neuromorphic Accelerator." ECS Transactions (2014): DOI: / ecst Lohn, Andrew J., et al. "Memristors as synapses in artificial neural networks: Biomimicry beyond weight change." Cybersecurity Systems for Human Cognition Augmentation. Springer International Publishing, DOI: / _9 Ottavi, Marco, et al. "Partially Reversible Pipelined QCA Circuits: Combining Low Power With High Throughput." IEEE Transactions on Nanotechnology 6.10 (2011): DOI: /TNANO Ottavi, Marco, et al. "High throughput and low power dissipation in QCA pipelines using Bennett clocking." Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures. IEEE Press, DOI: /NANOARCH S. Frost-Murphy, E. DeBenedictis, P. Kogge, "General floorplan for reversible quantum-dot cellular automata," in Proceedings of the 4th international Conference on Computing Frontiers (Ischia, Italy, May 07-09, 2007). CF '07. ACM, New York, NY, DOI= DeBenedictis, Erik P., David E. Keyes, and Peter M. Kogge. "Issues for the future of supercomputing: impact of Moore's law and architecture on application performance." Proceedings of the 2006 ACM/IEEE conference on Supercomputing. ACM, DOI: / E. DeBenedictis, "Reversible logic for supercomputing," in Proceedings of the 2nd Conference on Computing Frontiers (Ischia, Italy, May 04-06, 2005). CF '05. ACM, New York, NY, SAND C. DOI= Brightwell, Ron, et al. "Architectural specification for massively parallel computers: an experience and measurement-based approach." Concurrency and Computation: Practice and Experience (2005): DOI: /cpe.893 **DUPLICATE of ABOVE**R. Brightwell, W. Camp, B. Cole, E. DeBenedictis, R. Leland, J. Tomkins, A. Maccabe, "Architectural Specification for Massively Parallel Computers -- An Experience and Measurement- Based Approach" Research Articles. Concurr. Comput. : Pract. Exper. 17, 10 (Aug. 2005), DOI= E. DeBenedictis, "Will Moore's Law be Sufficient," in Proceedings of the 2004 ACM/IEEE Conference on Supercomputing (November 06-12, 2004). Conference on High Performance Networking and Computing. IEEE Computer Society, Washington, DC, 45. DOI= E. DeBenedictis, "Comment On User's Bill of Rights," COMMUNICATIONS OF THE ACM February 1999/Vol. 42, No. 2 Ghosh, S., Debenedictis, E., and Yu, M "YADDES: a novel algorithm for deadlock-free distributed discrete-event simulation." Int. J. Comput. Simul. 5, 1 (May. 1995), E. DeBenedictis, S. C. Johnson, " Extending Unix for scalable computing, " IEEE Computer, vol.26, no.11, pp.43-53, Nov 1993

4 E. DeBenedictis and S. Johnson, "I/O for Tflops Supercomputers," Proc. Sixth SlAM Conf. Parallel Processing Scientific Computing, SIAM, Philadelphia, 1993, pp E. DeBenedictis, J. M. del Rosario, "Modular scalable I/O," (electronic copy) J. Parallel Distrib. Comput. 17, 1-2 (Jan. 1993), E. DeBenedictis and M. Del Rosario, "ncube Parallel I/O Software," in Proceedings of the 1992 International Phoenix Conference on Computers and Communications. E. DeBenedictis, S. Ghosh, and M. Yu, "A Novel Algorithm for Discrete-Event Simulation," IEEE Computer, June 1991, pp Ghosh, S.; Debenedictis, E., "An asynchronous distributed discrete event simulation algorithm for cyclic circuits using a data-flow network," Systems, Man, and Cybernetics, 'Decision Aiding for Complex Systems, Conference Proceedings., 1991 IEEE International Conference on, vol., no., pp vol.1, Oct 1991 M. Yu, S. Ghosh, E. DeBenedictis, "A provably correct, non-deadlocking parallel event simulation algorithm, " in Proceedings of the 24th Annual Symposium on Simulation (New Orleans, Louisiana, United States). A. H. Rutan, Ed. Annual Simulation Symposium. IEEE Computer Society Press, Los Alamitos, CA, E. DeBenedictis and P. Madams, "ncube's Parallel I/O with Unix Compatibility," in Proceedings of the Sixth Distributed Memory Computing Conference, May E. DeBenedictis, "Hypercube Unix," in Proceedings of the Fourth Conference on Hypercube Concurrent Computers and Applications, March E. DeBenedictis and B. Ackland, "Circuit Simulation on a Hypercube," in Proceedings of the MULTI '88 Conference, February 1988, pp E. DeBenedictis, "Multiprocessor Architectures are Converging," in Proceedings of the Third Conference on Hypercube Concurrent Computers and Applications, January 1988, pp E. DeBenedictis, "Distributed programs and subroutines for multiprocessors," in Proceedings of the Third Conference on Hypercube Concurrent Computers and Applications: Architecture, Software, Computer Systems, and General Issues - Volume 1 (Pasadena, California, United States, January 19-20, 1988). G. Fox, Ed. ACM, New York, NY, Erik P. DeBenedictis, "A Multiprocessor Using Protocol-Based Programming Primitives," in International Journal of Parallel Programming, February 1987, pp E. DeBenedictis, "Protocol-Based Multiprocessors," in Hypercube Multiprocessors 1987, M. Heath, ed., September 1986, pp E. DeBenedictis, "Multiprocessor Programming with Distributed Variables," in Hypercube multiprocessors 1986 (A ). Philadelphia, PA, Society for Industrial and Applied Mathematics, 1986, p B. Ackland, S. Lucco, T. London, and E. DeBenedictis."CEMU: A Parallel Circuit Simulator,". In Proceedings of the International Conference on Computer Design, October B. Ackland, S. Ahuja, E. DeBenedictis, T. London, S. Lucco, and D. Romero, "MOS Timing Simulation on a Message Based Multiprocessor," in Proceedings of the IEEE International Conference on Computer Design, October 1986, pp D. Shenton, E. DeBenedictis, and B. Locanthi, "Improved Reed-Solomon Decoding Using Multiple-Pass Decoding," in Journal of the Audio Engineering Society, Vol. 33, No. 11, pp , November 1985.

5 E. Brooks, III, G. Fox, M. Johnson, S. Otto, P. Stolorz, W. Athas, E. DeBenedictis, R. Faucette, C. Seitz, J. Stack, "Pure gage SU(3) lattice theory on an array of computers," Phys. Rev. Lett. 52, 2324 (1984) E. Brooks III, G. Fox, S. Otto, M. Randeria, B. Athas, E. DeBenedictis, M. Newton, and C. Seitz, "Glueball Mass Calculations on an Array of Computers," Nuclear Physics B (Field Theory and Statistical Systems), September 5, 1983, pp E DeBenedictis, "Techniques for Testing Integrated Circuits," Ph. D. Thesis. E. DeBenedictis and C. Seitz, "Testing and Structured Design," in Proceedings of the 1982 International Test Conference, November 1982, pp Erik DeBenedictis, Mitsuya Komamura, Bart Locanthi, and Larry White, "An Error Correction Algorithm of the Convolutional Type Using Threshold Decoding," 67th AES Convention, October 31/November 3, 1980, New York. SELECTED INVITED PRESENTATIONS Superconducting Electronics and Future Computing, ITRS Meeting on Fundamental Concepts in Emerging Research Architectures December 8, 2012 Exotic Technologies Panel and Time Capsule Submission for Most Exciting Architecture at SC 20, Exotic Technologies Panel Session at SC 06, Tampa, FL, November 13-16, Time capsule at NERSC to be opened at SC 20. Petaflops, Exaflops, and Zettaflops for Climate Modeling, Presentation at 8th Internation Workshop on Next Generation Climate Models for Advanced Hight Performance Computing Facilities, February 23-25, Albuquerque, NM Petaflops, Exaflops, and Zettaflops for Science and Defense, SAND B, Presentation at Cray User Group, May 16-19, 2005, Albuquerque NM Red Storm (English Hints), SAND P, Presentation at VNIIEF, April 12-13, 2005, Sarov, Russia "Beyond Petascale Computing -- The End Of The Beginning Or The Beginning Of The End?," SAND C, invited presentation at the Conference on Computational Physics 2004, Genoa, Italy, September 1-4, ASCI Red Storm and and Supercomputer Scalability, SAND P, Symposium on Supercomputations, VNIIEF, Sarov, Russia, October 6-10, 2003 How Sandia May Reach 1000 TFLOPS, SAND P, Mission Critical Computing Conference, Washington DC, June 19-20, 2003 The Red Storm Computer Architecture and its Implementation, SAND P, CCGrid 2003, Tokyo Japan, May 12-15, 2003 Red Storm Update, SAND P, HPC User Forum, Sundance Utah, April 9, 2003 E. DeBenedictis, "Distributed programs and subroutines for multiprocessors," in Proceedings of the Third Conference on Hypercube Concurrent Computers and Applications: Architecture, Software, Computer Systems, and General Issues - Volume 1 (Pasadena, California, United States, January 19-20, 1988). G. Fox, Ed. ACM, New York, NY, SAND DOCUMENTS Selected documents approved for public release as part of my work for Sandia National Laboratories

6 Red Storm Update, SAND P, HPC User Forum, Sundance Utah, April 9, 2003 The Red Storm Computer Architecture and its Implementation, SAND P, CCGrid 2003, Tokyo Japan, May 12-15, 2003 How Sandia May Reach 1000 TFLOPS, SAND P, Mission Critical Computing Conference, Washington DC, June 19-20, 2003 A Network Architecture for Petaflops Supercomputers, SAND Report SAND ASCI Red Storm and and Supercomputer Scalability, SAND P, Symposium on Supercomputations, VNIIEF, Sarov, Russia, October 6-10, 2003 The Sandia Petaflops Planner, SAND Report SAND "Beyond Petascale Computing -- The End Of The Beginning Or The Beginning Of The End?," SAND C, invited presentation at the Conference on Computational Physics 2004, Genoa, Italy, September 1-4, "Beyond Petascale Computing -- The End Of The Beginning Or The Beginning Of The End?," SAND P, presentation at ANL, Argonne, IL, September 14, Issues in Supercomputer Architecture for the Next Dozen Years, SAND P, presentation at NMSU, Las Cruces, NM, January 29, 2004 Extreme Supercomputing, SAND P, seminar at University of Notre Dame, CS & Eng. and Center for Nano Science and Technology, September 13, 2004 Taking ASCI Supercomputing to the End Game, SAND Report SAND Devices and Architecture for Maximum Supercomputer Performance, SAND Report SAND C, paper at SC 04, November 6-12, 2004, Pittsburgh, PA Completing the Journey of Moore's Law, SAND , presentation at SOS 8, April 13-14, 2004, Charleston, SC Completing the Journey of Moore's Law, SAND P, presentation at IBM Austin, April 23, 2004, Austin, Texas Completing the Journey of Moore's Law, SAND P, presentation at Notre Dame, May 4, 2004, South Bend, IN Completing the Journey of Moore's Law, SAND P, presentation at UIUC, May 5, 2004, Champaign, IL Completing the Journey of Moore's Law, SAND P, presentation at PNNL, August, 25, 2004, Richland, WA Applications Modeling for Supercomputer Architecture, SAND P, presentation at meeting with VNIIEF, May 31-June 4, 2004, Vienna, Austria Completing the Journey of Moore's Law, presentation at ARSC Reversible Logic for Supercomputing, released as SAND C, presentation at Computing Frontiers 2005, May 4-6, 2005, Ischia, Italy

7 Red Storm (no pictures), SAND P, Presentation at VNIIEF, April 12-13, 2005, Sarov, Russia Red Storm (English Hints), SAND P, Presentation at VNIIEF, April 12-13, 2005, Sarov, Russia Reversible Logic for Supercomputing, SAND , Presentation at Computing Frontiers and RC'05, the First International Workshop on Reversible Computing, May 4-6, 2005, Ischia, Italy Reversible Logic for Supercomputing actual presentation, SAND , Presentation at Computing Frontiers and RC'05, the First International Workshop on Reversible Computing, May 4-6, 2005, Ischia, Italy Reversible Logic for Supercomputing posted, SAND , Presentation at Computing Frontiers and RC'05, the First International Workshop on Reversible Computing, May 4-6, 2005, Ischia, Italy Petaflops, Exaflops, and Zettaflops for Science and Defense, SAND B, Presentation at Cray User Group, May 16-19, 2005, Albuquerque NM Maintaining Scalability of Information Processing Systems, SAND C, Proposal to CRA Conference on Grand Research Challenges "Revitalizing Computer Architecture Research", December 4-7, 2005, Monterey Bay, CA Issues for the Future of Supercomputing: Impact of Moore's Law and Architecture on Application Performance, SAND P, Tutorial at SC 05, November 14, 2005, Seattle, WA Frontiers of Extreme Computing, SAND P, overview of Zettaflops Workshop, October 23-27, 2005, Santa Cruz, CA Quantum Programming for Classical Programmers, SAND P, presentation for sharing with non- Sandia collaborators, December 19, 2005 Petaflops, Exaflops, and Zettaflops for Climate Modeling, Presentation at 8th Internation Workshop on Next Generation Climate Models for Advanced Hight Performance Computing Facilities, February 23-25, Albuquerque, NM Review of Entangled State Quantum Cryptography: Eavesdropping on the Ekert Protocol, Public Report SAND P Quantum Dot Cellular Automata (QDCA) Strategic Partnership: Extending Moore's Law: Part 2, Computer Sciences Issues, SAND P, final report presentation for National Institute of Nanotech Education (NINE) project under LDRD, August 1, 2006 Quantum Dot Cellular Automata (QDCA) Strategic Partnership: Extending Moore's Law: Part 1, Physical Sciences Issues, SAND P, final report presentation for National Institute of Nanotech Education (NINE) project under LDRD, August 1, 2006 Issues for the Future of Supercomputing: Impact of Moore's Law and Architecture on Application Performance, Tutorial at SC 06, November 13, 2006, Tampa, FL S. Frost-Murphy, M. Ottavi, M. Frank, E. DeBenedictis "On the Design of Reversible QDCA Systems, " SAND Exotic Technologies Panel and Time Capsule Submission for Most Exciting Architecture at SC 20, Exotic Technologies Panel Session at SC 06, Tampa, FL, November 13-16, 2006 Beyond Moore's Law Computer Architecture, SAND , LDRD final report, October, 2014 A different way to formulate computing: Optimal Adiabatic Scaling (OAS) and Processor-In-Memory-and- Storage (PIMS), October, 2014

8 Scaling Beyond Moore's Law with Processor-In-Memory-and-Storage (PIMS), SAND , ISI visit, November, 2014 Spreadsheet associated with Scaling Beyond Moore's Law with Processor-In-Memory-and-Storage (PIMS), SAND , ISI visit, November, 2014 Review of "cross neural" research effort, SAND , November, 2014 Cognitive Computing for Security, SAND , LDRD final report, September, 2015 Scaling to Nanotechnology Limits with the PIMS Computer Architecture and a new Scaling Rule, SAND , February, 2015 Scaling Beyond Moore's Law with Processor-In-Memory-and-Storage (PIMS), SAND , ITRS ERD/IEEE Rebooting Computing Meeting, November, 2014 Error-Corrected Computing, SAND , Presentation at Georgia Tech, May 21, 2015 OSTP Nanotechnology-Inspired Grand Challenge: Sensible Machines, SAND , Whitepaper associated with Nanotechnology Grand Challenge, October 20, 2015 IEEE Rebooting Computing: Motivation, Genesis, and Context, SAND , IEEE Future Directions Committee ICCAD Special Session, November 2, 2015 How to plan for continued device-level energy scaling, SAND , SC 15 (Supercomputing 2015) sub workshop, November 18, 2015 RCS4 4th Rebooting Computing Summit "Roadmapping the Future of Computing", SAND , Report of IEEE workshop, December 9-11, 2015 Sensible Machine Grand Challenge, SAND , Notre Dame Solid State Physics Seminar Series, April 1, 2016 Sensible Machine Grand Challenge, SAND , NIST Seminar, June 21, 2016 Using Neuromorphic Computing Methods for General Computer Performance Growth, SAND C, Abstract for NANO (printed in program), August 22-25, 2016 REPORTS Marina Chen, Young-il Choo, Erik DeBenedictis, Jingke Li, and Janet Wu, "Speedup of a financial application using the crystal compiler for hypercubes". Technical Report YALEU/DCS/TR-673, Dept. of Computer Science, Yale University, January E. DeBenedictis, D. Shenton, Finite Element Algorithms for Multiprocessors Using Distributed Variables, Bell Labs Technical Report number Erik P. DeBenedictis, "HOMOGENEOUS MACHINE CURRENT STUFF," Lab Notebook for Homogeneous Machine and Nearest Neighbor Concurrent Processor (NNCP), later renamed Cosmic Cube, archived December Erik P. DeBenedictis, "The Fabrication of Pc Boards at Caltech," internal document, October 29, Erik P. DeBenedictis, "Caltech NNCP Project," presentation, July, Erik P. DeBenedictis, "Use of the Global Communications Lines in the Homogeneous Machine," internal document, February 9, 1982.

9 Erik P. DeBenedictis, "A Communications Operating System for the Homogeneous Machine," Caltech display file Erik P. DeBenedictis and Charles L. Seitz "Homogeneous Machine Technical Plan," project proposal for the Homogeneous Machine and Nearest Neighbor Concurrent Processor (NNCP), later renamed Cosmic Cube, January 9, E. Brooks, G. Fox, R. Gupta, O. Martin, S. Otto, and E. DeBenedictis, "Nearest Neighbor Concurrent Processor," CALT , DOE Research and Development Report, September Erik DeBenedictis, "Highlights of Design F," September 23, 1981, internal document. David Shenton, Erik DeBenedictis, and Bart Locanthi, "Error Correction for PCM Digital Audio Systems," presentation at AES, not in proceedings. E.Brooks, G.Fox, R. Gupta, O. Martin, S. Otto, and E. DeBenedictis "Nearest Neighbour Concurrent Processor," unpublished memo, Caltech, September 17, E. DeBenedictis, "A Preliminary Report on the Caltech ARPA Tester Project. Technical Report. California Institute of Technology. [CaltechCSTR: tr-80] Erik P. DeBenedictis, User's Manual For A ROM Emulator March, 1978, report. Erik P. DeBenedictis, The Z80 Datawidget Microprocessor Development System December, 1977, report. PARALLEL COMPUTER ARCHIVAL DOCUMENTS I've been encouraged by colleagues to post some documents to the Internet related to the development of the Cosmic Cube. At Caltech in 1981, Eugene Brooks and I started a project that was called both the Homogeneous Machine (HM) and the Nearest Neighbor Concurrent Processor (NNCP). The project grew over time to include many people, as will be described shortly. The 64 processor version of this machine was subsequently renamed to "Cosmic Cube" and became a focal point for a growing number of people to develop parallel scientific codes. Users and Government funders followed the 3 MFLOPS Cosmic Cube with a series of exponentially larger and more powerful computers for 25 years, up to IBM's current 360 TFLOPS Blue Gene/L supercomputer at Livermore. This represents a 100 million fold scale-up! The story I can contribute on this page is to give some background as to why the HM/NNCP/Cosmic Cube architecture survived repeated downselects and received 100 million fold scale-up where its competitors faltered. Readers may draw their own conclusions from the original documents I've linked to this site, but my guidance is to look at two things: the strong connection between the architecture and semiconductor scaling and the presence of an user community with a scalable problem right from the time of the architecture.

10 Competing architectures of the time (SIMD, shared memory, vector), each fared less well on one of these criteria. The early 1980s were a remarkable period at Caltech: Carver Mead and his colleagues were contributing heavily to VLSI design and scaling/ Richard Feynman was making major contributions to the "physics of computation" and "quantum computing/" A bunch of us in Computer Science and Physics were creating a parallel architecture destined to be successful. All these people were working together. Using unmodified microprocessors, HM/NNCP/Cosmic Cube was the full beneficiary of Moore's Law for microprocessor performance scaling over almost the entire existance of microprocessors. Specifically observe that a key 1982 proposal document for the 3 MFLOPS HM/NNCP/Cosmic Cube contained a diagram (figure 1, page 3) and justification for scaling to a 500 nm semiconductor process and a system very much like the IBM Blue Gene system (noting that Blue Gene continued scaling another factor of four to 130 nm). I have linked digitized versions of documents from the 1980s to the paragraphs below. The Cosmic Cube project started in the summer of By the end of the summer, there was a propoosal document and a DOE report describing intentions as well as prototype hardware. ARPA funded the development of the initial hardware based on this technical plan, complete with a photograph of working prototype hardware and with systems software operational. The four-processor, wire wrapped system became the basis for the paper Glueball Mass Calculations on an Array of Computers that included many of the simulation principles and computer systems analyses that were repeated many times in subsequent decades. By October, 1982, the PC boards were being fabricated for the 64-processor hardware that was later to be called the Cosmic Cube. However, I had graduated from Caltech and needed a job. I used this interview presentation and other presentation materials, and got a job at Bell Labs. As I left Caltech in December, 1982, I put the hardware lab notebook and the other hardware lab notebook away. 25 years later I scanned them and put on the Web.