-SQA-SCOTTISH QUALIFICATIONS AUTHORITY HIGHER NATIONAL UNIT SPECIFICATION GENERAL INFORMATION PHYSICS OF SEMICONDUCTOR DEVICES.

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1 -SQA-SCOTTISH QUALIFICATIONS AUTHORITY HIGHER NATIONAL UNIT SPECIFICATION GENERAL INFORMATION -Unit number Unit title- -Superclass category- -Date of publication- (month and year) -Originating centre for unit- PHYSICS OF SEMICONDUCTOR DEVICES XL March 1998 SQA DESCRIPTION- GENERAL COMPETENCE FOR UNIT: Explain the physics of the operation of semiconductor devices. NOTE: It is strongly recommended that centres which offer this course/unit should have close and continuing links with the appropriate industry and must provide evidence of an integrated approach to the course delivery. OUTCOMES: 1. describe the fabrication sequences of common semiconductor device families; 2. use physical models to describe the operation of semiconductor devices; 3. describe the operation of sub-micron semiconductor devices; 4. describe possible future trends in semiconductor devices. CREDIT VALUE: 2 HN Credits ACCESS STATEMENT: Access to the unit is at the discretion of the centre. However it would be beneficial if the candidate has completed the HN Units: Introduction to Semiconductor Devices and Fabrication Processes, Physics for Semiconductor Devices; Physical and Chemical Properties of Silicon or similar qualifications or experience

2 Additional copies of this unit can be obtained from: The Committee and Administration Unit, SQA, Hanover House, 24 Douglas Street, Glasgow G2 7NQ, (Tel: ). At the time of publication the cost is 1.50 per unit (minimum order 5.00). 2

3 HIGHER NATIONAL UNIT SPECIFICATION STATEMENT OF STANDARDS Unit number: Unit title: PHYSICS OF SEMICONDUCTOR DEVICES Acceptable performance in this Unit will be the satisfactory achievement of the standards set out in this part of the specification. All sections of the statement of standards are mandatory and cannot be altered without reference to SQA. OUTCOME 1. DESCRIBE THE FABRICATION SEQUENCE OF COMMON SEMICONDUCTOR DEVICE FAMILIES PERFORMANCE CRITERIA (a) (b) (c) (d) Description of the structure of common semiconductor devices is clear and precise. The operation of common semiconductor devices is clear and precise. Description of the fabrication sequence of common semiconductor devices is clear and precise. The impact of critical process steps and device features on the device performance are correctly described. RANGE STATEMENT Devices: CMOS; bipolar. Critical process steps: process steps which control the electrical performance. EVIDENCE REQUIREMENTS Written or oral evidence of the candidate s ability to describe the structure and fabrication sequence of common semiconductor devices. Written or oral evidence of the candidate s ability to describe the impact of critical process steps and devices features on the device performance. 3

4 OUTCOME 2. USE PHYSICAL MODELS TO DESCRIBE THE OPERATION OF SEMICONDUCTOR DEVICES PERFORMANCE CRITERIA (a) (b) (c) (d) Use physical models to describe the operation of common semiconductor devices from a qualitative perspective. Physical models are correctly used to describe the operation of common semiconductor devices from a quantitative perspective. The operating characteristics of common semiconductor devices are accurately sketched. The differing applications for common semiconductor devices are accurately described. RANGE STATEMENT Devices: CMOS: bipolar. Physical model: MOS transistor models; equations describing Vt and Ids; pinchoff punch through; geometry effects; breakdown; leakage; latch-up; pn junctions; drift and diffusion; Ebers-Moll equations; gain; isolation. Applications: high packing density; low power; high speed. EVIDENCE REQUIREMENTS Written/performance evidence of the candidate s ability to use physical models to describe the operation of common semiconductor devices. Written/graphical evidence of the candidate s ability to sketch the operating characteristics of common semiconductor devices. OUTCOME 3. DESCRIBE THE OPERATION OF SUB-MICRON SEMICONDUCTOR DEVICES PERFORMANCE CRITERIA (a) Description of the fabrication sequence of sub-micron semiconductor devices and device features is clear and precise. (b) The limitations of operation of sub-micron scale semiconductor devices are clearly explained. 4

5 RANGE STATEMENT Devices: MOS; bipolar; DRAM. Device features: LDD; poly emitter; sub-channel implants; LOCOS; trench; capacitor structures. Limits of operation: short channel effects; scaling laws; hot carrier effects; velocity saturation; isolation. EVIDENCE REQUIREMENTS Written or oral evidence of the candidate s ability to describe the structure, fabrication, and operation of sub-micron semiconductor devices. OUTCOME 4. DESCRIBE POSSIBLE FUTURE TRENDS IN SEMICONDUCTOR DEVICES PERFORMANCE CRITERIA (a) (b) (c) Description of the limitations in performance of semiconductor devices is clear and precise. Description of the impact of future trends in semiconductor device fabrication is clearly described. Description of the impact of future trends in semiconductor device structures is clearly described. RANGE STATEMENT The range is fully expressed in the performance criteria. EVIDENCE REQUIREMENTS Written or oral evidence of the candidate s ability to describe the impact of future trends on semiconductor device fabrication. MERIT STATEMENT: To gain a pass in this unit, a candidate must meet the standards set out in the outcomes, performance criteria, range statements and evidence requirements. 5

6 To achieve a merit in this unit, a candidate must demonstrate a superior or more sophisticated level of performance. In this unit this might be shown in the following ways: (i) (ii) displaying a greater depth of knowledge of the physics of semiconductor devices; displaying evidence of further reading or study. ASSESSMENT In order to achieve this unit, candidates are required to present sufficient evidence that they have met all the performance criteria for each outcome within the range specified. Details of these requirements are given for each outcome. The assessment instruments used should follow the general guidance offered by the Scottish Qualifications Authority (SQA) assessment model and an integrative approach to assessment is encouraged. (See references at the end of support notes). Accurate records should be made of the assessment instruments used showing how evidence is generated for each outcome and giving marking schemes and/or checklists, etc. Records of candidates achievements should be kept. These records will be available for external verification. SPECIAL NEEDS Proposals to modify outcomes, range statements or agreed assessment arrangements should be discussed in the first place with the external verifier. Copyright SQA 1998 Please note that this publication may be reproduced in whole or in part for educational purposes provided that: (i) (ii) no profit is derived from the reproduction; if reproduced in part, the source is acknowledged. 6

7 HIGHER NATIONAL UNIT SPECIFICATION SUPPORT NOTES Unit number: Unit title: PHYSICS OF SEMICONDUCTOR DEVICES SUPPORT NOTES: This part of the unit specification is offered as guidance. None of the sections of the support notes is mandatory. NOTIONAL DESIGN LENGTH: SQA allocates a notional design length to a unit on the basis of time estimated for achievement of the stated standards by a candidate whose starting point is as described in the access statement. The notional design length for this unit is 80 hours. The use of notional design length for programme design and timetabling is advisory only. PURPOSE The purpose of this unit is to introduce the candidates to the physics of semiconductor devices currently being manufactured and the impact of future trends on the fabrication processes. NOTE: It is strongly recommended that centres which offer this course/unit should have close and continuing links with the appropriate industry and must provide evidence of an integrated approach to the course delivery. CONTENT/CONTEXT This unit should be delivered in the context of manufacturing techniques which are currently in use in the semiconductor industry. It may also be delivered in conjunction with HN Unit Introduction to Semiconductor Devices and Fabrication Processes and an integrative approach to delivery and assessment is recommended. A minimum of 3 common semiconductor devices should be covered in outcomes 1 and 2. Candidates should be encouraged to use periodicals in research of the trends which may impact the current semiconductor fabrication processes. ASSESSMENT PROCEDURES Centres may use the Instruments of Assessment which are considered to be the most appropriate. Examples of Instruments of Assessment which could be used are as follows: Outcome 1 Outcome 2 Structured questions Practical assignment/case study/project 7

8 Outcome 3 Outcome 4 Structured questions Case study/project/assignment. REFERENCES 1. Guide to unit writing, SQA, 1993 (Code: A018). 2. Guide to assessment, SQA, 1993 (Code: B005). 3. Guide to certification, SQA, 1996 (Code: F025). 4. Notes for unit writers, SQA, 1995 (Code: A041). 5. Microelectronic Processing; W Scot Ruska; McGraw-Hill; 1988 ISBN VLSI Technology 2nd Edition; S.M. Size; McGraw-Hill; 1988 ISBN Solid State Technology; Penn Well Publishing Company, Westmead House, 123 Westmead Road, Sutton, Surrey, England, SM1 4JH. 8. Semiconductor International; Cahners Publishing Netherlands, Postbus 9000, 2130 DB Hoofddrop, The Netherlands. For details of other SQA publications, please contact staff in the Sales and Despatch section (Tel: ) who can supply you with a copy of the publication list (Code: X037). Copyright SQA 1998 Please note that this publication may be reproduced in whole or in part for educational purposes provided that: (i) (ii) no profit is derived from the reproduction; if reproduced in part, the source is acknowledged. 8