-SQA-SCOTTISH QUALIFICATIONS AUTHORITY HIGHER NATIONAL UNIT SPECIFICATION GENERAL INFORMATION INTRODUCTION TO ANALOGUE AND DIGITAL CIRCUITS

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1 -SQA-SCOTTISH QUALIFICATIONS AUTHORITY HIGHER NATIONAL UNIT SPECIFICATION GENERAL INFORMATION -Unit Number Superclass- -Title- XL INTRODUCTION TO ANALOGUE AND DIGITAL CIRCUITS DESCRIPTION- GENERAL COMPETENCE FOR UNIT: Explaining the operation of basic analogue and digital electronic circuits for non-specialist electronic candidates. OUTCOMES 1. explain the operation of semiconductor analogue devices; 2. explain the operation of semiconductor analogue circuits; 3. design combinational logic circuits to meet a given specification; 4. assemble and test combinational logic circuits. CREDIT VALUE: 1 HN Credit ACCESS STATEMENT: Access to this unit is at the discretion of the Centre. However, it would be beneficial if candidates had a knowledge of basic electrical circuit theory. This may be evidenced by possession of NC Module: , Electrical Fundamentals; Transformation and Rectification or similar qualifications or experience

2 For further information contact: Committee and Administration Unit, SQA, Hanover House, 24 Douglas Street, Glasgow G2 7NQ. Additional copies of this unit may be purchased from SQA (Sales and Despatch section). At the time of publication, the cost is 1.50 (minimum order 5.00). 2

3 HIGHER NATIONAL UNIT SPECIFICATION STATEMENT OF STANDARDS UNIT NUMBER: UNIT TITLE: INTRODUCTION TO ANALOGUE AND DIGITAL CIRCUITS Acceptable performance in this unit will be the satisfactory achievement of the standards set out in this part of the specification. All sections of the statement of standards are mandatory and cannot be altered without reference to SQA. OUTCOME 1. EXPLAIN THE OPERATION OF SEMICONDUCTOR ANALOGUE DEVICES PERFORMANCE CRITERIA (a) Mode of conduction in N-type and P-type semiconductors is explained correctly. (b) Standard symbols for semiconductor diode devices and transistors are drawn correctly. (c) Operating principles of semiconductor diode devices are explained correctly. (d) Operating principles of transistors are explained correctly. RANGE STATEMENT Diode devices: junction diode; light emitting diode; photodiode; zener diode. Transistors: bi-polar; field effect. EVIDENCE REQUIREMENTS Written and graphical evidence is required to show that the candidate can explain conduction in N-type and P-type semiconductors, draw the symbols for the devices listed and explain their operating principles. 3

4 OUTCOME 2. EXPLAIN THE OPERATION OF SEMICONDUCTOR ANALOGUE CIRCUITS PERFORMANCE CRITERIA (a) (b) (c) (d) Circuit diagrams for analogue circuits based on diodes are drawn correctly. Operation of analogue circuits based on diodes are explained correctly. Circuit diagrams for transistor circuits are drawn correctly. Operation of transistor circuits are explained correctly. RANGE STATEMENT Analogue circuits: full-wave rectifier; back-emf protection; opto-isolator; voltage stabilization. Transistor circuits: switch to control LED; amplifier with potential divider bias; common emitter; common source. EVIDENCE REQUIREMENTS Written and graphical evidence is required to show that the candidate can draw the circuit diagrams for the circuits listed and explain their operation. OUTCOME 3. DESIGN COMBINATIONAL LOGIC CIRCUITS TO MEET A GIVEN SPECIFICATION PERFORMANCE CRITERIA (a) (b) (c) (d) Truth tables for INVERTER and 2-input AND, OR, XOR, NAND and NOR gates are stated correctly. Boolean expression for INVERTER and 2-input AND, OR, XOR, NAND and NOR gates are stated correctly. The truth table produced from a written description of a practical problem with three inputs is correct. The design of a combinational logic circuit, using gates, minimum of 3 levels, and based on a given truth table is correct. RANGE STATEMENT The range for this outcome is fully expressed within the performance criteria. 4

5 EVIDENCE REQUIREMENTS Written or oral evidence is required to show that the candidate can state the truth tables, Boolean expressions and circuit truth table. Written evidence is required for the circuit design. OUTCOME 4. ASSEMBLE AND TEST COMBINATIONAL LOGIC CIRCUITS PERFORMANCE CRITERIA (a) (b) (c) The IC pin connection diagram produced from a logic circuit diagram with three inputs is correct. Using integrated circuits the circuit is assembled correctly from the IC pin connection diagram. Assembled circuit is tested and shown to operate in accordance with the truth table. RANGE STATEMENT The range for this outcome is fully expressed within the performance criteria. EVIDENCE REQUIREMENTS Written and graphical evidence is required to show that the candidates can produce an IC pin connection diagram. Performance evidence to show that the candidate can assemble, test and operate a correctly functioning combinational logical circuit with a minimum of 3 levels. MERIT To gain a pass in this unit, a candidate must meet the standards set out in the outcomes, performance criteria, range statements and evidence requirements. To achieve a merit in this unit, a candidate must demonstrate a superior or more sophisticated level of performance. This may be demonstrated by achieving at least three of the following: (i) (ii) (iii) (iv) the explanation of the operation of the analogue circuit; the explanation of the operation of semi-conductor diode and transistor devices; the minimising of the combinational logic design exercise; the testing procedure of the combinational logic circuit

6 ASSESSMENT In order to achieve this unit, candidates are required to present sufficient evidence that they have met all the performance criteria for each outcome within the range specified. Details of these requirements are given for each outcome. The assessment instruments used should follow the general guidance offered by the SQA assessment model and an integrative approach to assessment is encouraged. (See references at the end of support notes). Accurate records should be made of the assessment instruments used showing how evidence is generated for each outcome and giving marking schemes and/or checklists, etc. Records of candidates achievements should be kept. These records will be available for external verification. SPECIAL NEEDS Proposals to modify outcomes, range statements or agreed assessment arrangements should be discussed in the first place with the external verifier. Copyright SQA 1997 Please note that this publication may be reproduced in whole or in part for educational purposes provided that: (i) (ii) no profit is derived from the reproduction; if reproduced in part, the source is acknowledged. 6

7 HIGHER NATIONAL UNIT SPECIFICATION SUPPORT NOTES UNIT NUMBER: UNIT TITLE: INTRODUCTION TO ANALOGUE AND DIGITAL CIRCUITS SUPPORT NOTES: This part of the unit specification is offered as guidance. None of the sections of the support notes is mandatory. NOTIONAL DESIGN LENGTH: SQA allocates a notional design length to a unit on the basis of time estimated for achievement of the stated standards by a candidate whose starting point is as described in the access statement. The notional design length for this unit is 40 hours. The use of notional design length for programme design and timetabling is advisory only. PURPOSE The purpose of this unit is to provide an introduction to basic analogue and digital circuits for candidates, who have not studied electronics at NC level and will not be specialising in electronics in later stages of their course. CONTENT/CONTEXT Although not assessed, it is recommended that in outcomes 1 to 3 candidates be exposed to as much practical work as time permits. For example, in the analogue section, pre-assembled boards could be used to allow the candidate to observe full-wave rectification, voltage stabilisation and the switching and amplifying action of a transistor. Brief reports explaining the operation of the circuits could be used as formative assessment. In the digital section, each of the basic gates could be treated as a black box with input and output pins identified and the candidate asked to obtain the truth table experimentally. In view of the time available it is not intended in outcome 3 that the circuit designed be minimised to achieve the outcome. The final circuit may be implemented using AND, OR and NOT gates, or only NAND gates. If the candidate had sufficient background knowledge minimisation could be discussed. APPROACHES TO GENERATING EVIDENCE Evidence for outcomes 1 and 2 could be a written test paper covering all performance criteria. Alternatively, it could take the form of several written reports produced as a result of practical investigations. Outcome 3 Outcome 4 Written assessment. Circuit diagram showing correct pin numbering for ICs. Practical work covered by a checklist completed by assessor. 7

8 ASSESSMENT PROCEDURES Outcomes 1 and 2 Need not be assessed separately. It may be preferable to teach the diode and its applications and assess this in the manner described above, and then repeat the process with the transistor. If necessary, this could be split into bipolar and FET. Outcome 3 The circuit design produced from the truth table need not be a minimised circuit. It may take the form of AND, OR and NOT gates or only NAND gates. The truth table produced for performance criterion (c) should be used in performance criterion (d). Outcome 4 Ideally the circuit to be assembled should be the one designed in outcome 3. However, it is acceptable to provide the candidate with the logic diagram of a circuit to be constructed, along with the truth table to enable its performance to be verified. EXEMPLARS A typical specification for the combinational logic circuit might be as follows. A sheet metal guillotine operates whenever a safety guard is in place and the operator presses a pushbutton switch. When the guard is in the correct position a microswitch produces a logic 1 signal. When the pushbutton is pressed a logic 1 is generated. In addition, there is a keyswitch which produces a logic 0 in the off position and a logic 1 in the on position. Design a combinational logic circuit which will allow the guillotine to operate when the guard is in place, the keyswitch is off and the pushbutton is pressed. To allow for maintenance, the guillotine should also operate when the guard is not in position, the maintenance engineer puts the keyswitch to on and the pushbutton is pressed. This meets the specification of a 3 input, 3 level combinational circuit. It can be implemented (no minimisation) using 2 AND gates, 1 OR gate and 2 inverters, or 5 NAND gates. PROGRESSION There is no progression from this unit. The unit has been designed with the sole purpose of providing a non-electronic specialist with elementary knowledge of and skills in analogue and digital electronics. REFERENCES 1. Guide to unit writing. 2. For a fuller discussion on assessment issues, please refer to SQA s Guide to Assessment. 8

9 3. Information for centres on SQA s operating procedures is contained in SQA s Guide to Procedures. 4. For details of other SQA publications, please consult SQA s publications list. Copyright SQA 1997 Please note that this publication may be reproduced in whole or in part for educational purposes provided that: (i) (ii) no profit is derived from the reproduction; if reproduced in part, the source is acknowledged. 9

-SQA-SCOTTISH QUALIFICATIONS AUTHORITY HIGHER NATIONAL UNIT SPECIFICATION GENERAL INFORMATION

-SQA-SCOTTISH QUALIFICATIONS AUTHORITY HIGHER NATIONAL UNIT SPECIFICATION GENERAL INFORMATION -Unit Number- 8540317 -Superclass- -Title- XM RADIO COMMUNICATION CIRCUITS -----------------------------------------