Topic List: Review. CSE241 VLSI Digital Circuits Winter Lecture 20: Futures for VLSI. Logistics. HW Solutions. HW Solutions.

Transcription

1 CSE241 L20 Futures.1 Kahng, UCSD 2003 Topic List: Review CSE241 VLSI Digital Circuits Winter 2003 Lecture 20: Futures for VLSI Week 1: MOSFETs, interconnects, R/C/L, performance, power, Verilog Week 2: ASIC flow, design planning/convergence methodologies, key design challenges, STA, datapath blocks, performance coding Week 3: Logic synthesis (covering, technology mapping, local transformations), synthesis, timing Week 4: Timing, clocking, clock distribution, timing libraries, project announcement (v.1), synthesis for timing, placement Week 5: Routing, place-and-route, IBM ACG placement, STA lab (PrimeTime) Week 6: Power distribution, noise analysis, parasitic extraction, P&R lab (SE), project announcement (v. 2) Week 7: Verification, formal verification lab, manufacturing and manufacturability Week 8: Manufacturability, SDF back-annotation into PrimeTime Week 9: Packaging, cost Week 10: Memory blocks, VLSI futures CSE241 L20 Futures.2 Kahng, UCSD 2003 Logistics Today s class: Where the BIG research challenges are Power-centric view of VLSI futures References: - A. B. Kahng, A Roadmap and Vision for Physical Design, Proc. ISPD, April D. Sylvester and H. Kaul, Performance Challenges in Nanometer Design, Proc. DAC, June Class ends at 10:30am Will have OH s on Monday Will broadcast ABK project current status by Sunday night Any logistics questions, send HW Solutions HW #14 (3pt): (i) All costs of distinct paths to reach a given node from the source must be remembered, instead of only the minimum path cost. (ii) (1) You need to look "to the side" as you route. In other words, determining whether a route can be pushed forward by the next grid edge requires checking not just the other endpoint of the edge, but also the neighboring nodes to that endpoint's left and right, to see whether any crosstalk bound has been violated. (2) You need to worry about an adjacency between the victim and aggressor_i starting, then stopping, then resuming again. This means that a list of all aggressors must be maintained and referenced whenever the route is being pushed forward. (iii) Yes. One can make a wide-wire grid (WWG) that captures sets of three consecutive tracks. E.g., column i in the WWG captures tracks i, i+1 and i+2 in the actual routing grid. Whether a grid point in the WWG is empty is determined by examining all three of the underlying routing grid tracks. This explanation is really for right-way wiring, i.e., to go "sideways" requires handling both rows and columns in the WWG - essentially, this means that you must have grid points that capture a square array of 3x3 track intersections in the underlying routing grid. An alternative approach is simply to perform "crosstalk-driven" routing per your solution to (ii), but with infinite cost of adjacency to a nearest-neighbor. CSE241 L20 Futures.3 Kahng, UCSD 2003 CSE241 L20 Futures.4 Kahng, UCSD 2003 HW Solutions HW #15 (3pt): (i) The end-case placement assumes that the whitespace in the instance is evenly distributed. This is suboptimal. (ii) (Give data from a netlist.) You should have found that quite a few nets have 2 and 3 pins (at least 40%). This percentage is growing since there are more inserted repeaters, weaker drivers (and increasing ratio of interconnect R to driver R), etc. as technology scales. (iii) Some ideas are: (1) fanout limits, (2) output load capacitance limits, (3) output slew time limits, and (4) artificially tweaking the pin input caps in the library (to some extent, increasing per-unit length wire cap will also tend to reduce fanouts). HW #16 (2pt): (a) There are 4 internal nodes of the slicing tree, of which the first (root) is horizontal. The other 3 internal nodes can be either H or V, implying 2 3 = 8 possibilities. There are also 5 total blocks, each of which can be put into two orientations, implying another factor of 2 5 = 32. What is the number Ak of distinct slicing floorplans for k blocks? Actually, this does get kind of tedious. By hand: A 1 = 1, A 2 = 2, A 3 = 6, A 4 = 22. Trying to find previous results on Google leads to Catalan numbers (for binary trees) and thence to super-catalan numbers. A recurrence is given by B. Yao, H. Chen, C.- K. Cheng and R. Graham (of UCSD), in their ISPD-2001 paper. In particular, A 5 = 90. Multiply by 2 8 to obtain the answer. (b) A k is the k th super-catalan or Schroder number (see the given reference). (The main conclusion is that the number of floorplans grows rapidly with k, and hence it is difficult to optimize over all floorplans. This is one reason why no one has yet claimed my car as a prize from the open challenge made in April 2000.) CSE241 L20 Futures.5 Kahng, UCSD 2003 HW Solutions HW #17: (a) (2pt) Increase the percentiles that determine the WLM: More wires will be treated pessimistically, and hence more cell area, buffer area, and power will be used. Decrease the percentiles that determine the WLM: Fewer wires will be treated pessimistically, and less area and power will be used, but there is a higher likelihood that the design will fail to meet timing in placeand-route. (There is an interesting interaction between fanout, place-and-route, and WLM. If we believe that synthesis makes a high-fanout net only when the net does not affect critical paths, and if we further believe that timing-driven place-and-route does not carefully minimize wirelength of non-critical nets, then it is probably good to treat high-fanout nets pessimistically (this guardbands the assumption that we believe the synthesis tool is making). On the other hand, if we believe that synthesis makes a low-fanout net when the net is critical, and if we further believe that TD P&R more carefully minimizes the length of critical nets, then we might be more optimistic with the WLM for low-fanout nets.) Increase the clock frequency target: more buffers and higher-drive cells will be used, which actually increases the area of the design (eventually making wires longer, and timing harder to meet). So, the benefits of this technique eventually run out of steam. Decrease the clock frequency target: not applicable (would never do this in hopes of making timing). (b) (3pt) (Back up with evidence from P&R runs.) CSE241 L20 Futures.6 Kahng, UCSD 2003

2 CSE241 L20 Futures.7 Kahng, UCSD 2003 MT Solutions #1(a) My basic flow: (1) SC global placement, (2) post-placement STA, (3) clock sink useful-skew scheduling, (4) clock buffer tree construction that is useful-skew aware (cf. associative skew ), (5) standard-cell ECO placement (to put the buffers into the layout), (6) Steiner clock subnet routing at lower levels of the clock tree (following CTGen type paradigm), (7) bounded-skew clock subnet routing at all higher levels of the clock tree, and as necessary even at lower levels, to enforce useful skews, (8) global signal routing, (9) detailed signal routing, (10) post-detailed routing STA #1(b) Criteria: (1) likelihood of convergence with maximum clock frequency, (2) minimization of CPU time (by maximizing incremental steps, minimizing detailed steps, and minimizing iterations), (3) make a good tradeoff between wiring-based skew control and wire cost (this suggests Steiner routing at lower levels, bounded-skew routing at higher levels). [Comment 1. Criteria NOT addressed: power, insertion delay, variant flow for hierarchical clocking or gated clocking. Comment 2: I do not know of any technology for clock sink placement that can separate this from placement of remaining standard cells. So, my flow does not invoke this step. I also don t want post-route ECOs.] #1(c) Variants: (1) introduce Step 11: loop over Steps 3-10 (not adopted because costbenefit ratio was not attractive, and because there is a trial placement + global routing to drive useful-skew scheduling, buffer tree construction and ECO placement); (2) after Steps 1-4, re-place the entire netlist (global, detailed placement) and then skip Step 5 (not adopted because benefits of avoiding ECO placement and leveraging a good clock skeleton were felt to be small buffer tree will largely reflect the netlist structure, and replacing can destroy assumptions made in Steps 3-4); (3) can iterate the first 5 steps essentially by iterating: clock sink placement, (ECO placement for legalization), (incremental) standard-cell (global + detailed) placement (not adopted because I feel that any objective for standalone clock sink placement would be very fuzzy, e.g., based on sizes of intersections of fanin/fanout cones of sequentially adjacent FFs) MT Solutions #2 What happens every two technology nodes: (1) one more level of H is added (with WL = twice the WL used to implement the previous level of H total clock tree WL doubles); (2) the number of clock sinks and the number of buffers are each multiplied by 4; (3) frequency is multiplied by 4; (4) supply voltage is multiplied by (0.85) x (0.85) = ; and (5) the gate area of a given clock sink or buffer scales is reduced by a factor of 4 (0.7 ^ 4 = 0.24). In the analysis of CV 2 f power, V 2 f scales by (0.5) x (4) = 2x. Then, wire capacitance scales by 2x while gate and buffer capacitance scale by 1x. Conclusion: power dissipation due to wiring multiplies by 4, and power dissipation due to clock sinks multiplies by 2. This analysis assumes that static power can be ignored, and does not dissect wire capacitance into area + fringing components. Also, there is no accounting for possible need for wider wires at the top levels of the clock tree (e.g., for process variation robustness at higher frequencies). #3 The LEF file will remain roughly the same size (same richness of cell library, say, between masters), modulo possible changes in conventions (e.g., CTLF used to be a part of LEF) and modulo possible additional library model semantics (e.g., adding power modeling into LEF). The DEF file should at least double (the components and nets will double, but if there is extra routing complexity (more complex geometries, and more segments per connection due to antenna rules or badly scaling router heuristics) the DEF could grow significantly faster. CSE241 L20 Futures.8 Kahng, UCSD 2003 Project Logistics 4 pages of report + pointers Place your PDF report in ~projxx/public_html/ on VLSI CAD Lab machines, then a URL by midnight, Wednesday night (March 19 th ) Maximum of two pages for (A), and maximum of two pages for (B) - Minimum 10 point font, minimum 1-inch margins on all sides, US Letter paper only. Only PDF will be read. Report contents: - History: When you first completed synthesis, when you first completed P&R, when you first completed analyses (RSPF-based STA, FV) where first completed means the first time that you obtained a well-formed output - Final values of metrics: (A) Frequency, (B) Frequency / Area - CPU time, wall time and server type for flows used to obtain final metrics. - Assessment of methods that were (a) considered, (b) not tried (and why), (c) tried (how, using the tools), and (d) were found most enabling (with justification of how this credit assignment was determined). - Links to all final project files: runscripts, flow description ( README ), logfiles and journal files, report files (RCX, STA, FV, etc.), design files (.sv,.def). It will help to organize the project files and to put README files in each directory. Points will be deducted for incorrect spelling, incorrect grammar, and other indications that you did not read over your own report! - Hint: MSWord has spelling and grammar checks; use these. Also, ask your roommates/labmates/colleagues to read over your report before you turn it in. CSE241 L20 Futures.9 Kahng, UCSD 2003 The BIG Challenges CSE241 L20 Futures.10 Kahng, UCSD 2003 The Red Brick Wall vs Red Brick Example: Dielectric Permittivity YEAR TECHNOLOGY NODE DRAM ½ PITCH (nm) (SC. 2.0) MPU/ASIC ½ PITCH (nm) (SC. 3.7) MPU PRINTED GATE LENGTH (nm) (SC. 3.7) MPU PHYSICAL GATE LENGTH (nm) (SC. 3.7) Conductor effective resistivity (µω-cm) Cu intermediate wiring* Barrier/cladding thickness (for Cu intermediate wiring) (nm) Interlevel metal insulator effective dielectric constant (κ) Interlevel metal insulator (minimum expected) bulk dielectric constant (κ) Red Brick = ITRS Technology Requirement with no known solution Source: Semiconductor International - CSE241 L20 Futures.11 Kahng, UCSD 2003 CSE241 L20 Futures.12 C. Case, BOC Edwards ITRS-2001 Kahng, UCSD 2003

3 CSE241 L20 Futures.13 Kahng, UCSD 2003 SRC Grand Challenges 1. Extend CMOS to its ultimate limit 2. Support continuation of Moore's Law by providing a knowledge base for CMOS replacement devices 3. Enable Wireless/Telecomm systems by addressing technical barriers in design, test, process, device and packaging technologies 4. Create mixed-domain transistor and device interconnection technologies, architectures, and tools for future microsystems that mitigate the limitations projected by ITRS 5. Search for radical, cost effective post NGL patterning options 6. Provide low-cost environmentally benign IC processes 7. Increase factory capital utilization efficiency through operational modeling 8. Provide design tools and techniques which enhance design productivity and reduce cost for correct, manufacturable and testable SOC's and SOP's 9. Enable low power and low voltage solutions for mobile/battery conserving applications through system and circuit design, test and packaging approaches. 10. Enable very low cost components 11. Provide tools enabling rapid implementation of new system architectures SRC ICSS Key Technologies (Top 12) Systems S3.2: Early Design Space Exploration S1.2: Low Power, Real-Time Algorithms and Architectures S4.1: On-Chip Communication S1.3: High Bandwidth and/or Low Power Communication S2.4: Deep Submicron Aware Microarchitectures, Accounting for Noise, Power, Timing, Interconnects, etc. S1.1: High Level Specifications of Complex Systems Circuits C1.2: Digital Low Power and/or Low Voltage Circuit Design C2.1: Mixed Signal Circuits on Advanced Technologies C2.4: Mixed Signal Low Power and/or Low Voltage Circuit Design C1.1: Digital Circuits on Advanced Technologies C2.3: Mixed Signal Design for Test C2.2: Mixed Signal Noise Immune and/or Tolerant Circuits CSE241 L20 Futures.14 Kahng, UCSD 2003 ITRS Logical/Physical/Circuit Challenges Efficient and predictable implementation - Scalable, incremental analyses and optimizations - Unified implementation/interconnect planning and estimation/prediction - Synchronization and global signaling - Heterogeneous system composition - Links to verification and test - Reliable, predictable fabric- and application-specific silicon implementation platforms - Cost-driven implementation flows Variability and design-manufacturing interface - Uncertainty of fundamental chip parameters (timing, skew, matching) due to manufacturing and dynamic variability sources - Process modeling and characterization - Cost-effective circuit, layout and reticle enhancement to manage manufacturing variability - Increasing atomic-scale variability effects ITRS Logical/Physical/Circuit Challenges Silicon complexity, non-ideal device scaling and power management - Leakage and power management - Reliability and fault tolerance - Analysis complexity and consistent analyses / synthesis objectives - Recapture of reliability lost in manufacturing test Circuit design to fully exploit device technology innovation - Support for new circuit families that address power and performance challenges - Implementation tools for SOI - Analog synthesis - Increasing atomic-scale effects - Adaptive and self-repairing circuits - Low-power sensing and sensor interface circuits; micro-optical devices CSE241 L20 Futures.15 Kahng, UCSD 2003 CSE241 L20 Futures.16 Kahng, UCSD 2003 Design-Manufacturing Integration 2001 ITRS Design Chapter: Manufacturing Integration = one of five Cross-Cutting Challenges Goal: share red bricks with other ITRS technologies Lithography CD variability requirement new Design techniques that can better handle variability Mask data volume requirement solved by Design-Mfg interfaces and flows that pass functional requirements, verification knowledge to mask writing and inspection ATE cost and speed red bricks solved by DFT, BIST/BOST techniques for high-speed I/O, signal integrity, analog/ms Does X initiative have as much impact as copper? PD + PIDS (Devices/Structures) CV/I trend (17% per year improvement) = constraint Huge increase in subthreshold I off Room temperature: increases from 0.01 ua/um in 2001 to 10 ua/um at end of ITRS (22nm node) - At operating temperatures ( deg C), increase by 15-40x Standby power challenge - Manage multi-v t, multi-v dd, multi-tox in same core - Aggressive substrate biasing - Constant-throughput power minimization - Modeling and controls passed to operating system and applications Aggressive reduction of Tox Physical Tox thickness < 1.4nm (down to 1.0nm) starting in 2001, even if high-k gate dielectrics arrive in 2004 Variability challenge: 10% < one atomic monolayer CSE241 L20 Futures.17 Kahng, UCSD 2003 CSE241 L20 Futures.18 Kahng, UCSD 2003

4 CSE241 L20 Futures.19 Kahng, UCSD 2003 PD + Lithography 10% CD uniformity is a red brick today 10% < 1 atomic monolayer at end of ITRS This year: Lithography, PIDS, FEP agreed to raise CD uniformity requirement to 15% (but still a red brick) Design for variability Novel circuit topologies Circuit optimization (conflict between slack minimization and guardbanding of quadratically increasing delay sensitivity) Centering and design for $/wafer Design for when devices, interconnects no longer 100% guaranteed correct? Potentially huge savings in manufacturing, verification, test costs PD + Assembly and Packaging Goal: cost control ($0.07/pin, $2 package, ) Grand Challenge for A&P: work with Design to develop diepackage co-analysis, co-optimization tools Bump/pad counts scale with chip area only Effective bump pitch roughly constant at 300um MPU pad counts flat from , but chip current draw increases 64% IR drop control challenge Metal requirements explode with I chip and wiring resistance Power challenge 50 W/cm 2 limit for forced-air cooling; MPU area becomes flat because power budget is flat More control (e.g., dynamic frequency and supply scaling) given to OS and application Long-term: Peltier-type thermoelectric cooling, CSE241 L20 Futures.20 Kahng, UCSD 2003 PD + Manufacturing Test High-speed interfaces (networking, memory I/O) Frequencies on same scale as overall tester timing accuracy Heterogeneous SOC design Test reuse Integration of distinct test technologies within single device Analog/mixed-signal test Reliability screens failing Burn-in screening not practical with lower Vdd, higher power budgets overkill impact on yield Design challenges: DFT, BIST PD in the loop! Analog/mixed-signal Signal integrity and advanced fault models BIST for single-event upsets (in logic as well as memory) Reliability-related fault tolerance CSE241 L20 Futures.21 Kahng, UCSD 2003 How to Share Red Bricks Cost is the biggest missing link within the ITRS Manufacturing cost (silicon cost per transistor) Manufacturing NRE cost (mask, probe card, ) Design NRE cost (engineers, tools, integration, ) Test cost Technology development cost who should solve a given red brick wall? Return On Investment (ROI) = Value / Cost Value needs to be defined ( design quality, time-to-market ) Understanding cost and ROI allows sensible sharing of red bricks across industries CSE241 L20 Futures.22 Kahng, UCSD 2003 A Top-10 List (0) Sensible unifications to co-optimize global signaling, manufacturability enhancement, and clock/test/power distribution (1) Fundamental new combinatorial optimization technologies (and possibly geometry engines) for future constraintdominated layout regimes (2) New decomposition schemes for physical design (3) Global routing that is truly path-timing aware, truly combinatorial, and able to invoke atomistic interconnect synthesis (4) In-context layout synthesis that maximizes process window while meeting electrical (functional) spec A Top-10 List (5) Efficient analog and mixed-signal layout synthesis (6) Methods for synchronization and global signaling at multi- GHz or Gbps, extending to system-level (7) Analysis, modeling and simulation methods that are tied more closely to PD syntheses, and that adapt to resource and accuracy and fidelity constraints (8) Revival of platform-specific (parallel, distributed, hardwareaccelerated) algorithm implementations (9) Mindset changes, including a culture of duplicating, deconstructing and debunking CSE241 L20 Futures.23 Kahng, UCSD 2003 CSE241 L20 Futures.24 Kahng, UCSD 2003

5 CSE241 L20 Futures.25 Kahng, UCSD 2003 VLSI Futures (Power Focus) VLSI Futures Many challenges in nanometer design Signal integrity, RC delay, inductance (self and mutual), soft error rates, process variability (V th control), reliable multi-ghz clock distribution, robust power distribution, designer productivity, etc. Focus on POWER Low-power design = high-performance design Key challenges in power: Affordable power removal: Packaging Efficient power management: Design Reliable power delivery: Distribution (not discussed today) Start with a view of future high-speed (workstations, servers) microprocessors (MPUs) CSE241 L20 Futures.26 Kahng, UCSD 2003 Working Model of High-Perf MPUs Less Performance Per Watt (Pollack s Rule) A number of CPU cores (~10M transistors each) surrounded by numerous levels of caches (L1,L2,L3) 1-T SRAM or other exotic technologies may improve memory density and/or performance More cores == more work done == more power! Current example: IBM Power4 (2 CPU MB L2); dissipates 115W in 3.8cm 2 die Power limits the computational capabilities of such a processor CPU core CPU core Cache (L1 + L2), 2MB CSE241 L20 Futures.27 Kahng, UCSD 2003 CPU CPU CPU CPU CPU CPU Cache (L1, L2, L3), 16MB May Dec Jun SPECfp Per Watt Jan Jul Feb Date of Data Aug Mar New microarchitectures aren t helping: 40-70% better performance At the expense of 2-3X area! (power also higher) Oct Apr Refs: specbench.org, Pollack, CSE241 L20 Futures.28 Gelsinger (Intel) Kahng, UCSD 2003 Power = Nanometer Design Driver Submicron ( µm) and deep submicron (0.35~0.13 µm) regimes focused on: Maintaining speed improvements despite lower V dd (constant voltage to constant field scaling) Nanometer design ( 100 nm) will be driven by minimizing power consumption while sustaining throughput and reliability Outline Packaging limitations on power Global signaling and layout optimization Packaging Limitations Packaging limitations on power Global signaling and layout optimization Static power analysis Multi-V th +V dd + sizing Static power analysis Multi-V th + V dd + sizing CSE241 L20 Futures.29 Kahng, UCSD 2003 CSE241 L20 Futures.30 Kahng, UCSD 2003

6 CSE241 L20 Futures.31 Kahng, UCSD 2003 Rising Power Density Equation governing the relationship among power, temperature, and packaging capabilities: Power Density (W/cm 2 ) Year of Production Data taken from Intel, IBM, AMD, Compaq, Sun, ITRS2000 θ ja = ( Tchip Tambient ) Pchip Packaging and Power To maintain reasonable on-die (junction) temperatures, package thermal resistance must decrease Cooling costs are highly non-linear with power consumption Circuit reliability degrades (exponentially) with rising junction temperatures Oxide lifetime Electromigration Hot carrier effects Performance also penalized by high operating temperatures Slower transistors Higher interconnect resistance Higher leakage currents == higher total power θ ( T T ) Pchip ja chip ambient Power Density (W/cm 2 ) CSE241 L20 Futures.32 Kahng, UCSD 2003 = Cost ($) ~ 30-40W/cm 2 Packaging Capabilities/Limitations MPU packaging improving with time Current paradigm = heat sinking + fans + flip-chip Modern θ ja s on par with liquid cooling in mid-late 1980s Continued gains may require paradigm shifts in technology Refrigeration (vapor compression = $1/W) Liquid cooling Limitations of affordable packaging options? ~50 W/cm 2 for forced air + heat sinking >100 W/cm 2 for liquid cooling and other advanced technologies Maximum Power Is Too Constraining Maximum power is artificial Synthetic benchmarks maximum utilization Package is designed to tolerate it Typical power == highest dissipation under normal loads between typical and maximum power is currently ~25% Ref: Compaq Ref: Intel CSE241 L20 Futures.33 Kahng, UCSD 2003 CSE241 L20 Futures.34 Kahng, UCSD 2003 Leveraging Typical vs. Maximum Power Package design for maximum power wastes $$$ Better approach: Set thermal design point = largest commonly occurring power dissipation in typical applications, P typical Design package to tolerate P typical (sustained) Apply dynamic thermal management techniques to restrict power to P typical - Little performance loss as MPU rarely runs apps that exceed P typical CSE241 L20 Futures.35 Kahng, UCSD 2003 Dynamic Thermal Management Simple hardware example: Intel P4 compare current across a diode (temperature sensitive) to reference current source Reference current source Temperature sensing diode Power flag Current comparator Power flag reduces internal clock frequency, limiting power and temperature Other approaches voltage scaling, speculation control Multiple sensors on large dies, placed in applicationspecific hot-spots CSE241 L20 Futures.36 Kahng, UCSD 2003

7 CSE241 L20 Futures.37 Kahng, UCSD 2003 Global Signaling and Layout Packaging limitations on power Global signaling and layout optimization Static power analysis Multi-V th +V dd + sizing Global Signaling Current global signaling paradigm insert large static CMOS repeaters to reduce wire RC delay Impending problems: Too many repeaters - 180nm processors: 22K repeaters (Itanium), 70K (Power4) - Project 1-1.5M repeaters at 45-65nm technologies Too much power - Many large repeaters = significant static and dynamic power Too much noise - Repeater clustering complicates power distribution - Inductive coupling across wide bus structures CSE241 L20 Futures.38 Kahng, UCSD 2003 Cell Layout Optimization Advanced layout techniques must allow Continuous individual device sizing Variable p/n ratios Tapered FET stacking sizes Arbitrary V th assignments within gates First cut: Cadabra 15-22% power reduction using 1 st two approaches under fixed footprint constraint Optimize specific instances of standard gates Multi-Vdd Packaging limitations on power Global signaling and layout optimization Static power analysis Multi-V th +V dd + sizing Multi-V dd Ref: Hurat, Cadabra GDSII Import Compact fixed width CSE241 L20 Futures.39 Kahng, UCSD 2003 CSE241 L20 Futures.40 Kahng, UCSD 2003 Multi-Vdd Status Lower Power Via Rich Replacement Idea: Incorporate two V dd s to reduce dynamic power Limited to a few recent Japanese multimedia processors Example 0.3 µm, 75MHz, 3.3V media processor (Toshiba) - Total power savings of 47% in logic, 69% in clock Dynamic voltage scaling of mobile processors - Transmeta Crusoe, Intel Speedstep, etc. - Not considered in this talk Very powerful technique currently applied only in low-performance designs Mentality: today s high performance parts aren t limited by power Media processors and other low speed designs have many non-critical paths 60-70% of paths have delay half the clock period After replacement, most paths become near critical What about high-speed microprocessors? % of total paths Path delay (normalized to clock period) CSE241 L20 Futures.41 Kahng, UCSD 2003 CSE241 L20 Futures.42 Kahng, UCSD 2003

8 CSE241 L20 Futures.43 Kahng, UCSD 2003 Similar Story For High-Performance IBM 480 MHz PowerPC shows over 50% of paths have delay less than half the clock period Implies that high-performance designs can benefit from multi-v dd Resizing Is Not The Right Answer Post-synthesis optimizations resize gates to recover power on non-critical paths Looks similar to pre- and post-replacement figures in media processor Ref: Akrout, JSSC98 Before postsynthesis resizing After postsynthesis resizing This is the wrong approach for nanometer design! Ref: Sirichotiyakul, DAC99 CSE241 L20 Futures.44 Kahng, UCSD 2003 Multi-Vdd Instead of Sizing Power ~ C V dd 2 f, where f is fixed Key: Reducing gate width impacts power sub-linearly Interconnect capacitance is not affected Reducing supply voltage cuts power quadratically All capacitive loads have lower voltage swing How can we minimize delay penalty at low V dd? Challenges For Multi-Vdd Area overhead Toshiba reported 7% rise in area due to placement restrictions, level converters, additional power grid routing EDA tool support for the above issues (placement, dual power routing) Noise analysis Additional shielding required between Vdd,low and Vdd,high signals? Including clock network CSE241 L20 Futures.45 Kahng, UCSD 2003 CSE241 L20 Futures.46 Kahng, UCSD 2003 Static Power Packaging limitations on power Global signaling and layout optimization Multi-V th +V dd + sizing Static power Static Power Why do we care about static power in non-portable devices? Standby power is wasted -- leaves fewer Watts for computation Worsens reliability by raising die temperatures Leakage current is a function of V th and subthreshold swing (S s ) (x10 at operating vs. room temp!) Vth Ss Ioff µ A/ µ m S s expected to remain at mv/dec (room temp) Device technology may cut this by ~20% V th reductions are mandated by scaling V dd V th has been around V dd /5 CSE241 L20 Futures.47 Kahng, UCSD 2003 CSE241 L20 Futures.48 Kahng, UCSD 2003

9 CSE241 L20 Futures.49 Kahng, UCSD 2003 Current Status No sub-1v technologies demonstrate good on/off current performance (yet expect improvements in production) Oxide scaling is running out of steam; overall ~3x I off per node Reference Intel,00 Samsung,00 NEC,00 TI,99 Intel,99 NEC,00 ITRS node T ox (Å) (electrical) (physical) V dd I on (µa/µm) I off (na/µm) Leakage Suppression Approaches Dual-V th (most common) Low-V th on critical paths, high-v th off Only cost is additional masks MTCMOS Series inserted high-v th device cuts leakage current when off (sleep mode) Delay and area penalties, control device sizing is critical Other techniques Vdd Pull Up Pull Down Vout ITRS 2000 ITRS 2000 ITRS 2000 ITRS (physical) 8-12 (physical) 6-8 (physical) 11 (uses high-k) Working numbers Substrate biasing to control V th Dual-V th domino - Use low-v th devices only in evaluate paths Vcontrol High Vth Device Parasitic Node CSE241 L20 Futures.50 Kahng, UCSD 2003 Multi-Vth + Vdd + Sizing Packaging limitations on power Global signaling and layout optimization Static power analysis Multi-V th +V dd + sizing Multi-Everything Need an approach that selects between speed, static power, and dynamic power Should be scalable to nanometer design Rules out dual-v th domino or other dynamic logic families (low supplies kill performance advantages) Techniques mentioned so far Flexible, optimized cell layouts Dual-V th Put them all together CSE241 L20 Futures.51 Kahng, UCSD 2003 CSE241 L20 Futures.52 Kahng, UCSD 2003 Multi-Vdd Can Leverage Vth s Existing designs using multi-v dd do not alter V th in low- V dd cells Highly sub-optimal, delay is fully penalized Limits cell replacement limits power savings Much better solution: reduce V th in low-v dd cells to carefully balance delay, static power, and dynamic power Enforce technology scaling within a chip whenever we reduce V dd, we also reduce V th to maintain speed CSE241 L20 Futures.53 Kahng, UCSD 2003 Multi-Vdd + Vth Negates Delay Penalty Delay ~ CV dd /I on Scenarios Constant V th (current paradigm) Scale V th to maintain constant static power Scale V th to reduce static power linearly with V dd Delay penalty is substantially 4 offset I on is very sensitive to V th at V dd < 1V P static reduces with V dd due to linear term and smaller I off (I on and DIBL ) Result: V dd = 0.2V gives 89% dynamic power reduction, constant P static, 29% delay increase Delay (Normalized) Constant V th (0.11V) Scaled V th, Constant P static Conservatively Scaled V th 35-nm, nominal V dd = 0.6V V dd (V) CSE241 L20 Futures.54 Kahng, UCSD

10 CSE241 L20 Futures.55 Kahng, UCSD 2003 Now Add Sizing + multi-v th + sizing/cell layout optimization attacks power from many angles (multi-dimensional) Depending on criticality and switching activities, noncritical gates can be: Assigned Vdd,low Assigned Vdd,low + lower Vth Assigned Vth,high Downsized (at the individual transistor level if advantageous) Assigned Vdd,low and upsized - For gates that cannot tolerate Vdd,low delay, this can be power efficient And others Intra-Cell Vth Assignments Finer granularity of V th assignment Assigning top/bottom NMOS/PMOS in a stack to low-v th (other devices high-v th ) balances speed and leakage - 62% average leakage reduction compared to all-low V th gate (3- in NAND) - Worst-case delay is 7.2% faster than all-high V th gate Added manufacturing costs hard to quantify (stricter requirements on process recipes, longer process development times) Still unclear whether this is beneficial and costeffective CSE241 L20 Futures.56 Kahng, UCSD 2003 Summary Power density must saturate to maintain affordable packaging options 50 W/cm 2 means W for future large MPUs Dynamic thermal management saves 25% on packaging power budget will leverage multiple V th s to offset delay penalty at low V dd More widespread re-assignment to Vdd,low Use V dd first instead of re-sizing to take advantage of large path slacks Anticipated power savings of 50-80% Static power also addressed through multi-v th + V dd + sizing V th difficult to control in ultra-short channels Intra-cell V th assignment + MTCMOS/variants + sleep modes CSE241 L20 Futures.57 Kahng, UCSD 2003 Conclusions Future High-End MPU Many cores, lots of cache (possibly 1-T SRAM or edram) Memory/logic breakdown is set by power density limitations (packaging/cost) - By end of roadmap, <10% of chip will be logic CPU cores, up to 0.5 GB SRAM Several V dd s and V th s 2 V dd s and 3 V th s are possible Aggressive use of sleep modes in both logic and memory Breakdown of P static and P dynamic?? Optimal could be larger than we think: 30+% static power Global communication using low-swing, current-steering, differential signaling fabrics Process variation, particularly V th control, will be crucial Design tools must enable designers to implement all the above CSE241 L20 Futures.58 Kahng, UCSD 2003