Fabrication of JFET device on Si (111) for sensor interface array circuit

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1 Fabrication of JFET device on Si (111) for sensor interface array circuit Yoshiko Kato, a) Takashi Hashimoto, Liew Yoke Ching, Hidekuni Takao, Kazuaki Sawada, and Makoto Ishida Department of Electric and Electronic Engineering, Toyohashi University of Technology, 1 1 Hibarigaoka, Tempaku-cho, Toyohashi , Japan a) kato@dev.eee.tut.ac.jp Abstract: In this study, single-sided gate JFET structure on Si (111) has been proposed and investigated for array circuit. The performance of the single-sided gate JFET can be optimized by simulation, and has sufficient performance as sensor interface device. The noise level of the (111) JFET at low frequency was about 1/50 of that of a (111) n-mosfet, and 1/25 of that of a (100) n-mosfet. It has been experimentally confirmed that single-sided gate JFET is a suitable device as sensor interface on Si (111), possessing large interface states. Keywords: JFET, Si (111), low noise, sensor interface, array circuit Classification: Electron devices References [1] H. S. Momose, T. Ohguro, S. Nakamura, Y. Toyoshima, H. Ishiuchi, and H. Iwai, Ultrathin Gate Oxide CMOS on (111) Surface-Oriented Si Substrate, IEEE Trans. Electron Devices, vol. 49, no. 9, pp , [2] H. S. Momose, T. Ohguro, K. Kojima, S. Nakamura, and Y. Toyoshima, Electrical characteristics of ultra-thin gate oxide CMOS on (110) surfaceoriented Si substrate, Tech. Report of IEICE, SDM , pp , [3] M. Ishida, K. Sogawa, A. Ishikawa, and M. Fujii, Selective growth of Si wire for intelligent nerve potential sensors using vapor-liquid-solid growth, Transducers 99, vol. 2, pp , [4] Reda R. Razouk, and Bruce E. Deal, Dependence of Interface State Density on Silicon Thermal Oxidation Process Variable, J. Electrochem. Soc., vol. 126, pp , [5] W. Buttler, G. Lutz, G. Cesura, P. F. Manfredi, V. Speziali, and A. Tomasini, Short channel, CMOS-compatible JFET in low noise applications, Nucl.Instrum.Meth.A, vol. 326, pp , [6] H. Takao, R. Asaoka, Y. Ito, K. Sawada, S. Kawahito, and M. Ishida, A JFET Device for CMOS Integrated Circuits and Its Application to CMOS-Based LOW Noise Amplifier, Tech. Report of IEICE, SDM , pp. 1 6,

2 1 Introduction Recently, device structures fabricated on various orientations of silicon substrate have been developed in a breakthrough in downsizing of MOS devices. And the researches into improved performance on various surface orientations of silicon crystals other than Si (100) have attracted attention. It has been reported that mobility of p-mosfets on Si (110) and Si (111) surface are higher than that on Si (100) surface [1, 2]. In the future, it is inferred that it will be necessary to fabricate sensor system with integrated circuits on various surface orientations of Si substrate such as intelligent nerve potential sensor using vapor-liquid-solid growth [3]. However, there are large interface states at SiO 2 -Si interfaces on these silicon surface orientations. Large interface states at SiO 2 -Si interface, result in the generation of high 1/f noise. In particular, the interface state density at SiO 2 -Si(111) is considered to be significantly higher than that at SiO 2 - Si(100) [4]. Therefore, it is feared that 1/f noise of a MOSFET fabricated on Si (111) would be very high. There are many sensor systems that cover signal frequencies between DC and 10 khz. The frequency band of the sensing signal corresponds to the band of 1/f noise, and the SN ratio of sensor system degrades because of 1/f noise. Attention is, therefore, focused on the junction field-effect transistor (JFET) as a low noise device. In the case of a MOS device, the channel is formed at the SiO 2 -Si interface and carriers drifting in the channel are influenced by the interface states. On the other hand, the channel of a JFET is formed within the Si substrate, and the performance of the JFET is not affected by interface states. Therefore, it is expected that 1/f noise of JFET would be lower than that of MOSFET. Additionally, a JFET can be fabricated by almost the same process as CMOS [5, 6]. It is anticipated that the JFET is essential for a sensor system fabricated on a surface with large interface states. This study focuses on the Si (111) surface which possesses large interface states. If a low noise device for a sensor system is fabricated on Si (111) surface, high-performance sensor system on Si (111) can be achieved. In order to use the JFET effectively as a sensor, a JFET structure that was suitable for a two-dimensional array circuit was proposed and fabricated on Si (111). Current-voltage characteristic of fabricated JFET was evaluated, and 1/f noise was compared with 1/f noise of an n-mosfet on Si (111) and Si (100). The performance of the JFET for a sensor system on Si (111) substrate was discussed. 2 JFET structure In order to use a JFET device for an array circuit, it is important that the applied voltage of one JFET does not affect the other JFET devices. In other words, gate of one JFET must be independent of the gates of other JFET devices. Additionally, the pixels need to be formed in the same p-well in order to reduce the pixel area. A suitable structure for a JFET in an array circuit is shown in Fig. 1. Source, gate, drain and p-well are laid out radially 244

3 from the center in this JFET structure. It is possible to fix the p-well voltage and only vary the gate voltage, because the gate is separated from the p-well. The channel width is controlled only by the gate depletion layer. Therefore, multiple JFET devices can be formed in the p-well. In this paper, this JFET is called single-sided gate JFET. This single-sided gate JFET is proposed as suitable structure for an array circuit. Fig. 1. Top view and cross-section of single-sided gate JFET. 3 Fabrication This single-sided gate JFET will be integrated into CMOS circuits in the future. Fabrication technology for JFET-CMOS integrated circuits has been established in our laboratory [6]. The designed JFET was fabricated by the process based on this JFET-CMOS process. N-type Si (111) substrate was used to fabricate single-sided gate JFET devices. A fabrication process is as the following. (a) The p-well regions and active regions were fabricated with the standard CMOS fabrication process. (b) The p + contact to the p-well was formed at the same time as the source and the drain of p-mosfet. (c) The n + region as source and drain regions of the JFET were formed at thesametimeasthesourceandthedrainofthen-mosfet,followedby thermal annealing. (d) P and B ions were implanted in sequence into the JFET channel region, and thermal annealing was repeated. In this process, the n-channel region and p + gate region of JFET were formed. ASiO 2 passivation film was then deposited, contact holes formed, and interconnection was completed using the standard CMOS fabrication process. The interconnection material was Al. Only one additional mask was required to integrate JFET channel fabrication with the CMOS fabrication process. 245

4 4 Results and discussion 4.1 I-V characteristics of single-sided gate JFET The device performance of fabricated single-sided gate JFET was evaluated. Figure 2 (a) shows I D -V G characteristic. The solid line is the measured characteristic and the dashed line is a calculated characteristic using the simulation tool SPECTRA. The drain voltage V D was 50 mv. The measurement indicated a pinch-off voltage (V p )of 0.5Vandag m of 18.5 µs. The measured V p was shifted by only several mv positive with respect to the simulated V p. The measurement results of single-sided gate JFET almost corresponds to the simulation results. It is considered that characteristics of single-sided gate JFET can be further optimized by the simulation. Figure 2 (b) shows measured I D -V D characteristic. At V D nearly equal to V G -V p,drainare pinched off and a good characteristic is obtained in the saturation region. g ds is 0.15 µs. From above results, the characteristics of a single-sided gate JFET can be optimized by simulation, and are satisfactory for detection of signals. Fig. 2. Measured characteristics of single-sided gate JFET. (a) I D -V G characteristic. (b) I D -V D characteristic. 4.2 Noise characteristic comparison between (111) JFET and n-mosfet The noise characteristic of a single-sided gate JFET on Si (111) was evaluated. For comparison, the noise characteristic of a (111) n-mosfet and a (100) n-mosfet fabricated in p-well were also evaluated. In order to make the measurement, a common-source circuit was used with a load resistance R, and an output noise spectrum of device was measured with a FFT analyzer. From this measured noise spectrum and the gain obtained at operation point of the circuit, the input referred noise was calculated. A low noise battery was used as the power source voltage V dd and the bias voltage V b. The measurement results of input referred noise in the (111) JFET and the (111) n-mosfet are shown in Fig. 3. In (111) n-mosfet, the influence of 1/f noise is highly apparent and is still observed at 100 khz. In contrast, the 246

5 Fig. 3. Measured input referred noise of fabricated (111) JFET, (111) n-mosfet and (100) n-mosfet. 1/f noise of the (111) JFET is not observed above than 100 Hz. Also, the noise spectrum of the (111) JFET is quite low, as compared to that of the (111) n- MOSFET. Particularly at the low frequency, the noise spectrum of the (111) JFET is less than 1/50 of that of the (111) n-mosfet. Additionally, as a result of noise characteristic comparison between the (111) JFET and a (100) n-mosfet, the noise spectrum of the (111) JFET is about 1/25 of that of the (100) n-mosfet at 100 Hz. It is considered that noise characteristic of JFET is not influenced by interface states because the channel of JFET is formed within the substrate. Therefore, 1/f noise can be decreased by using JFET devices in a circuit, even if the circuit is fabricated on surface with large interface states. It is confirmed that the noise problem can be solved by using JFET even when Si (111) substrate is used for circuit fabrication. In particular, this JFET device is expected to be effective as a low noise input device in an interface circuit for a sensor system. 5 Conclusion A single-sided gate JFET for array circuit was fabricated on Si (111). The performance of the single-sided gate JFET can be optimized by simulation, and has sufficient performance to detect the signals. The noise level of the (111) JFET at low frequency was about 1/50 of that of a (111) n-mosfet, and 1/25 of that of a (100) n-mosfet. It is confirmed that low noise sensor system can be realized on Si (111) surface using the single-sided gate JFET. It is inferred that the array circuit with low noise at low frequencies can be realized by using a single-sided gate JFET, even when a substrate with high interface states is used for circuit fabrication. Acknowledgments This work was supported in The 21st Century COE Program Intelligent Human Sensing and a Grant-in-Aid for Scientific Research from the ministry of Education, Culture, Sports, Science and Technology Japan. 247