XHB μm Process Family: 0.6 Micron Modular High Voltage High Precision Analog RF Technology DESCRIPTION KEY FEATURES OVERVIEW

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1 0.6 μm Process Family: XHB Micron Modular High Voltage High Precision Analog RF Technology DESCRIPTION The XHB06 is X-FAB's 0.6 Micron High-Voltage High Precision Analog RF Technology, optimized for applications requiring operating voltages of 5V to 30V. Main target applications are power management, RF circuits and high precision analog applications mixed with digital parts for Telecommunication, Consumer, Automotive and Industrial products. The digital part is fully compatible with X-CMOS 0.6 process family. Reliable design rules, precise SPICE models, cell libraries, IP s and development kits support the process for major EDA vendors. KEY FEATURES OVERVIEW 0.6-micron double poly, triple metal N-well CMOS process 13 mask layers CORE process with wide selections of devices: -5V - NMOS 5V isolated NMOS with high-side capability 5V PMOS and Natural PMOS with high-side capability 30V HV NMOS 12V, 18V, 28V HV PMOS with high-side capability 5V lateral PNP for linear application vertical NPN for analog applications 12V lateral PNP with high-side capability 15V NDMOS with high-side capability ESD self-protecting 20V NDMOS with highside capability 10V Schottky diodes 20V Schottky diodes with high-side capability 10V linear capacitors, resistors, MOS varator OTP options: zener-zaps and poly fuses Optional s to realize NPN and HV NPN with poly emitter for linear as well as RF applications (3 additional mask layers), and additional devices: 5V and 15V NPN transistors with various layout and well adjusted for most typical requirements 30V PIP Optical window, polyimide as stress relief, black resist as light shielding layer. EPROM option Electrostatic discharge (ESD) protection in accordance with MIL-STD 5V ESD NMOS transistors 5V I/O with improved ESD robustness High precision BSIM3V3 SPICE models for CMOS and Gummel Poon model for bipolars Excellent analogue performance with accurate device matching Four digital core cell libraries optimised for most typical applications 2000 to 2500 effective gates per mm2 Typical gate delays (digital) of 160 ps 5V and 3.3V I/O cell libraries IEEE boundary scan macros High-density RAM, DPRAM. ROM blocks Development kits for major EDA tools APPLICATIONS RF and Mixed signal embedded systems; systems on a chip (SOC) High precision mixed signal circuits High-Voltage output drivers Comparators and Op-Amps Analog frontends for sensors Communications, consumer, automotive and industrial markets QUALITY ASSURANCE X-FAB spends a lot of effort to improve the product quality and reliability and to provide comprehensive support to the customers. This is maintained by the direct and flexible customer interface, the reliable manufacturing process and complex test and evaluation conceptions, all of them guided by strict quality improvement procedures developed by X-FAB. This comprehensive, proprietary quality improvement system has been certified to fulfill the requirements of the ISO 9001, ISO TS and other standards. 1

2 DELIVERABLES PCM tested wafers Optional engineering services: Multi Project Wafer (MPW) and Multi Layer Mask Service (MLM) Optional design services: feasibility studies, Place & Route, synthesis, custom block development DIGITAL LIBRARIES Foundry-specific optimized libraries Standard core library for high speed digital blocks Low-noise, standard core library with separate bulk supply for reduced substrate noise Low-power core library, 50% less power, 40% less area Low-noise, low-power core library with separate bulk supply for reduced substrate noise Pad-limited IO library Core-limited IO library IEEE 1364 Verilog simulation models IEEE VHDL-VITAL simulation models Synthesis libraries Macrofunction and IP s on request RAM, DPRAM, ROM PRIMITIVE DEVICES LV and HV NMOS/PMOS, HV DMOS Transistors ESD transistors RF and HV NPN Bipolar Transistors Lateral PNP Bipolar Transistors Junction Diodes Schottky diodes PIP, MIM and sandwich Capacitors Poly silicon, diffusion and metal resistors Varactors Inductors Zener zap, poly fuse PRIMITIVE DEVICES ROM RAM DPRAM EPROM XHB06 BASIC DESIGN RULES Mask width [µm] Spacing [µm] N-well Active Area Sinker Poly-silicon Gate Poly-silicon Resistor Collector Base Emitter Contact Metal 1, Via 1, Metal Thick Via Thick Metal

3 XHB06 DEVICES SCHEMATIC CROSS SECTION CMOS Transistor, PIP Capacitor, & Resistor Lateral PNP, Vertical NPN MIM Capacitor, Spiral Inductor 3

4 XHB06 PROCESS FLOW Core Module Additional Modules Wafer Start N buried layer N-well Active area P-well Collector implant Poly 1 N-LDD implant P-LDD implant N+ implant P+ implant Contact Metal 1 Via 1 Metal 2 PAD P buried layer EPROM Depletion implant Special VARDIO mask ESD implant Intrinsic base block Intrisic base implant HVBase implant Polysilicon Capacitor Emitter window etch Poly2 deposition High resistive implant Poly2 implant Extrinsic base implant Poly2 etch MIM capacitor Via 2 Metal 3 Thick Via Thick Metal Passivation deposition Optical area etch UV erase Black resist coating Polyimide deposition NOPBUR EPROM DEPL VARDIO ESD SCHOTTKY HRBASE HVNPN HVNPN NPN POLY2 HRPOLY POLY2 NPN POLY2 MIM MET3 THKMET EPROM OPTO EPROM LIGHTSLD PIMIDE mask steps 4

5 XHB06 PROCESS MODULES Module Descriptions Masks No. CORE MOS CORE 13 ESD ESD implant 1 HRBASE Base resistor 0 * POLY2 Poly2 1 NPN NPN 2 HVNPN HV NPN 1 CAPPOLY Poly1-Poly2 capacitor 1 MIM MIM capacitor 1 HRPOLY High resistive poly 1 * DEPL Depletion NMOS 1 VARDIO Varicap diode 1 SCHOTTKY Schottky diode 1 * EPROM EPROM 0 OPTO Optical window 1 NOPBUR allow user defined areas without any buried layer doping 1 METAL3 Triple metal 2 THKMET Thick third metal 2 PIMIDE Polyimide 1 LIGHTSLD Light shield 1 XHB06 ADDITIONAL MASK COUNT FOR MODULE COMBINATION Module When combines with s Combined additional mask count SCHOTTKY HRBASE * 1 SCHOTTKY HRPOLY * 1 SCHOTTKY HRBASE + HRPOLY * 1 XHB06 RESTRICTION FOR MODULE COMBINATIONS Module name NPN HVNPN CAPPOLY HRPOLY MIM SCHOTTKY EPROM OPTO METAL3 THKMET PIMIDE LIGHTSLD Use of the also requires use of the following (s) HRBASE, POLY2 NPN POLY2 POLY2 Use of the is not available with the use of the following (s) SCHOTTKY MIM OPTO, THKMET EPROM, THKMET THKMET EPROM, OPTO, METALS3, LIGHTSLD LIGHTSLD THKMET, PIMIDE 5

6 Active s XHB06 UNIPOLAR TRANSISTORS Available with VT IDS [µa/µm] BVDS RDSON [kω.µm] RDSON*A [mω.mm 2 ] Max. VDS Max. VGS 5V NMOS nmos4 CORE V PMOS pmos4 CORE V isolated NMOS nmosi CORE V natural PMOS pnat CORE V ESD NMOS * nesd ESD V isolated ESD NMOS * nesdi ESD V NMOS nh CORE V sym. NMOS nhh CORE V PMOS ph CORE V PMOS pha CORE V PMOS phb CORE V sym. PMOS phh CORE V n-dmos ndha CORE V n-dmos ndhb CORE V depletion NMOS 30V depletion NMOS 20V depletion N-DMOS nd DEPL nhd DEPL ndhdb DEPL * Typical value for onset voltage of avalanche effect (active transistor 1.0µm) = 6.5V. XHB06 BIPOLAR TRANSISTORS Available with BETA VBE [mv] VA BVCEO Ft. [GHz] max. VCE Lateral PNP qpd CORE Lateral PNP qpe CORE Lateral HV PNP qpha CORE Vertical NPN in Nwell qnva CORE > Vertical NPN in Nwell 2) qnbij *) NPN Vertical NPN in n-epi 2) qnbij *) x NPN Vertical HV NPN in n-epi 2) qnhbij *) NPN Vertical HV NPN in n-epi 2) qnhb2h HVNPN *) "ij" stands for different layouts with special application benefits 2) Parameters for different layouts might differ, please refer to process specification manual for details. 6

7 Active s (Continued) NPN PRIMITIVE DEVICES & SPECIAL APPLICATION BENEFITS (SELECTED EXAMPLES ONLY) Group Layout Characteristic Application Benefit qnva C/B/E/C (ring collector) length variable = µm analog, available in CORE qnb1 C/E/B length variable = µm minimum size, minimum junction capacitance qnb2 C/B/E/B length variable = µm medium size, reduced base resistance qnb2me/mf predefined layout vertical NPN improved matching behaviour qnb3 qnb4/sa C/B/E/B/E/B/C length variable = µm C/B/E/B/E/B/E/B/C length from 25 to 250 in fixed steps low base resistance, higher current drive very large transistor, high current drive, low base resistance, capacitances minimized qnbro ring transistor fixed layout very good matching behaviour qnb2x qnhb1ma/mb qnhb2a qnhb2h qnhb3a C/B/E/B/C (ring collector) length variable = µm C/E/B/C (ring collector) predifined layout vertical HV NPN C/B/E/B/C (ring collector) length variable = µm C/B/E/B/C (ring collector) length variable = µm C/B/E/B/E/B/C (ring collector) length variable = µm high linearity small size, minimum parasitics extended operating conditions, high current capability extended operating conditions, high current capability suitable for switching applications extended operating conditions, high current capability, larger emitter size per transistor Passive s XHB06 VARACTORS 2V 100kHz [ff/μm] 1GHz [pf] Max VCC Varicap diode dvc VARDIO 42, kHz [ff] 100kHz [ff] Max Vcc MOS varactor mosvc CORE XHB06 DIFFUSION DIODES Area Cap. [ff/µm 2 ] Sidewall Cap.[fF/µm] BV N+ diffusion / P-well dn CORE P+ diffusion / N-well dp CORE N-well / P-sub dnw CORE HV N-well / P-sub dnwh CORE P-well / NBUR / N-well dpw3 CORE P-well low / NBUR / N-well dpwl CORE Isolated N+ diffusion / P-well dni CORE Emitter / Base diffusion de NPN

8 Passive s (Continued) XHB06 RESISTORS AND CONDUCTORS RS [Ω/ ] Thickness/junc. depth [µm] Max. current denisty [ma/µm] Max VTB rpoly1/ rpoly1c * CORE Poly Silicon rpolyh/ rpolyh * HRPOLY rpoly2/ rpoly2c * POLY Diffusion rdiffn3 CORE rdiffp3 CORE Well rnwell3 CORE rpbase HRBASE Base rxbase HRBASE rxebase NPN rm1 CORE Metal rm2 CORE METAL3/THKMET rm3 METAL rm3l THKMET * These devices are variants of the corresponding basic device with underlying NWELL. The models realize an improved description of parasitics. XHB06 INDUCTORS (SELECTED EXAMPLES ONLY) No. of turns METL width [µm] METL space [µm] outer diameter [µm] L09A THKMET L09B THKMET Spiral Inductors L09C THKMET L24A THKMET L24B THKMET L24C THKMET * Q-factor and inductance see diagrams. The following data are for information only. XHB06 CAPACITORS Area Cap [ff/µm²] Peri Cap [ff/µm] V Coeff. [1/V] BV max. VCC POLY1-MET1-MET2 sandwich csandwt CORE SINKER-POLY1-POLY2 sandwich csandws CAPPOLY POLY1-POLY2 cpoly cpolyc * CAPPOLY SINKER-POLY1 ccsink CORE High-voltage POLY1-POLY2 METAL-ISOLATOR-METAL cpolyh cpolyhc * POLY cmim cmimc * MIM * devices variants with underlying NWELL with identical parameters but realized an improved description of parasitics. 8

9 Passive s (Continued) XHB06 SPECIAL DIODES Forward Voltage BV ILeakage Vref=10V Forward 0.6V [µa] Scalable Schottky dsa SCHOTTKY dsb SCHOTTKY < * Fixed width (W), stretchable length (L). 2.4µm x 2.4µm. Non-Volatile-Memory XHB06 POLY FUSE Unprog. Res. [Ω] Prog. Res. [MΩ] Prog. Max Vread Unprog. Max Vread Poly fuse pfuse CORE 250 > XHB06 ZENER ZAP Zener 50 µa Max lread [ma] Max Zapped Voltage Zener Zap dzap CORE XHB06 EPROM EPROM blocks with memory sizes up to 4kbytes (4k x 8) are available on request. STANDARD CELLS LIBRARIES XHB06 LOGIC LIBRARY Library feature Voltage range Application benefits D_CELLSL Low Power 5.0V Min. area, min. power consumption D_CELLS_B Low Power, Low Noise 5.0V Low noise, min. power consumption D_CELLSL_JI Low Power, Junction Isolated 5.0V Min. noise, min power consumption, junction isolated I/O LIBRARIES XHB06 I/O CELLS LIBRARY Library Feature * V CORE * V IO ESD Level Application benefits IO_CELLS Standard, V CORE =V IO single supply voltage 5.0V 5.0V 2kV HBM Pad limited IO_CELLS_F Standard, V CORE =V IO single supply voltage 5.0V 5.0V 2kV HBM Core limited IO_CELLS_E ESD, V CORE =V IO single supply voltage 5.0V 5.0V 2-4kV HBM Pad limited IO_CELLS_FE ESD, V CORE =V IO single supply voltage 5.0V 5.0V 2-4kV HBM Core limited * Please refer to the library databook for details about available PVT ranges 9

10 EXAMPLES FOR MEASURED AND MODELED PARAMETER CHARACTERISTICS Output characteristics of HV NDMOS (ndhb) for a typical wafer W/L = 20/10, VGS = 2.0, 2.5, 3.0, 3.5, 4.0, 4.5, 5.0V, + = measured, solid line = BSIM3V3 model Current gain of vertical HV NPN bipolar transistor qnhb2a Emitter length 20 µm, VCE = 1.0, 6.0, 11.0V, + = measured, solid line = SPICE model L09C: Q 8 20 L09B: Q Quality Factor Q 6 4 L09A: L L09A: Q Inductance L in nh L09B: L 2 L09C: L ,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 Frequencyfin GHz Ft/Fmax vs. Ic plot of vertical HV NPN transistor qnhb2a Emitter length 12 µm, VCE = 1.0, 8.0V, dotted line = measured values, + = fmax, = ft s: L09A, L09B, L09C measured inductance characteristic and quality factor characteristic vs. frequency of a typical wafer 400 (C(V)-C(0V))/C(0V) [ppm] Diode dsa: current & substrate current vs. forward voltage for typical wafer. W/L = 2.4/2.4, 2.4/50, + = Ia (measured), = Isub (measured), solid line = SPICE model V Linearity characteristics of cpolyh for a typical wafer + = measured, solid line = SPICE model 10

11 XHB06 SUPPORTED EDA TOOLS Synthesis Frontend Design Environment Digital Simulation Timing, Power, Signal-Integrity Analysis Mixed-Signal- Simulators Analog Simulators Mixed Signal Environment Floorplanning, Place & Route Layout / Chip assembly drawing Verification & SignOff Tape Out / GDSII Note: Diagram shows overview of reference flow at X-FAB. Detailed information of suported EDA tools for major vendors like Cadence, Mentor and Synopsys can be found on X-FAB s online technical information center X-TIC. X-FAB'S IC DEVELOPMENT KIT "THEKIT" The X-FAB IC Development Kit is a complete solution for easy access to X-FAB technologies. TheKit is the best interface between standard CAE tools and X-FAB s processes and libraries. TheKit is available in two versions, the Master Kit and the Master Kit Plus. Both versions contain documentation, a set of software programs and utilities, digital and I/O libraries which contain full front-end and back-end information for the development of digital, analog and mixed signal circuits. Tutorials and application notes are included as well. The Master Kit Plus additionally provides a set of general purpose analog functions mentioned in section Analog Library Cells and is subject to a particular license. CONTACT Marketing & Sales Headquarters X-FAB Semiconductor Foundries AG Haarbergstr. 67, Erfurt, Germany Tel.: Fax: info@xfab.com Web: Technology & Design Support hotline@xfab.com Silicon Foundry Services sifo@xfab.com DISCLAIMER Products sold by X-FAB are covered by the warranty provisions appearing in its Term of Sale. X-FAB makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. X-FAB reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with X-FAB for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as medical life-support or life-sustaining equipment are specifically not recommended without additional processing by X-FAB for each application. The information furnished by X-FAB is believed to be correct and accurate. However, X-FAB shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interrupt of business or indirect, special incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of X-FAB s rendering of technical or other services by X-FAB Semiconductor Foundries AG. All rights reserved. 11