The Ohio State University EE Senior Design (I)

Transcription

1 VLSI Scarlet Letters Design Report Report Due Date: Tuesday November 15 th 2005 The Ohio State University EE Senior Design (I) VLSI Scarlet Letters Team Members: -David W. Adams II -Steve Jocke -Joseph Ryan -Ryan Bogadi -Kristoffer Schacker

2 1. Executive Summary 1.1 Introduction Very Large Scale Integration, (VLSI), Design is essential in today s high-tech world. From our television remotes, to supercomputer, and even items as simple as the Glade Wisp Air Freshener, displayed in class, all have IC s. With the consumers expecting products of this quality we, as electrical engineers, must learn VLSI and design in such a fashion Purpose The VLSI Scarlet Letters are tasked with creating digital cells to add to The Ohio State University Digital Cell Library. Our goal is to create a diverse set of digital cells to add to the current library. As of now the library is quite minimal, when we are done we plan to have a more robust library Problem Statement At the beginning of the project many of the group members were unfamiliar with VLSI Design and Cadence, our computer aided design tool. We had to learn the tools of the trade, including: CMOS network structures, Transistor sizing issues, and the Cadence design tool Scope Our scope is to have six cells laid out in Cadence with some initial simulation results. We plan to test our designs further in EE683 and eventually have EE582 Autumn Tuesday, November 15, 2005

3 the chip fabricated by MOSIS. After chip fabrication, testing will possibly come as a research opportunity in latter EE classes. 1.2 Background Research Our group performed research in various aspects. Much time was spent in the Cadence environment learning the software, and working to layout transistor level schematics. Also we learned about Complementary MOS (CMOS) networks, and how to implement logic function. 1.3 Additional Design Requirements Analysis Content An additional design requirement we are considering is taking into consideration the overall system hierarchy when creating a VLSI Design. We discuss how a user can write hardware description language (HDL) in order generate a physical layout of gates, on a single silicon wafer. This is done through the HDL code, a complier, and the digital cell library, all to create the physical layout of the IC. 1.4 Design Approach Our design approach was straight forward. We first analyzed the cell to be designed. Once we knew the logic function to be performed, we used Karnaugh maps to minimize the function. Using our knowledge of CMOS networks we built the pull-up & pull-down networks, and then placed this into Cadence. Once in Cadence, this tool gave us the ability to simulate our designs in great detail. 1.5 Statement of Work In 582 we planned to have transistor level schematic laid out in Cadence with initial simulations. In 683 we plan to continue testing these cells and noting cause and EE582 Autumn Tuesday, November 15, 2005

4 effect relationships. Also we plan to send perform physical cell layouts, and sending these designs to MOSIS for production. Beyond this we assume there will be opportunities to test these cells in later classes. 1.6 Resources For this project, we did not need to purchase anything. All materials we supplied by the university, and their computing labs. All costs involved were man hours associated with research and development. 1.7 Design Review Strategy During design we had to follow requirements connected to the 0.6 [um] fabrication processes. The group followed the CMOS design strategies found in chapter 10 of the EE323 book. Also we designed for proper length and with ratios associated with transistor sizing. Cadence played the biggest part in our design; this tool enabled on the fly testing and ease of simulation with out going to many hand calculations. EE582 Autumn Tuesday, November 15, 2005

5 2. References 2.1 Table of Contents 1. Executive Summary Introduction Purpose Problem Statement Scope Background Research Additional Design Requirements Analysis Content Design Approach Statement of Work Resources Design Review Strategy References Table of Contents List of Figures Introduction Purpose Problem Statement Scope Background Research Additional Requirements Analysis Content & Specifications Design Approach System Design Some Detail Design Analysis and Evaluation Statement of Work tasks: tasks: Beyond 683 tasks: EE582 Autumn Tuesday, November 15, 2005

6 8. Resources Personnel...23 David W. Adams II Steve Jocke Kristoffer Schacker Joseph Ryan Benjamin Carter Ryan Bogadi Facilities & Equipment Schedule and Costs Design Review Strategy Appendix A...33 Appendix B...35 Appendix C...37 Appendix D...39 Appendix E Appendix F EE582 Autumn Tuesday, November 15, 2005

7 2.2 List of Figures Figure 1 - HDL to Layout Flow Figure 2 - K-map for Digital Cell SCG Figure 3 - Cell Design Process Figure 4 - SCG-9 Non-Symmetric Cell Figure 5 - Symmetric Gate Level Schematic Figure 6 - Transistor Layout Process Figure 7 - SCG-9 Transistor Level Layout Figure 8 - Simulation Setup Process Figure 9 - Stimuli Setup, Settings for C input Figure 10 - Fully Configured Analog Design Environment Figure 11 - SCG-9 Transient Response Figure 12 - Resources and Associated Costs Figure 13 -CMOS NAND gate, sizes relative to minimum W/L of 1.5 [um] / 0.6 [um] EE582 Autumn Tuesday, November 15, 2005

8 3. Introduction Today, the designs of integrated circuits are very complex; containing thousands of transistors in a single silicon wafer. In order to make the process of designing Very Large Scale Integrated (VLSI) circuits easier, engineers are using computer software programs. These programs allow the designer to describe the behavior of the circuit initially using an HDL (hardware description language). Once the behavior has been described, another computer program converts the HDL into a gate-level design. In order to do this the converting program needs certain tools. These tools are predefined and tested units called cells. These cells form the basis for all the gate logic used in digital design. Gates such as inverters, NAND s, and OR s are all described by these cells. These cells consist of transistors that have been configured in such a way so that they perform a particular desired task. For example, a cell that functions as an inverter is configured so that if the input voltage to the cell is high, the output voltage will be low and vice versa. 3.1 Purpose Currently, OSU has its own library of cells; however, the library is incomplete. The task of the VLSI Scarlet Letters is to design and test new cells that can later be added to the OSU cell library. This will allow more versatility for future designs as well as making the current library more robust. Our mission is to create high quality cells that are comparable to others that could be bought off the market or other universities are designing. Our team will be designing a total of six new cells. These are illustrated in Appendices A through F. Each design is shown with a gate level schematic, a truth table, and a transistor level schematic. Also we have chosen to describe one cell and its simulation in great detail throughout Section 6. EE582 Autumn Tuesday, November 15, 2005

9 3.2 Problem Statement To accomplish these designs, a software tool called Cadence will be largely used. With Cadence, we will be able to map out transistors on a schematic level. After this has been completed, Cadence will also allow us to run simulations on the behavior of the configuration. This way we can determine if our design functions in the manner in which it was intended. The final step in the process will be to transform the functioning transistor schematic into a cell layout. The cell layout shows how the design should be placed on silicon along with all the metal connection that will be required. Once the new cells have been designed and tested to function accurately, the design will be sent to company called MOSIS, who will fabricate these cells into chips. The chips will then be sent back to OSU, where they will receive their final testing. The team was provided with six logic gates and Boolean equations, four of which were symmetric designs while two were non-symmetric. From these, we were required to design the transistor-level schematics using Metal Oxide Silicon Field Effect Transistors (MOSFET). We used the complementary MOS (CMOS) design, which involves both P-channel Metal Oxide Silicon (PMOS) transistors and N- channel Metal Oxide Silicon (NMOS) transistors. These different types of transistors work inversely to each other: the PMOS transistors create AND gates when in parallel, while two NMOS transistors in parallel translate to an OR gate. The PMOS transistors are implemented above the NMOS, directly below the V dd voltage source. This is referred to as the pull-down effect. The NMOS transistors lie EE582 Autumn Tuesday, November 15, 2005

10 directly above ground, using the pull-up effect. This is more clearly illustrated in the transistor schematics located in the various appendices. 3.3 Scope Our aim, as a group, is to have these designs simulated and have the data plotted in Matlab by the end of ECE 683. The option of plotting data in Matlab will allow more versatility in the representation of the graphs, also allowing better comparisons with other designs and simulations. As we at this moment know the plots that Cadence produces are hard to read due to their elected color schemes. With our designs tested, we will have the necessary data to optimize the designs and have them fabricated. One simulation is detailed for one cell in section 6 of this report. In the following 683 class, we anticipate having the rest of the designs thoroughly simulated and optimized. At this point we will them be ready for ready for chip fabrication. Upon MOSIS fabrication the chip for the VLSI Scarlet Letter, we can then explore testing opportunities in further ECE classes. 4. Background Research In order to understand the VLSI Cell Libraries project more fully, the VLSI Scarlet Letters did background research on many aspects of VLSI design. Most of the design work for the project is done in Cadence. Since some group members had never used it before, the team made an effort to get them familiar with the software. Each member set up Cadence under their accounts using the NCSU AMI 0.6 [um] design library, and ensured it was working by making a blank schematic using the Cadence Virtuoso schematic editor. Once Cadence was properly running, each team member went through the University of Virginia EE582 Autumn Tuesday, November 15, 2005

11 Cadence tutorials in order to become proficient at implementing and testing a design. The designs required some education in basic CMOS planning, because the transistor layouts are not as straightforward and level based, like the logic gate schematics. A tutorial was provided by our senior VLSI design team member, which allowed each of us to become more proficient in transistor layout design. Once the team was educated on this, as well becoming familiarized with Cadence, the design aspect of the project became more elementary. Since the project was to extend a Cell Library with additional components, it was important to become familiar with Cell Libraries. Cell Libraries are collections of cells, which are reusable logic components that are designed to easily fit into another circuit. Cells are similar to functions in computer programming. Examples of cells are logic gates, flip-flops, counters, registers, and other common digital components. The advantage of using cells is that they are already designed and tested, allowing a circuit designer to produce circuits more quickly and accurately. Finally, since the cell libraries will eventually be fabricated onto a chip in ECE 683, the team felt that it was important to research the production process. The chip will eventually be fabricated by a group called MOSIS. In order to fabricate a chip, MOSIS needs the circuit to be presented as a circuit layout, and not as a circuit schematic. Circuit layouts are a representation of the circuit as it will actually be fabricated. This means that transistors are drawn as their actual physical representation (as a series of wells and depletion regions), and wire must be drawn and routed. Wire and depletion EE582 Autumn Tuesday, November 15, 2005

12 regions are represented as a series of boxes. MOSIS has very specific rules on how close these boxes may be drawn to each other in order to ensure the circuit will work correctly. Circuit layouts are created in Cadence using the Virtuoso Layout tool. 5. Additional Requirements Analysis Content & Specifications To define the behavior of a circuit, engineers typically start off by using a hardware description language. Once the description has been written, a compiler is used to synthesize gate-level logic of the circuit. A netlist is used by the compiler to accomplish this task. A netlist is nothing more than a description of connectivity for electrical designs. The netlist uses the cells, which have inputs and outputs, and connects them with other cells in the manner that meets the description created in the HDL. A cell can be compared to a customized block that implements common logic functions. Several of these blocks can then be connected in a variety of combinations to produce larger and more complex designs. What makes cells so appealing is that they can be placed down on a chip and connected a lot easier than any other method currently known. Also, cells usually have high transistor densities and good speed and power characteristics. Therefore, having a wide variety of different cells in a library allows not only more versatility in designing a circuit, but increases the probability that complex circuit will have the ability to be created from an HDL. Placing the cells down and routing (connecting with wires) can be accomplished by hand or automatically through Cadence. Typically doing them by hand yields a more efficient EE582 Autumn Tuesday, November 15, 2005

13 circuit, but it also consumes more of a designer s time. The ultimate goal in the design process is to create a layout of the cells. A layout can be compared to the drafts that an architect creates. From these drawings, a physical model can be created. Figure 5.1 on the next page shows the basic design flow from a hardware description to the layout. Figure 1 - HDL to Layout Flow 6. Design Approach 6.1 System Design The cells that we have designed consisted of several gates such as AND s and OR s. One method for designing our cells was to simply take the transistor configuration of one logic gate and link it up to another transistor configuration of another logic gate. The problem with this approach is that one cell would end up being comprised by a lot of transistors. For example, both AND s and OR s gates are made up of six transistors. If a cell uses just three of these gates to accomplish EE582 Autumn Tuesday, November 15, 2005

14 a function, then the cell would require 18 transistors. We decided that a better approach was needed. We first began our design process by taking the truth tables for each of our cells and creating Karnaugh maps. From there we were able to determine if the circuit could be simplified. One of the goals we had was to design the cells with as few transistors as possible. By doing this we could improve the efficiency of each cell. Typically the smaller something is, the better it performs. From the K-maps, shown in Figure 2, we were able to draw the transistor layouts by hand. Figure 2 - K-map for Digital Cell SCG-9 The next part of the design process was to use Cadence to layout our transistor configurations. The Cadence program contains a schematic editor that acts like a computer aided drafting program for electronic circuits. We placed NMOS and PMOS transistors on out simulator, and then connected them to the inputs, output, ground, and power through wires. Once the schematic was created, Cadence also EE582 Autumn Tuesday, November 15, 2005

15 allowed us to run a simulation on each of the designs. The simulations produced graphs showing the input voltages and how they should affect the output voltage. Figure 3, shown below, gives an overview of how we accomplished our design process. Figure 3 - Cell Design Process In the next section we will discuss one of our cell designs in more detail. Even though our group created 6 individual cell designs, there are a lot of similarities among them. Therefore, we will limit our detailed discussion to just one of our cells. Then, in the section that follows, we will discuss the analysis and evaluation for all our cell designs. 6.2 Some Detail Design Below, in Figure 4, contains the cell SCG9 a nonsymmetrical cell which we have designed. Figure 4 - SCG-9 Non-Symmetric Cell EE582 Autumn Tuesday, November 15, 2005

16 Unlike most of the other cells that our group has designed, SCG-9 is special because it is Non-Symmetrical. Since this cell is Non-Symmetrical it causes a number of issues of which timing issues will be our concern. The two logic paths A and B must go through and AND gate before finally being OR ed together with C. This causes an issue because if the cell is clocked at the time of which path C is AND ed together with the resultant of the previous gate level it will produce an error. This error is the resultant of the gate delay from logic paths A and B. There are two solutions available to remedy this problem: 1. Insert proper amount of inverters to add delay to path C 2. Change the nonsymmetrical design to a symmetric one. In this case we chose to implement a symmetrical design because it resolves the timing issues while keeping the design process simplified. Additionally, the insertion of inverters would increase the transistor count. Also, this makes the timing at the first gate level exact at the second level. If we were to use inverters it would cause the signal to get there either before gate level 1 completed or just after it. Below, in Figure 5, is the symmetrically designed gate level schematic of SCG-9. Figure 5 - Symmetric Gate Level Schematic EE582 Autumn Tuesday, November 15, 2005

17 Now, having a symmetrical design, we can continue to the transistor layout stage in order to utilize our CAD tool. To map the logic equations to transistors we use two basic rules: 1. Connect Transistors in series for AND function 2. Connect Transistors in parallel for OR function Below, in Figure 6, we detail design flow used when creating the transistor level layout, using the two basic rules formed above. Figure 6 - Transistor Layout Process The pull down network is composed of all NMOS transistors while the pull up network is composed of PMOS transistors. Transistor sizing was done 2 to 1 and 1 to 1 ratio, PMOS to NMOS respectively. Also, the circuit is viewed in the worst case scenario. The worse case scenario sets transistor sizing, such that the current could flow through without resistance if only one transistor was turned on in the current path. In SCG-9 there is an inverter at the end of the function because the center tapped line is the inverse of the function we want. Figure 7 is a final layout of the function in detailed transistor level implementation. Having the transistor layout completed in Cadence allows for the circuit to be simulated, while accurately estimating the cell s performance. EE582 Autumn Tuesday, November 15, 2005

18 Figure 7 - SCG-9 Transistor Level Layout 6.3 Analysis and Evaluation The Cadence Analog Environment tool allows for simulation to check that the newly created transistor layout works according to the Boolean expression. Figure 8 shows the overview of the analysis setup. EE582 Autumn Tuesday, November 15, 2005

19 Figure 8 - Simulation Setup Process In our example cell, SCG-9, we chose the inputs to be high, low, and pulse which respectively goes to the variables A, B and C. Using the stimuli section of the analog Environment we can tailor each input as we choose. Stimuli setup has two types, one being the input and the other being global sources. Global sources menu specifies ground levels and V dd level voltages. The inputs section allow for a variety of signals to be used, such as pulse waves, sine waves, and DC. Below in Figure 9 shows a sample window of input C being setup as a pulse input. Having the input setup we move on to simulation selection. To test the SCG-9 function we used a transient analysis. This provides us with information about how the cell responds to input C changing timing wise. EE582 Autumn Tuesday, November 15, 2005

20 Figure 9 - Stimuli Setup, Settings for C input The final phase of the process is to select the variables which need to be plotted. Within the Analog Environment window the Output menu can be selected. From there, there is a number of different ways of choosing which outputs are saved or also plotted. Typically the easiest way is to choose select on schematic and click on them within the schematic. Finishing this completes the setup phase which is shown in Figure 10. EE582 Autumn Tuesday, November 15, 2005

21 Figure 10 - Fully Configured Analog Design Environment Running the simulation will result in Figure 11, which will be the focus of this last section. Using the original function we can verify that our cell is outputting the correct results. From the setup previous to this we would expect the output of our cell to follow the pulse on C which is verified below. Also there is a slight delay of 0.3 [ns] which is expected. The cell will have some lag in accordance to the input. The timing results shown below are actually not realistic because this simulation was ran with no load on the output. To get proper loading characteristics we would have to put a NAND gate at the output of our cell. By the time we produce the final report, will have simulations for SCG-9 that includes loading characteristics produces from the NAND gate interconnections. We will then be able to compare and contrast the results. EE582 Autumn Tuesday, November 15, 2005

22 Figure 11 - SCG-9 Transient Response EE582 Autumn Tuesday, November 15, 2005

23 7. Statement of Work tasks: All of our design work for 582 will be done in Cadence. We will first familiarize ourselves with the Cadence environment, and then develop our skills by working through a set of Cadence tutorials. When the specific cells are assigned, we will develop transistor-level schematics for each cell. We will then use Cadence to simulate these cells to ensure their functionality and efficiency. Following 582, we will all take 683 either winter or spring quarter tasks: Our first step in 683 will be to develop transistor-level layouts of the cells that we have designed. We will try to optimize for both area and speed when laying out the transistors. When we have sufficiently simulated our layouts and are satisfied with our results, we will send the chips to MOSIS to be fabricated. Depending on when we get the fabricated chips back from MOSIS, we will either begin to physically test the chips during 683 or possibly after our completion of Beyond 683 tasks: The only design work left to be completed after 683 would be to test the chips in a real environment (rather than a Cadence simulation). If the tests show that our cells work as well as they possibly could, then the cells should be added to the OSU cell library. EE582 Autumn Tuesday, November 15, 2005

24 8. Resources Since this project did not require us to do any physical design, we were able to design our cells with very few resources. In developing our solution, we dealt mostly with software packages and personnel. 8.1 Personnel All VLSI Scarlet Letters team members were responsible for their own cell design and simulation. This consisted of designing the transistor level schematic from the logic functions we were required to design for the client. All members setup their own Cadence environment on the engineering region 4 (ER4) UNIX computer accounts. Also each group member, at various levels of detail, advanced through the recommended Cadence tutorials. We each contributed to the team in our own unique manner. Below is a listing of the specific tasks each member performed. David W. Adams II Dave has contributed as a group leader and as the contact entity for our client. He has created a List Serve mailing address for effective group communication. Also Mr. Adams will be researching the output files generated by Cadence and determining the feasibility for Matlab plotting routines. Dave has also been responsible for turning in all group assignments and merging all documents produced by the VLSI Scarlet Letters. Dave was responsible for designing, laying out, and simulating digital cell SCG-4. EE582 Autumn Tuesday, November 15, 2005

25 Steve Jocke Steve is responsible for Cadence administration, and supporting other members in digital cell design. Cadence administration tasks range from simulation Analog Environment Setups along with setting up Cadence to be ran remotely from home (i.e. PC s located off campus through XWin32). Mr. Jocke is responsible for the design and simulation of cell SCG-9. He has also prepared and edited Sections 6.2 & 6.3 of the final design report. Steve has also supported Chip Off the Old Block in Cadence cell design and simulations thought the past weeks. Kristoffer Schacker Kris has contributed to the group by providing various background research activities, such as reading the Copus paper thoroughly. In addition, he was responsible for the design and simulation of the SCG-4 cell. He also helped by writing the introduction for the initial proposal and a portion of the design approach for the final report. Kris also fostered development with other group members Joseph Ryan Joe has contributed by researching and developing the design and testing processes used by each group member when implementing their cells. Also Joe has been a big help in getting all members up to speed on VLSI design. Mr. Ryan has also contributed by creating the design and simulation for cell block SG12. Joe supported the overall design progression from a technical point of view. Benjamin Carter Benjamin has researched the Cadence environment by setting up an account and completing the tutorials which explain the Cadence tools, MOS IV curves, schematic capture and inverter VTC. Ben has also researched on the internet and in various textbooks in terms of VLSI design and the CMOS transistor EE582 Autumn Tuesday, November 15, 2005

26 layout. He contributed to the writing of the paper, mainly in the Introduction, Background Research, Resources, Facilities, and Appendix sections. Ben also designed the SCG-5 transistor layout and was responsible for organizing and presenting the team s schedule and goals for the future. Ryan Bogadi Ryan designed the cell SGC-10. He also contributed to the writing of each of the group s writing assignments. 8.2 Facilities & Equipment Following is a table, Figure 12, that lists the facilities and equipment that we utilized for our design process, as well as the cost associated with each: Facilities & Equipment Quantity Cost Computer Lab (DL 557 UNIX Lab) 1 Free Computer Lab (Caldwell 260) 1 Free Copus Thesis 1 Free Bayer Thesis 1 Free VLSI Design Book N/A Free (Internet Chapters) Cadence Software N/A Free Cadence Tutorials N/A Free Figure 12 - Resources and Associated Costs Our final cost for this project was essentially nothing, since we required nothing more than these facilities and equipment. The only design costs will be incurred when the designs are sent for fabrication during 683. However this cost will be minimal because MOSIS is funded by the government for university chip manufacturing. EE582 Autumn Tuesday, November 15, 2005

27 Our greatest resource in this project is our customer, Brian Dupaix. He also happens to be the teaching assistant for this course. Brian is the one for whom we are designing this solution, and he is the one who instructs us on any project criteria. Whenever we have questions regarding specifications of this project, he is the one that we turn to. In addition, we have the course instructor, Professor Steve Bibyk to consult regarding any VLSI design issues. 9. Schedule and Costs Following is a week-by-week look at the tasks we were starting and finishing. This should give you a good idea of the pace at which we were working, which should, in turn, give a good indication of how much more time we should need to complete the project. Week 1: - Tasks started / In progress o Team forming assignment - Tasks completed o Team Formation Week 2: - Tasks started / In progress Formed based on course instructors examination of students interests & past coursework o Meet project supervisor (Brian Dupaix) o Problem statement o VLSI design research EE582 Autumn Tuesday, November 15, 2005

28 - Tasks completed o Project assignment Week 3: - Tasks started/ In progress o Set up Cadence environments o OSU cell library research o VLSI design research - Tasks completed o Problem statement Week 4: - Tasks started / In progress o Customer interview of project supervisor o Cadence tutorials o OSU cell library research - Tasks completed o Cadence setup and testing Work with an existing schematic to make sure our environment is operational Week 5: - Tasks started / In progress o Requirements analysis o Cadence tutorials o Prepare status review presentation o Proposal - Tasks completed EE582 Autumn Tuesday, November 15, 2005

29 o Refine problem statement to help with project requirements analysis Week 6: - Tasks started / In progress o Look into possible cell assignments Cells that are currently absent from the OSU digital cell library - Tasks completed o Status review presentation o Cadence tutorials o Proposal Week 7: - Tasks started / In progress o Specific cell assignments from Brian Dupaix o Individual cell designs - Tasks completed Transistor level schematic o All background research necessary to begin cell design Week 8: - Tasks started / In progress o Individual cell designs Transistor level schematic o Cell simulations in Cadence o Prepare for final group presentation - Tasks completed EE582 Autumn Tuesday, November 15, 2005

30 o Discussed each of our individual cells as a group to make sure that we all understand how to proceed with design Week 9: - Tasks started / In progress o Cell simulations in Cadence o Begin working on final report o Cell optimization to minimize number of transistors - Tasks completed o Individual cell designs Transistor Level Schematics o Final group presentation Week 10: - Tasks started / In progress o Continue working on final report o Cell optimization to minimize delays - Tasks completed Maximize Speed & Minimize Area o Cell simulations Week 11: - Tasks started / In progress o TBD (To Be Determined) - Tasks completed o Final report EE582 Autumn Tuesday, November 15, 2005

31 10. Design Review Strategy Each cell was designed using a straight forward process. Since each cell was described by a VHDL logic function, they were implemented using pull-up and pull-down CMOS (complementary MOS) networks. CMOS networks are a technique to directly map a logic function to a complementary layout of P-type and N-type MOS transistors. A CMOS network will implement the inverse of a logic function, and so a CMOS network followed by an inverter is generally used to implement the logic function. To better describe a CMOS Network, please refer to the Figure 13 and the discussion which follows. Figure 13 -CMOS NAND gate, sizes relative to minimum W/L of 1.5 [um] / 0.6 [um] CMOS networks are made up of two elements: a pull-down network (made of NMOS transistors), and a pull-up network (made of PMOS transistors). When the pull-down network is on, it pulls the output down to 0. When the pull-up network is on, it pulls the output up to 1. To implement a pull-down network, the Boolean function is first put into minimized form using a K-Map, and then grouped into terms. Each variable of each term is EE582 Autumn Tuesday, November 15, 2005

32 then assigned to the gate of a transistor, and then the transistors of each term are put into series with each other. For instance, in Figure 13, there is only 1 term; (AB). A and B are each assigned to a transistor, and then put into series. Then, each term is put in parallel. Finally, the pull-up network is designed by complementing the pull-down network, meaning that every transistor that was in series is now in parallel, and every term that was in parallel is now in series. Once the transistor schematic for each cell was defined, they were optimized for speed and area by altering the sizes of each transistor. The sizes of each transistor were minimized to the smallest allowed by the manufacturing process, which is 1.2 [um] for the width and 0.6 [um] for the length. Next, the sizes of some transistors were increased in order to balance the pull-down network and pull-up network currents, thus optimizing the intrinsic speed of each stage. The widths for each PMOS transistor was doubled to account for the fact that the PMOS hole mobility constant is roughly half of that of the NMOS electron mobility constant. Finally, the relative magnitudes of each network were balanced to account for the fact that each network is a complement of each other. For instance, in the NAND gate example, the size of the NMOS transistors needs to be doubled because the two drain currents of the two PMOS transistors add together. After the cells were fully designed, they were entered as a schematic in Cadence, and tested using Cadence's Spectre simulation package. Cadence was used as it is an industry standard CAD tool for designing and simulating transistor circuits. To test, a pulse function was simulated on each input of the cell, and the output was analyzed for correctness. The pulse functions sent into each input were different from each other in EE582 Autumn Tuesday, November 15, 2005

33 order to ensure that the entire truth table of the logic function was covered. In order to ensure that the simulation accurately predicted the performance of the cell in a larger environment, the output of each cell was loaded by a NAND gate during simulations. EE582 Autumn Tuesday, November 15, 2005

34 Appendix A SCG-2: Two 2-ANDs into 2-OR EE582 Autumn Tuesday, November 15, 2005

35 SCG-2 Transistor Level Layout: EE582 Autumn Tuesday, November 15, 2005

36 Appendix B SCG-4: Two (two 2-ANDs into 2-NORs) into 2-NAND EE582 Autumn Tuesday, November 15, 2005

37 SCG-4 Transistor Level Layout: EE582 Autumn Tuesday, November 15, 2005

38 Appendix C SCG-5: Three 2-ANDs into 3-OR EE582 Autumn Tuesday, November 15, 2005

39 SCG-5 Transistor Level Layout: EE582 Autumn Tuesday, November 15, 2005

40 Appendix D SCG-9: 2-OR into 2-AND EE582 Autumn Tuesday, November 15, 2005

41 SCG-9 Transistor Level Layout: EE582 Autumn Tuesday, November 15, 2005

42 Appendix E SCG-10: Two 2-ORs into 2-AND EE582 Autumn Tuesday, November 15, 2005

43 SCG-10 Transistor Level Layout: EE582 Autumn Tuesday, November 15, 2005

44 Appendix F SCG-12: 2-NAND into 2-NOR EE582 Autumn Tuesday, November 15, 2005

45 SCG-12 Transistor Level Layout: EE582 Autumn Tuesday, November 15, 2005