ECEG 350L Electronics I Laboratory Fall 2017

Transcription

1 ECEG 350L Electronics I Laboratory Fall 2017 Introduction Lab #6: CMOS Logic Gates [revised 11/30/2017] Digital circuitry forms the foundation of the modern technical, information-centric world. All digital circuits, from simple combinational logic circuits to sophisticated microprocessors, employ logic gates that perform the basic Boolean functions such as AND, OR, NAND, NOR, etc. All of the basic logic gates are implemented in the major logic families. The CMOS (complementary metal-oxide semiconductor) family is currently the most widely used because of its low power dissipation properties and because of its high density of gates in integrated circuit (IC) chips. In this lab exercise you will analyze the properties of a basic CMOS logic gate using test procedures of your own design, which in turn should help you appreciate some of the important details of the operation of digital logic circuits. Group assignments are listed at the end of this handout. Theoretical Background The most fundamental logic gate in any logic family is the NOT gate, or inverter. The output of a NOT gate is simply the complement of the input. That is, a logical input of 0 yields a logical output of 1, and vice versa. The other types of combinational logic gates, the AND, OR, NAND, NOR, XOR, and XNOR gates, have two or more inputs. For two-input gates with inputs labeled A and B, the following truth table defines the output states for the indicated Boolean operations: Inputs Boolean Operation A B AND NAND OR NOR XOR XNOR In the CMOS logic family, these Boolean operations are implemented on IC chips that contain both p-channel (PMOS) and n-channel (NMOS) MOSFETs. For enhancement-mode NMOS devices in normal operation, the drain current idn, the drain-to-source voltage vdsn, the threshold voltage Vtn, and the transconductance parameter kn = µncoxw/l are all positive quantities. The corresponding quantities for enhancement-mode PMOS devices are negative except for the drain current idp and transconductance parameter kp. Typical i-v characteristics for NMOS and PMOS devices are shown in Figure 1. In normal CMOS gate operation, all NMOS devices in their equilibrium state (i.e., after the input and output voltages have settled to either a logical 0 or 1 representation) have gate-to-source voltages of either 0 V or VDD, and all PMOS devices have gate-to-source voltages of either 0 V or VDD. This implies that the operating point of each device lies along either the upper curve in one of the plots in Figure 1 or along the horizontal axis (which corresponds to the cut-off region). Note that 1 of 7

2 the vgs = VDD curve and the vgs = 0 curve (the horizontal axis) in each plot intersect at the origin. idn NMOS PMOS idp vgsn = VDD vgsp = VDD 0 vgsn = 0 vgsp = vdsn 0 vdsp Figure 1. Graphical representations of the i-v characteristics for n-channel (left) and p-channel (right) MOSFETs. When in the equilibrium state, the transistors in a CMOS gate operate in either the cut-off region or the triode region because the drain current through all of the transistors should be zero. Examination of Figure 1 shows that zero drain current can occur with either vgs = 0 or vgs = VDD. Which region the transistor operates in is determined by the value of vgs. Important issues to consider when designing with CMOS devices and deciding which CMOS technology (i.e., transistor size and fabrication methods) to use are the propagation delay and transition time of a typical gate. Propagation delay indicates how much time elapses between the moment a logical transition occurs at the input of the gate and the response appears at the output. Transition time refers to the duration of the rise time from 0 V to VDD (or fall time from VDD to 0 V) at the output of the gate. Both characteristics are determined by the internal capacitances of the transistors and the stray capacitances in the interconnecting wires and/or circuit board traces. [paragraph revised 11/30/17] A simplified representation of the capacitance charge/discharge process is depicted in Figure 2. Voltage source vds and resistance rds comprise a Thévenin equivalent circuit that represents the output port of the logic gate. In the case of a CMOS inverter, vds and rds are the actual drain-to-source voltage and resistance of a single transistor (whichever one is not cut off during the transition). In a more complicated gate, vds and rds represent a composite output voltage and resistance; that is, they are not associated with a specific transistor but represent the collective behavior of several transistors. Capacitance C represents a combination of the output capacitances of the gate (comprised mainly of the drainto-source capacitances and drain/source-to-substrate capacitances of the logic gate s transistors), the wiring capacitance, and the input capacitance(s) of any following gates (primarily their gateto-source and gate-to-drain capacitances). The voltage vds is either 0 V or VDD, depending on the logical state of the output of the gate. Depending on its value, the capacitance could be charging or discharging at any given time. The rate of charge/discharge is dependent on the time constant determined by the product rdsc. 2 of 7

3 [paragraph revised 11/30/17] Not apparent from Figure 2, however, is that the value of the output resistance rds changes throughout the charge/discharge cycle because the PMOS and NMOS devices in the logic gate move through the cut-off, saturation, and triode regions (or vice versa) during each logical state transition. The effective resistance therefore depends on the region of operation and is highly variable. Some insight into its value can be gained, though, by examining the output resistance after the transistors have settled into their equilibrium states. From that point on, the value of rds does not change until the next logical state transition. rds vds + + vo C Figure 2. Simplified representation of the charging process of the capacitances in a CMOS logic circuit. The output resistance rds of the gate might be due to a single transistor or multiple transistors and changes as the output voltage of the gate transitions from one logical state to the next. The capacitance C is a composite of many device and wiring capacitances. Experimental Procedure You will be given a circuit diagram for a CMOS logic gate that implements an unknown (to you) Boolean operation. Complete the following tasks: Using the NMOS and PMOS i-v characteristics as a guide, complete the truth table for the circuit and determine which Boolean operation (NOT, AND, OR, NAND, NOR, XOR, or XNOR) the circuit implements. Also determine the region of operation of each of the four MOSFETs for each input state (00, 01, 10, and 11). A table has been provided for you to list the various output states and regions of operation. You should discover that determining the operating region of the one of the MOSFETs will be more challenging than for the other three, and you should also discover that it is impossible (at least at this level of understanding) to determine the operating region of one of the MOSFETs for one of the four input combinations. However, you should be able to show in that case that it does not matter what the operating region of that particular MOSFET is in order to predict the overall output state of the gate. Prepare a copy of the CMOS gate circuit diagram with a completed truth/region-of-operation table to submit with your lab documentation. Heed the following warnings for the next step: Do not apply input signals to a CD4007 device until power (VDD) has been applied to the circuit; otherwise, damage to the device could result. 3 of 7

4 Pin 7 (the NMOS substrate) must be connected to ground and pin 14 (the PMOS substrate) must be connected to VDD regardless of the circuit configuration of the IC. You should connect the gates of all of the unused NMOS and PMOS devices to ground or to VDD. Static build-up on the MOSFET gates can cause the devices to switch randomly between states, which in turn can cause current spikes from the power supply and other undesirable effects, including erratic operation in the devices that are being used in the circuit. A bypass capacitor of 1 µf or so (the value is not critical) should be connected in parallel with the power supply as close as possible to the CD4007 device. Confirm your analysis in the preceding step by building the logic gate using a CD4007 integrated circuit (IC) chip and then designing a test procedure to determine the gate s truth table. The power supply voltage for the circuit should be VDD = +10 V. Figure 3 shows the pin-out of the CD4007 chip. Note that the pins in the diagram are not in numerical order, but they are on the actual device. The substrates of the three NMOS devices are connected together at pin 7, and the substrates of the three PMOS devices are connected together at pin 14. One PMOS device and one NMOS device each have their sources connected internally to their respective substrates. The sources of the other transistors must be connected to their respective substrates externally, if the design calls for that. One NMOS-PMOS pair (pins 9-12) is already configured as a CMOS inverter; that is, their gates and drains are connected together internally. You might be able to take advantage of the inverter configuration when you construct your gate circuit. A data sheet for the CD4007 is available via a link on the Laboratory web site. VDD to Pin 14 VSS (ground) to Pin Figure 3. Pin-out of the CD4007 dual complementary pair plus inverter. 4 of 7

5 Devise a reasonably accurate measurement procedure to determine the output resistance of the logic gate for each of the four possible input combinations. Record the results of your measurements for each of the four combinations, and be prepared to explain your procedure. [added 11/30/17] After you have completed the steps above, complete the following with the instructor: o Demonstration of the working logic gate and identification of its type. o Explanation of how the regions of operation of each of the four transistors were determined for two to three of the logical input combinations (00, 01, 10, or 11). Each person in the group will be randomly assigned one of the combinations. o Explanation of the output resistance measurement procedure and summary of the measurement results for each of the four input combinations. Lab Documentation [this section revised 11/30/17] After the lab sessions are over, describe in a single electronic document the procedure that your group developed to determine the output resistance of your assigned logic gate. You do not need to include a fully developed results section, but you should append a completed truth and regionof-operation table. The document does not have to refer to that particular table. Pay particular attention to the issues discussed in the Lab Documentation Formatting Guidelines available at the Laboratory web page. Note that the guidelines have been revised recently. More explicitly, the documentation must include: a. An introductory section that focuses the reader s attention from a broad overview or perspective to the specific topic under discussion. It must prepare the reader for the information that is to be presented in the main body of the text. b. A description of your output resistance measurement procedure and the results you obtained. Provide enough detail so that someone unfamiliar with details of the lab exercise could have a reasonable chance of repeating your results. This means that you do not need to discuss the regions of operation of the MOSFETs or include any of your truth table measurement results. Schematic diagrams (which may be hand-drawn), other figures, and tables (if any) must be properly formatted and captioned, and equations must be professionally formatted and integrated into the text. c. A brief concluding section that brings about a thoughtful and satisfying sense of closure for the reader (who would probably be a manager or supervisor). It should be reflective and include a brief discussion of implications that the reader might miss without your guidance. You should avoid rambling, vague, unsupported, and/or excessively farreaching statements. Your ideas should be at least partly original and drawn from your own lab experience. Do not simply repeat information that has already been given in the course except to elaborate on them in new ways. d. A copy of a completed truth and region-of-operation table for the logic gate assigned to you. Be sure to indicate what type of logic gate the circuit represents. The documentation must be in MS-Word (*.doc or *.docx) format using 11-point or larger font. The file size must be less than 5 MB. Multiple text columns per page may not be used. The total length of the text must not exceed 900 words, but any number of supporting figures, tables, equations, and/or other graphics may be added. Include your group members names, the course 5 of 7

6 number (ECEG 350), the lab session dates (Nov , 2017), the lab meeting time (1 pm or 3 pm), and the lab number on the first page. A cover sheet is not required. Use the file naming convention described on the lab web page. One copy per group must be submitted via the course Moodle site by the deadline posted on the lab web page. The documentation must be thorough, well organized, clear, legible, concise, and professional in tone and style. It must also exhibit good writing mechanics, spelling, and grammar. All equations must be typeset using one of the equation editors available in MS-Word. Figures may be neatly hand-drawn, scanned or photographed, and inserted into the document, but screen images must be captured using software. Minimize the file size by using appropriate camera or scanner settings (e.g., black & white and 300 dpi for scanning). All four margins should be at least one inch. Single line spacing is acceptable. Keep a copy of your documentation if you wish to use it to prepare for the next exam. Lab Scores [this section revised 11/30/17] Each group member will receive the same overall score according to the following criteria. Scores will be quantized at the indicated percentage levels following the rubric posted at the lab web site: 0, 5, 10, 15, and 20% Demo properly working logic gate 0, 5, 10, 15, and 20% Demo output resistance measurement procedure 0, 5, 10, 15, and 20% Demo explanation of regions of operation 0, 5, 10, 15, and 20% Properly completed truth and region-of-operation table 0, 5, 10, 15, and 20% Thorough description of output resistance measurement procedure If the demonstration is completed after the deadline, a 10% score deduction for every 24 hours or portion thereof that it is late will be applied (not including weekend days). No demonstration credit will be given four or more days after the deadline, but credit for the lab documentation can still be obtained. Lab documentation submitted after the deadline will have a 10% score deduction applied for every 24 hours or portion thereof that it is late (not including weekend days), but credit for a successful demonstration (60% maximum) will be recorded regardless of when the documentation is submitted. Group Assignments The randomly generated groups for this lab exercise are listed below. The letter next to your names indicates the logic gate circuit assigned to your group. 1 pm section Chowenhill-Dhuicque-Romeyn (A) Evans-Karki-Kyaw (B) Alves-Bloschichak-Qureshi (A) Strunk-Vehra (B) 6 of 7

7 3 pm section Byanjankar-Schmidt-Yang (A) B.Chen-Ji-Tian (B) Diehl-M.Chen-Nam (A) Awe-Fox-Hubal (B) Agosta-Tchokouani (A) David F. Kelley, Bucknell University, Lewisburg, PA of 7