Power Module Design - The HF in Power Semiconductor Modelling and Design

Transcription

1 Power Module Design - The HF in Power Semiconductor Modelling and Design Keysight Weiterbildung Charakterisierung & Modellierung von Halbleiter-Bauelementen Böblingen, 5. Mai 2015 Ingmar Kallfass Institute of Robust Power Semiconductor Systems University of Stuttgart

2 Id (A) Outline Semiconductor-Based Power Electronics An Introduction Challenges in Power Module Design Power Module Design Flow Modeling and Characterisation Electro-Thermal Co-Simulation GaN Integration: Power Electronic Circuits Vds (V) 2

3 SEMICONDUCTOR-BASED POWER ELECTRONICS AN INTRODUCTION 3

4 Power Electronics A Definition Power Electronics is the extension of solid-state electronics away from handling communications and data and into the business of efficiently handling power, from milliwatts to gigawatts. It makes the mobile phone battery last longer, it makes hybrid cars practicable, and it helps make electrical generation and distribution possible from sources ranging from a solar cell on your roof to a nuclear reactor in mainland Europe. [BIS2011] 4

5 Power Electronics A Definition Power Electronics is (...) an enabling technology that often determines the performance of, and provides the competitive advantage for, much more expensive devices or systems. For example, choosing a mobile phone or lap-top computer for its battery life is actually a Power Electronics decision, with the battery performance itself just one part of that. The importance of Power Electronics to the economy is consequently very much greater than its direct market value. Power Electronics is rarely seen as an end product by the general public, but it does play a critical role in almost all aspects of our daily lives. [BIS2011] 5

6 Power Electronic Applications [Catrene2013] 6

7 Power Semiconductors [Catrene2013] 7

8 FOM Power Semiconductors [Catrene2013] 8

9 SEMICONDUCTOR-BASED POWER ELECTRONICS CHALLENGES IN POWER MODULE DESIGN 9

10 ECPE Technology Roadmap [ECPE] Requirement Key Performance Indicator Goal: Improvement by 2020 by a factor of size power density [kw/l] 2-3 Google/IEEE Little Box Challenge weight power-to-mass ratio [kw/kg] 2 efficiency efficiency [%] 3 cost relative cost [kw/ ] 2-3 robustness failure rate [1/h] 3 10

11 Design Measures I/V ripple high f sw small FOM = R on Q sw high d/dt switching slopes (I G ) high temperature operation of wide bandgap SC LRC resonance (gate and power loops) compact layout / integration density 11

12 Tradeoffs size f sw d/dt high T operation integration density weight efficiency cost robustness EMC Optimum design requires an RF-refined design flow from device characterisation and modelling to multi-domain circuit analysis 12

13 R&D at the ILH Multi-Domain Modeling & Design Characterisation Modeling Design IV CV QV vs T pulsed IV Zth double pulse B1506A Modeling Transistor Package DBC, PCB static dynamic thermal time and frequency domain analysis electro-magnetic co-simulation electro-thermal cosimulation C th,j R th,jc C th,hs R th,hs 13

14 POWER MODULE DESIGN FLOW MODELLING AND CHARACTERISATION Capacitance Model and Inductive Load Switching Dynamic Ron in GaN Self-Heating 14

15 Which (Transistor) Switch Model Complexity? 2 dim. f(v) NQS LF dispersion 1 dim. f(v) Ids/gm gate IV (HEMT) Ron Caps bulk IV (MOSFET) electrothermal RF parasitics (package) accurate, but beware of convergence! 15

16 Dynamic IV for Switching of Inductive Loads I d VDS ID 3 2 Vin IdMAX VG t PLOSS 1 V ds VG V Plateau t cross ON t ON t cross OFF t Q derived from capacitance model 16

17 Dynamic IV for Switching of Inductive Loads Dynamic IV in a FET transistor switch transits from sub-threshold to saturation to linear regime 17

18 Capacitance (pf) Capacitance Measurement DUT: SiC MOSFET 600V, 100mΩ, 35A Ciss Coss Crss B1506A Vgs = 0 V Vds = 0 to 500 V 10 f = 100 khz Vds (V) measurement conditions as defined in datasheets 18

19 Capacitance Trace for Inductive Load Switching datasheet application C gs [ff/0.1mm] C gd [ff/0.1mm] GaAs 0.15µm RF power phemt 19

20 Vgs (V) Qg Measurement B1506A Qg HC Qg HV DUT: Si MOSFET 100V, 11mΩ, 200A Qg (nc) Qg Derived: JESD24-2 standard Ig = 5mA HC meas: Vdsoff=60V Idson=10A HV meas: Vdsoff = 100V 20

21 Capacitance Derived from Gate Charge Factors 21

22 Traps in GaN Devices well known from RF devices drain/gate-lag LF dispersion dynamic R on after OFF-to-ON switching, R on remains high for a period of time trapping time constants from ns to ms or even longer (continuous exposure) [Catrene2013] 22

23 Dynamic Ron Measurement V stress V ds, I d 1 3 I d 3 Meas Meas 2 1 V ds V low V on t stress t delay1 2 t Quiescent total delay Vds_Pulse Vgs_Pulse V ds pulse width V gs pulse width T_delay1 for safety. Minimun value depends on slew rate of drain SMU Very short total_delay necessary for measuring dynamic effects V ds pulse delay V gs pulse delay t 23

24 Id (A) Trapping Effects in GaN devices AMCAD/Maury pulsed IV 25 Effect of Vstress in Output Characteristics DUT: 600V GaN-on-Si V_Stress = 50V V_Stress = 100V V_Stress = 150V V_Stress = 200V Vds (V) Measurement Setup: VdsPulse_Delay = 1us VdsPulse_width = 10us VgsPulse_Delay = 1.6us VgsPulse_Width = 8us Period = 2ms NOS = 1 24

25 Ron (Ω) Dynamic Ron vs. Time 0,9 0,8 V_Stress = 200V 0,7 0,6 0,5 0,4 0,3 SMU slew rate delay stable voltages? DUT: 600V GaN-on-Si V_Stress = 20V 0,2 0,E+00 1,E-06 2,E-06 3,E-06 4,E-06 5,E-06 Time (seconds) Meas Setup: VdsPulse_Delay = 1us VdsPulse_Width = 10us VgsPulse_Delay = 1.5us VgsPulse_Width = 8us Period = 2ms NOS = 1 Resolution=200ns 25

26 Id (A) Benchmarking different GaN devices Device A Device B Device C Vds (V) Device A, B and C, comparable devices from different manufacturers Meas Setup: Same voltage conditions VdsPulse_Delay = 1us VdsPulse_Width = 10us VgsPulse_Delay = 1.5us VgsPulse_Width = 8us Period = 2ms NOS = 1 26

27 Ron (Ω) Ron Temperature Dependence B1506A w/ heat plate 0,3 0,25 0,2 T=23 C T=100 C T=150 C 0,15 0,1 0,05 0 DUT: SiC MOSFET 600V / 100mΩ / 35A Vgs=10V Ids (A) Measurement Setup: Vgs=10V GatePulse_Delay=100us GatePulse_Width=100us DrainPulse_Delay=0us DrainPUlse_Width=200us PulsePeriod=50ms Keysight

28 Model Requirements 2D Capacitance Model LF Dispersion Model Thermal Model 28

29 POWER MODULE DESIGN FLOW ELECTRO-THERMAL CO-SIMULATION 29

30 Multi-Chip Module for Google/IEEE Little Box Challenge mm AlN DBC with half- and full-bridge bare-die SiC MOSFETs driver Ics bootstrap supply buffer caps 3D Mounting capacitor bank PCB multi-chip module heat sink dimensioning: f sw > 100 khz power up to 10 kw Reliability: 10 C simulated ΔT from T j to T heatsink

31 Electro-Thermal Co-Simulation Switching frequency: 100 khz Alternating output voltage V P = 340 V 31 Alternating output current I P = 11 A Alternating output power HB1 HB2 Temperature transients R th heatsink: K/W

32 Fullbridge-Module Transient Simulation 32 Power dissipation of each SiC-MOSFET depends on the actual output voltage The temperature pulsates with 60 Hz Temperature difference about 5 C Temperature peaking is only visible in the junction layer Time constants of the materials are high enough

33 Electro-thermal Co-Simulation 33 Mold mass 1 mm Bond-hor. M2 M1 Bond-vert. 0.5 mm Al-Top 0.04 mm SiC 0.4 mm Solder 0.1 mm Cu (DBC) 0.3 mm Ceramic (DBC) 0.63 mm Cu (DBC) 0.3 mm Heatsink 2mm New degrees of freedom Thermal equivalent circuit extraction (thermal impedance) Optimised compact layout of modules (hybrid, multi-chip, on-chip) Reduction of safety margins (de-rating) Optimised robustness Lifetime prediction (coupling to thermo-mechanical co-simulation)

34 POWER MODULE DESIGN FLOW GAN INTEGRATION 34

35 AlGaN/GaN HEMTs... can be tailored for power (cp. Baliga FOM, R on Q g, V bd ) and microwave applications (cp. Johnson FOM, f max, V bd ) show best R on Q g compared to Si and SiC can be cost-efficient when on Si-substrate as lateral devices are amenable to monolithic functional integration are today less mature (traps -> reliability, dynamic R on,...) are intrinsic depletion-mode / normally-on devices, normally-off are more complex (pdoping, Si-GaN cascode,...) have limited input dynamic range due to Schottky gate (except MISFET) 35

36 GaN Driver Integration: Motivation V GS t Robustness: normally-off default behaviour Switching Speed: reduction of gate loop inductance Quasi normally-off GaN driver (Monolithic) Integration of Gate driver & power transistor 36

37 Normally-On GaN-on-Si HFET Quasi-Normally-Off GaN-on-Si HFET Mönch et.al. ISPSD 2015 V GS = 0V I D V DS I D V V GS 37

38 GaN-Based Push-Pull Gate Driver Circuit V+ D Mönch et.al. ISPSD 2015 IN GaN HFET 600 V Power transistor IN Avoids shoot-through currents robust GaN push-pull Gate driver V- SS S Default: pull-down power transistor off if V- available 38

39 Boost Converter switching node Mönch et.al. ISPSD 2015 V IN V OUT GaN 600 V HFET V G++ V G- GaN gate driver Monolithic integration Hybrid integration 39

40 Hybrid GaN Power Module Mönch et.al. ISPSD 2015 Q1: GaN Power HEMT 100 mm, 24 A, 600 V D: GaN Schottky diode 50 mm, 12 A, 600 V Q PD : GaN HEMT 10 mm, 2.4 A, 600 V Q PU : GaN HEMT 10 mm, 2.4 A, 600 V 4x GaN diode, <100V, 10 mm 40

41 Turn-On and Turn-Off Transitions Turn-on t f,ds > 1.6 ns dv/dt MAX 91 V /ns t r,gs 5.4 ns no overshoot no oscillation fast switching Turn-off t r,ds > 1.2 ns dv/dt MAX 177 V /ns t f,gs 3.8 ns fast switching Mönch et.al. ISPSD

42 2 mm Monolithic Integration: Gate Driver & Power Transistor Power transistor 600 V / 24 A Gate driver <100 V +2.4 A / -1.2 A 3 mm Parasitic gate loop inductance almost eliminated Monolithic combination of transistors with different voltage ratings 42

43 CONCLUSION 43

44 Power and Microwave Electronics what do they have in common? 44

45 Thank you for your attention Ingmar Kallfass University of Stuttgart Institute of Robust Power Semiconductor Systems Pfaffenwaldring 47 D Stuttgart Tel.: +49 (0) Fax: +49 (0) ingmar.kallfass@ilh.uni-stuttgart.de 45

46 References [Catrene2013] Integrated power & energy efficiency, Power device technologies, simulations, assembly and circuit topographies enabling high energy efficiency applications, Catrene Scientific Committee Working Group Integrated power & energy efficiency, Comm.pdf [BIS2011] UK Department for Business Innovation and Skills, Power electronics: A strategy for success, [ECPE] [Online] 46

47 MISCELLANEOUS 47

48 Abstract The talk gives a high frequency perspective to the area of power semiconductor device modeling, power modules and power electronic circuits, and highlights the need for an RF-refined design flow in power electronics, with a focus on wide bandgap power transistors based on SiC and GaN. 48

49 EMC in Automotive Electronics Numerous and distributed electronic sensor, control and power units Data bus (e.g. CAN) t rise typ. 20 ns MOSFET (125 ns IGBT) f max = 17.5 MHz (2.8 MHz) λ eff 14.5 m (90.5 m) Car body (4m) 0.28 λ eff Reflections/Resonances Crosstalk Illustration: 49

50 Examples: Fast but Oscillating HRL Lab [1] 600 V GaN HEMT ISE [2] 600 V Panasonic GaN GiT IAF [3] 600 V GaN HFET Gate-Loop parasitics limit switching performance [1] Hughes, B., Rongming, C., Lazar, J., Hulsey, S., Garrido, A., Zehnder, D., Musni, M., and Boutros, K., Normally-off GaN switching 400V in 1.4ns using an ultra-low resistance and inductance gate drive, In Wide Bandgap Power Devices and Applications (WiPDA), 2013 IEEE Workshop on, [2] Hensel, A., Wilhelm, C., and Kranzer, D., Application of a new 600 V GaN transistor in power electronics for PV systems, In Power Electronics and Motion Control Conference (EPE/PEMC), th International, DS3d.4-1. [3] Weiss, B., Reiner, R., Quay, R., Waltereit, P., Müller, S., Benkhelifa, F., Mikulla, M., Schlechtweg, M., and Ambacher, O., Characterization of AlGaN/GaN-on-Si HFETs in high-power converter applications, In Power Electronics and Applications (EPE 2014), Proceedings of the th European Conference on: IEEE Press 50

51 Verwandte Arbeiten / Konzepte UCSD (2013): (D-Mode) 28V, 100 MHz GaN Systems (2014): (E-Mode) 3000 mm, 600 V Panasonic (2014): (E/D-Mode) 12 V, 2 MHz IAF (2009): (D-Mode) 120 V, GHz Panasonic (2012): (RF Gleichrichter) GHz / MHz Quellen: [1] Roberts, J. and Scott, I., On-Chip Drivers Enable High-Current, Normally Off GaN Transistors (Part 1), How2Power Today, no. 5, [2] Ujita, S., Kinoshita, Y., Umeda, H., Morita, T., Tamura, S., Ishida, M., and Ueda, T., A compact GaN-based DC-DC converter IC with high-speed gate drivers enabling high efficiencies, In Power Semiconductor Devices & IC's (ISPSD), 2014 IEEE 26th International Symposium on, [3] Young, P. H., Mukai, K., Gheidi, H., Shinjo, S., and Asbeck, P. M., High efficiency GaN switching converter IC with bootstrap driver for envelope tracking applications, In Radio Frequency Integrated Circuits Symposium (RFIC), 2013 IEEE, [4] Maroldt, S., Haupt, C., Kiefer, R., Bronner, W., Mueller, S., Benz, W., Quay, R., and Ambacher, O., High Efficiency Digital GaN MMIC Power Amplifiers for Future Switch-Mode Based Mobile Communication Systems, In Compound Semiconductor Integrated Circuit Symposium, CISC Annual IEEE, 1 4. [5] Nagai, S., Negoro, N., Fukuda, T., Otsuka, N., Ueda, T., Tanaka, T., and Ueda, D., eds., A one-chip isolated gate driver with Drive-by-Microwave technologies, Radio-Frequency Integration Technology (RFIT), 2012 IEEE International Symposium on,