Verilog-A Modeling of Radiation-Induced Mismatch Enhancement

Transcription

1 TNS R2 1 Verilog-A Modeling of Radiation-Induced Mismatch Enhancement Maxim S. Gorbunov, Student Member, IEEE, Igor A. Danilov, Student Member, IEEE, Gennady I. Zebrev and Pavel N. Osipenko Abstract Physical model of TID effects is embedded into BSIM3v3 model implemented using Verilog-A. Radiationinduced mismatch enhancement due to the combined action of technology variations and electrical bias difference is demonstrated by simulation. It is shown that the total ionizing dose degradation of circuit components under inequivalent electric field conditions could lead to mismatch of internal circuit parameters, which results in a change to circuit output mismatch parameters. Index Terms TID, SPICE, Verilog-A, CMOS, simulation, mismatch. M I. INTRODUCTION ODERN submicron CMOS ICs are widely used for special applications in ionizing radiation environments. Space electronic components usually need several hundreds of krad (Si) tolerance, the readout electronics for the high energy physics experiments require greater radiation hardness (more than 10 Mrad (Si)) and low power consumption. This work is devoted to the modeling of total ionizing dose (TID) effects on typical analog and mixed-signal ICs for the latter field with high dose levels. Radiation-induced charge buildup in oxides causes the threshold voltage shift, mobility and subthreshold swing degradation and leakage currents. In fact, for advanced ICs with very thin gate oxides, radiation-induced charge buildup in field oxides and SOI buried oxides (BOX) normally dominates the radiation-induced degradation of ICs [1, 2]. Radiation-induced leakage drastically increases power consumption and at high dose levels leads to the functional failure. High radiation tolerance can be achieved by technology optimization or by design [3]. The former approach is very effective but also very expensive. The latter approach can be implemented on standard commercial technology with high Manuscript received September 16, Maxim S. Gorbunov, Igor A. Danilov, Pavel N. Osipenko are with Computation Engineering Department (ORVT) of Scientific Research Institute of System Analysis, Russian Academy of Sciences, Nakhimovsky prosp. 36/1, Moscow, Russia, gorbunov@niisi.msk.ru; phone: ; fax: Gennady I. Zebrev is with the Department of Micro- and Nanoelectronics of Moscow Engineering Physics Institute (National Research Nuclear University), Moscow, Russia, gizebrev@mephi.ru. effectiveness and low cost. The focus of this work is on a new transistor-level TID effects modeling approach, which allows estimation of circuit components degradation under inequivalent bias conditions leading to mismatch of internal circuit parameters, which results in a change to circuit output mismatch parameters. The developed modeling tool is based on a TID effects model [4] embedded into BSIM3v3 compact model implemented in Verilog-A hardware description language (HDL). Simulation results for different types of ICs are discussed. A. Modeling and Simulation Conceptions for RHBD Radiation hardened IC designer often needs to compare different hardening methods to increase the effectiveness of the design. Irradiation tests for the whole chip allow the system hardness estimation, but evaluation of the components hardness is much more complicated. Therefore multi-level modeling is an essential part of radhard IC design. Standard SPICE models (BSIM, BSIMSOI, EKV, PSP, etc.) do not take into account any radiation effects. The integration of models of these effects into transistor-level simulation still remains a significant problem. Designers of radhard ICs often need the effective modeling tool embedded into standard design flow. Several modeling conceptions and their implementations were proposed during last few years (e. g., see [5-9]). The first main approach [5, 6] is based on complicated and computationally intensive TCAD modeling. In this case TID effects are simulated in single structure or small (~10 transistors) circuit for given dose value. Then SPICE parameters can be obtained with standard extraction strategy. It is very useful and accurate method if designers have sufficient information about technology features. However an IC designer often deals only with SPICE models and design rules and therefore can not obtain high simulation precision. Another disadvantage of this method is the need for a full extraction procedure for each dose value and at the electrical biases under irradiation. Another way of transferring between physical and transistor levels is based on VHDL-AMS or the other Analog-HDL modeling of radiation-induced parameters degradation by including of dose dependences of subsystem main parameters (obtained from whole chip radiation test) rather than SPICE parameters. Even when element s SPICE parameters dose dependencies are included in simulation routine, the major

2 TNS R2 2 Fig. 1. Proposed transistor-level approach for TID modeling. disadvantage of such tools is that modeling of degradation dependence on electrical bias during irradiation is practically impossible due to the semiempirical equations inflexibility: test structure can not be tested under all possible electrical bias conditions. A variety of different IC parameters total dose dependences is difficult to obtain from the experiment due to the complexity of necessary equipment. Therefore prediction of radiation-induced mismatch can be effectively done only by transistor-level simulation. Thus developing of modeling methodologies and tools is very important. B. Radiation-induced Mismatch Enhancement Transistor parametric mismatch is also a very important problem, especially for deep submicron analog and mixedsignal ICs. In addition to mismatch due to radiation-induced charge trapping variability caused by oxide thickness inequality there is the enhancement of parametric mismatch due to various electrical biases of transistors in real IC during irradiation. Matching is a subject widely studied [10-12], but there is still a lack of studies on irradiation effects on matching [13-15]. The impact of TID on unhardened and hardened SRAM cell margins was investigated in [14] and [15]. For the unhardened cells radiation-induced leakage is the primary source of parametric degradation. For the hardened cells the increase of leakage is negligible [15]. Therefore, a threshold voltage shift is the primary source of radiationinduced cell margins degradation for RHBD cells. In this work we have focused on the effect of radiation-induced mismatch enhancement due to the combined action of technology variations and electrical bias difference. Simulation results for threshold voltage variation in MOSFETs, characteristics of the ring oscillators, a bandgap voltage reference and a two-stage 3.3 V operational amplifier are presented. We assume that all transistors in the considered ICs have edgeless layout and consequently there is no radiation-induced leakage. Chartered 0.18 µm CMOS Design Kit is used due to the presence of the parameters for Monte Carlo simulation. Transistors with standard thin ( TN ) 3.5 nm and 3.3 V thick ( TK ) 6.5 nm gate oxides are available in this process. C. Paper Organization Section I has provided an introduction and motivation for this paper. The proposed transistor-level modeling approach is described in Section II. Section III briefly describes the TID effects model used in this work. The analysis of variation sources and simulation results for the process variation are provided in Section IV. Simulation results for different types of ICs are presented and discussed in Section V. II. TRANSISTOR-LEVEL MODELING APPROACH Integrated circuit designers work in the context of simulation environment (see Fig. 1), which contains simulators, editors, etc. Standard SPICE-like simulators support only limited quantity of device models. SPICEparameters and parameters for special types of analysis (e. g., statistical, or Monte Carlo analysis) are provided by Process Design Kit (PDK). Verilog-A module ( TIDEsim [16] in Fig. 1) is used instead of standard simulator s built-in models in the proposed circuit-level approach for TID modeling. A simulator evaluates the external code and makes the precalculation of the electrical regime of each transistor in a circuit. A total dose degradation is calculated within the Verilog-A module on the basis of the precalculations, i. e. inside each transistor. A series of recalculations is performed until solution for a given dose is found. The series of recalculations is provided only at the initial step of analysis. Thus a designer must take into account the initial conditions in a circuit, because these conditions appear as electrical bias conditions under irradiation. Two simulation modes are proposed:

3 TNS R2 3 1) All transistors in the circuit are assumed to have equal electrical bias under irradiation. In this case gate-source voltage and dose value are used as the additional parameters given by designer. 2) Electrical bias under irradiation for each transistor is set by the initial step of the analysis. In this case the dose value is used as the additional parameter. The former mode is used for calibration and TID model parameters values calculation. It is recommended when IV characteristics of single elements are needed. The latter mode can be recommended for radiation ICs sensitivity estimation. In this case radiation-induced parameters degradation is calculated for each transistor in IC taking into account the real values of node potentials. This mode is the primary one for our simulations. For switching circuits or circuits with periodic fluctuating voltages a designer must set different initial conditions to ensure that all typical or dominant electrical biases are considered. The input biases leading to the worst parametric degradation can be considered as worst case conditions. TIDEsim module contains MOSFET compact model with built-in TID effects model [4]. We used BSIM3v3 in this work [17]. If radiation effects are turned-off Verilog-A code provides the same simulation results as the built-in model. All simulations are provided with Cadence Spectre simulator [18] in this work. Subcircuits with the transistor instance parameters (channel length, width, source and drain perimeters and areas, etc.) and with included Verilog-A module are described. All transistors are therefore simulated as Verilog-A modules with standard instance parameters and additional parameters for TID effects modeling. The important feature of the proposed modeling strategy is that no changes in schematics are needed. Thus the modeling tool is built in the standard design flow. T ox Q D V E, D t. (2) ot Eox, 0 ox Model equations were added to BSIM3v3 Verilog-A code. Equation (2) was used as the additional component to SPICE parameter VTH0, which thus became dose dependent. The proposed model was verified experimentally [4]. The test partially depleted SOI transistors with shallow trench isolation (STI) were manufactured in a commercial nonhardened 0.5 μm process. A good correlation between the experimental data and simulation results has been demonstrated for rather wide range of dose levels. The threshold voltage shift was simulated for the bottom (with buried oxide as the gate oxide) and main enclosed layout transistor (ELT) [20] for the following bias conditions during irradiation: TG (V G = 0 V, V S =V D = 3.3 V, grounded substrate), TGB ( TG with substrate biased at -3.3 V), OFF (V D = 3.3 V, V G =V S = 0 V, grounded substrate) and OFB ( OFF with substrate biased at -3.3 V). Figs. 2-3 show the typical modeling results. One can see the good correlation between the experimental data and the modeling results. Fig. 2. Dose dependence of the main ELT threshold voltage shift: experimental (dots) and modeling (solid line) results. ox III. THE MODEL OF TOTAL IONIZING DOSE EFFECTS The model of radiation-induced edge leakage current has been presented [4]. Radiation-Induced Charge Neutralization (RICN) effect [19] has been shown to be significant for leakage current simulation. The possibility of electrical bias modeling and single set of parameters for all doses are important features of the proposed model. For a charge density Q ot (x, D) trapped in the oxide we have obtained dose dependence q Ft tox Qot Eox, D neox xecoll (1) 1 exp neox eff Eox K g xecolld, where D is dose, K g cm -3 rd -1 (SiO 2 ), F t is the hole capture efficiency, n is the electric-field-dependent crosssection for electron capture on positively charged oxide centers, x ecoll is effective electron collection length, eff is effective yield factor, t ox is the gate oxide thickness. The threshold voltage shift is modeled as follows: Fig. 3. Dose dependence of the bottom ELT threshold voltage shift: experimental (dots) and modeling (solid line) results. Unfortunately we have no information about TID sensitivity of Chartered 0.18 µm CMOS process. Therefore experimental data for the TID sensitivity of UMC 0.18 µm CMOS technology is used to obtain model parameters for simulation. Maximum threshold voltage shift at 2.2 Mrad (Si) is about 90 mv [21]. No significant mobility degradation was observed during the experiment, which is quite usual for this technology node [22, 23]. Therefore, interface trap formation is not taken into account. Obtained TID model parameters were applied to Chartered Design Kit.

4 TNS R2 4 IV. ANALYSIS OF THE VARIATION SOURCES The modern SPICE simulators support Monte Carlo analysis which involve calculation of batch-to-batch (process) and per-instance (mismatch) variations for netlist parameters. These statistically-varying netlist parameters can be referenced by models or instances in the main netlist and may represent IC manufacturing process variation [18]. The matching properties of the threshold voltage V th are derived by examining the mutually independent components W, L, N D and C OX (similarly to the matching properties of the current factor in [10]): V th W L N D Cox, (3) Vth W L N D Cox where W, L are channel width and length correspondingly, C OX is gate oxide capacitance, N D is the doping concentration. Radiation-induced positive charge trapped in gate oxide depends on the gate oxide thickness [14] and hence the V th matching properties are radiation dependent. Standard deviation, mv Dose, krad (Si) TK 3.3 V TK 0 V TN 1.8 V TN 0 V Fig. 4. Simulated dose dependences of threshold voltage standard deviation for 0.18 µm thick (TK) and thin (TN) gate oxide n-mosfets under high and low V GS during irradiation. Fig. 4 shows the simulated dose dependences of threshold voltage standard deviation σ Vth for different oxide thicknesses and electrical biases under irradiation. Only process variations are taken into account during these simulations. The threshold voltage is calculated from simulated IV characteristics by linear approximation technique. Before irradiation, σ Vth for TK is less than it is for TN (see Fig. 4). This effect is caused by combined action of different variation sources: layout parameters variation dominates other factors for small TN transistors. For TK transistors irradiated at high V GS the standard deviation dose dependence grows linearly from 8 mv to 28 mv while the change of the σ Vth after irradiation for TN transistors and another irradiation bias can be neglected. The growth of the σ Vth dose dependence is caused by more intensive charge collection in thicker gate oxides. For TK transistors the gate oxide thickness variation is higher than it is for TN transistors. It can be due to the complexity of uniformity assurance, because additional technology process steps are needed for non-standard thick oxides [24]. The negligible change of the standard deviation for low irradiation biases can be due to the predominance of the layout factors and doping concentration variations over the gate oxide thickness variation. The obtained simulation results are qualitatively correlated with σ Vth growth for ELT reported in [13]. The local changes in the electric field can be the additional mismatch source, independent of the gate area but dependent of size/shape of the drain. The difference of electrical biases during irradiation is the additional factor to the mismatch effect. V. SIMULATION CONDITIONS AND RESULTS In this work we have focused on typical parameters obtained from DC, AC and transient types of analysis. For DC analysis the dose dependences of the threshold voltage variations and bandgap voltage reference temperature dependence are simulated. Ring oscillator frequencies and offduty factor dose dependences are investigated for transient analysis. Low-frequency gain, gain-bandwidth product and phase margin of the simple two-cascade operational amplifier are investigated. Monte Carlo simulations are performed under process only and process and mismatch modes without definition of correlations. Thus layout dependence is not taken into account. Therefore, the results obtained should be considered as the worst case estimation. A. DC analysis: threshold voltage mismatch Let us consider two 0.18 µm n-mosfets with thick gate oxides. Threshold voltage of non-irradiated TK MOSFET is about 800 mv. The first transistor is irradiated at V GS =0 V, and the second is irradiated at V GS =3.3 V. Figs. 5-6 show simulated threshold voltage distributions for these transistors. Simulations are performed under process and mismatch mode. Fig. 5. Simulated threshold voltage distributions for TK MOSFETs after irradiation (2.5 Mrad (Si)) at V GS =0 V.

5 TNS R2 5 Fig. 6. Simulated threshold voltage distributions for TK MOSFETs after irradiation (2.5 Mrad (Si)) at V GS =3.3 V. Figs. 7-8 show the threshold voltage difference distributions for thick and thin gate oxides. One can see that due to the combined action of technology variations and electrical bias difference the threshold voltage mismatch is enhanced by radiation. The largest value of threshold voltage difference is about 550 mv (compare with nominal 335 mv for mean values) for thick oxides and 175 mv (versus nominal 103 mv) for thin oxides. The comparison of the results shown in Fig. 4 with the results shown in Figs. 7-8 demonstrates that the value of radiation-induced process variation enhancement can be neglected compared to mismatch enhancement due to the difference of the electrical biases during irradiation. B. Transient analysis: ring oscillators For transient analysis investigations 2 types of ring oscillators (RO) was used: with thin oxide (TN) and thick oxide (TK) transistors. Each RO consists of 240 inverters + 1 control element (NAND2). Table 1 shows obtained simulation results for the output frequency and off-duty factor. The initial condition for the control elements prevents the oscillation. At this point near half of transistors are under ON bias condition (V S =V D =0 V, V G =VDD for n-mosfets, V S =V D =VDD, V G =0 V for p- MOSFETs) and residual are under OFF condition (V S =V G =0 V, V D =VDD for n-mosfets, V S =V G =VDD, V D =0 V for p-mosfets). Transistor type TABLE I RING OSCILLATORS CHATACTERISTICS Total dose, Frequency, Off-duty Mrad (Si) MHz factor TK TK TK TN Fig. 7. Simulated threshold voltage difference distributions for 0.18 µm MOSFETs: thick oxide. Dose value is 2.5 Mrad (Si). Fig. 8. Simulated threshold voltage difference distributions for 0.18 µm MOSFETs: thin oxide. Dose value is 2.5 Mrad (Si). TN TN The shown results demonstrate insufficient frequency degradation at 2.5 Mrad (Si). Nevertheless, if we apply the same model parameters of the threshold voltage degradation to extremely high total dose values, frequency and off-duty factor degradation is significant even for TN transistors. C. DC analysis: Bandgap voltage reference Bandgap voltage reference (BGVR) consists of thick oxide transistors and operates under 3.3 V power supply. Fig. 9 shows its schematics. Resistors, vertical pnp transistors and start-up circuit are shown as black boxes. In standard CMOS technology pnp transistors are often used as diodes for Bandgap voltage references [25]. It is known that bipolar transistors are very sensitive to TID effects [26]. The main consequence of the TID effect is the strong decrease of the forward-current transfer ratios. The damage in bipolar devices is enhanced at low dose rates [27].

6 TNS R2 6 Fig. 9. Bandgap voltage reference schematics. It has been found that bandgap references featuring conventional diodes are rather vulnerable to TID effect. Detailed analysis of the behavior of conventional bandgap references in deep submicron CMOS technology indicates that radiation damage in diodes is the main cause of reference voltage shifts [28]. For radiation doses up to 79 Mrad (Si), about 4% shift in the reference voltages, due to this effect, has been found [28]. The maximum considered value of total dose for BGVR is 2.5 Mrad (Si) and the dose rate is about 100 rad (Si)/s in our work. Therefore the parametric degradation of vertical bipolar pnp transistors are assumed to be negligible. The voltage drift from -60 ºC to 125 ºC and the output voltage at -60 ºC, 27 ºC and 125 ºC were simulated for dose values up to 2.5 Mrad (Si). Figs show the simulation results. Mean voltage drift is about 3.7 mv and does not significantly change after 2.5 Mrad (Si). Fig. 10. Simulated output voltage drift distribution before irradiation. Fig. 11. Simulated output voltage drift distribution after 2.5 Mrad (Si). In some applications not only the stability of the reference voltage is important, but also its absolute value [28]. The permissible range of the output voltage values depends on the desirable accuracy of the design. Let s consider 1.22 V as the nominal value of the output voltage and 2.5% as the permissible range. Fig. 12 shows the simulated output voltage distributions at 27 ºC before irradiation and after 2.5 Mrad (Si). The impermissible regions are marked with rectangles. Since there are no radiation-induced leakage and a degradation of bipolar transistors characteristics, the threshold voltage shifts are the primary source of parametric degradation. One can see that the number of iterations with impermissible output voltage value increases after irradiation. Nevertheless the TID sensitivity of the considered BGVR is relatively low, which is firstly caused by small gate oxide thickness. Secondly, the gate-source voltages during irradiation do not reach the worst case value (V GS < VDD).

7 TNS R2 7 Fig. 7. Simulated output voltage distributions at 27 ºC: a) before irradiation, b) after 2.5 Mrad (Si). D. AC analysis: operational amplifier Two-stage OpAmp consists of thick-oxide transistors and operates under 3.3 V power supply. Frequency compensation and load capacitances characteristics are assumed not to degrade after irradiation. Electrical bias conditions were calculated for each transistor by simulator at the initial point of AC analysis. Both inputs have equal DC voltage level during irradiation and AC analysis (1.21 V). This case is more typical for operational amplifiers than for comparators [29] or sense amplifiers, because OpAmps are used with negative feedback. Low-frequency gain, gain-bandwidth product and phase margin distributions were obtained from Bode diagrams. Simulation results show no significant parameters degradation after 2.5 Mrad (Si) was observed when input signals values are the same. The possible reasons for this fact are likely to be the same as for BGVR. VI. CONCLUSION Physical model of total ionizing dose (TID) effects previously developed and successfully verified by authors [4] is embedded into BSIM model implemented using Verilog-A language. This tool is fully compatible with standard SPICE simulators (Spectre, UltraSim, HSPICE, ELDO, etc.) and allows taking into account the electrical bias conditions for each transistor during irradiation. Radiation-induced enhancement of transistor parameter s variation is simulated for 0.18 μm MOSFETs. Electrical bias conditions (during irradiation) dependence of variation is clearly demonstrated. For non-standard layout, the local changes in the electric field can be the additional mismatch source, independent of the gate area but dependent of shape of the drain-gate region. The value of radiation-induced process variation enhancement can be neglected compared to mismatch enhancement due to the difference of the electrical biases during irradiation. Note that high electric bias sensitivity of TID effects leads to necessity of special bias networks design for analog and mixed-signal circuits. With these networks all the devices in critical nets have equal gate-source voltages, and hence threshold voltage shifts track very closely and radiation-induced degradation therefore decreases [30]. But even using of such networks can not guarantee the absence of radiation-induced imbalance due to the different voltage values at the inputs. The proposed model can aid the designers in finding worst input signals combinations, so the system designer can avoid the appearance of these combinations for the given device. The proposed simulation approach is applied to different digital and analog devices. Simulation results for high dose values were obtained. ACKNOWLEDGMENT The authors wish to thank Sven Löchner, GSI Helmholtzzentrum für Schwerionenforschung GmbH, Germany, for providing the experiments information, Valeriy Shunkov and Alexandra Shnaider, Scientific Research Institute of System Analysis, Russian Academy of Sciences, for discussions. REFERENCES [1] H. J. Barnaby, Total-Ionizing-Dose Effects in Modern CMOS Technologies, IEEE Trans. Nucl. Sci., vol. 53, no. 6, pp , [2] J. R. Schwank, M. R. Shaneyfelt, D. M. Fleetwood, et al., Radiation Effects in MOS Oxides, IEEE Trans. Nucl. Sci., vol. 55, no.4, pp , August [3] R. C. Lacoe, Improving Integrated Circuit Performance Through the Application of Hardness-by-Design Methodology, IEEE Trans. on Nucl. Sci., vol. 55, no. 4, August 2008.

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