2. TECHNICAL CONTENT

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1 2. TECHNICAL CONTENT 2.1 Abstract: We propose to design and build novel 50W Silicon Carbide single chip power converters, while at the same time demonstrating the capability to design and fabricate SiC integrated circuits (IC s). These Silicon Carbide (SiC) power ICs will have switching speeds greater than 5MHz and efficiencies greater than 93%. Currently, single chip power circuits are typically limited to a few watts and tens of volts. The proposed prototype will overcome this limitation by more than an order of magnitude, and establish a new paradigm for single chip, high efficiency power converters. Due to SiC s large bandgap, which is three times the bandgap of Silicon, much smaller power devices can be constructed with large blocking voltages. This can lead to an assortment of extremely favorable IC properties including significantly smaller dimensions, greater efficiency and higher switching speeds. Design and fabrication of this transformational technology will be enabled through the use of the unique SiC fabrication capabilities at Cree Inc., which is the world s leading foundry for SiC wafers and devices. Cree is close to starting full production of its power DMOSFET and has significant experience with the SiC MOS technology. The objective for Cree Inc. as part of this project is to create a MOSFET based integrated circuit fabrication process consistent with their existing processes. Cree will fabricate lateral power MOSFETs and various circuit components like op-amps, gate drivers and control circuits. Cree will progress on to fabricating the full power converter chip in the second year of this project. Cree, CoolCAD and Boise State University will create process design kits (PDKs) to streamline the circuit design, layout and fabrication tasks. State of the art design tools have been developed exclusively for SiC by scientists and engineers at CoolCAD and the University of Maryland. These tools are unique in that they account for oxide, interface and transition layer characteristics of SiC MOS devices. Accounting for the role of these structural challenges for MOS devices will allow for robust SiC chip design which otherwise may not be realizable. In addition, we have developed unique modeling codes that allow for co-design of electrical and thermal characteristics. These simulation capabilities are key to developing power IC s which are expected to handle power densities that are orders of magnitude higher than the current state of the art. Circuit design will include the efforts of the Boise State team, whose lead member holds over one hundred patents on circuits, and has authored one of the world s best-selling books on CMOS design. Packaging for extreme environments will be achieved by the University of Maryland team (CALCE Center), which is a world leader on assessing package related reliability of electronics. The proposed research represents a transformational technology because it propels the microelectronics revolution to high power and high temperature through the use of the wide bandgap semiconductor material SiC. This will enable fabrication of high temperature power and control systems that will work in extremely harsh environments such as those found in geothermal drill sites, sensor systems in engines of aircraft and hybrid vehicles, and compact power systems in satellites. The availability of highly efficient, high voltage and high power density IC s will find application in solar micro-inverters as well as solid-state lighting. As part of this project, we will create other high temperature IC s such as integrated gate drives and operational amplifiers which will be used in control electronics of large power systems such as wind turbines. Substantial research in the areas of SiC integrated circuits, power device design, and high temperature packaging will be carried out. This will lead to several research publications for the universities involved in this project. i

2 2.2 Research and Development Tasks This project seeks to design and develop a 50W Silicon Carbide power converter IC for application in high-temperature and harsh environments. We aim to prototype new power IC s that, by using SiC, set a new standard for operating voltages, temperatures, frequencies and power transferability. Also, our goal is to establish a new paradigm and a nascent industry of power ICs based on the design and fabrication of SiC MOS electronics. This requires a comprehensive approach involving modeling, device design, circuit design, fabrication, process optimization, high temperature packaging and thorough testing in real-world conditions. The design and development of SiC power converter chips present significant innovation including: Fully-integrated SiC based single chip power converters in the 10W-50W class; Op- Amp integrated circuit in SiC capable of operation at high temperatures; Integrated gate drive in SiC; Verilog-A based behavioral models for SiC CMOS devices; Comprehensive Process Design Kit (PDK) for Cree s SiC Process; Coupled electro-thermal simulation capability to create optimized power ICs in SiC; Fabrication methodologies of SiC integrated circuits; and reliable packaging of SiC Power Integrated Circuits. Challenges to this project are the relatively early-stage of Silicon Carbide semiconductor products, lack of design rules and device models, lack of large scale integration process in Silicon Carbide, and need for high temperature packaging. During this project, we aim to overcome these challenges, and create a novel Silicon Carbide based integrated circuit, design kits, and technical know-how, that could potentially revolutionize the energy efficiency of existing systems and extend the use of sophisticated electronics to temperatures beyond 250 o C. For efficient project management, we have broadly divided the project s tasks as follows: 1. TCAD Modeling and Design of SiC MOSFETs 2. Physics Based Compact Device and Circuit Modeling 3. SiC Process Design Kit (PDK) Development 4. SiC Circuit Design 5. SiC Integrated Circuit Fabrication 6. Thermal Modeling and High Temperature Packaging 7. Testing, Validation and Design Optimization While these distinctions are made for organizational purposes, in reality, all the tasks are inter-related and the various teams will be working closely with one another to ensure success. End of Project Goals: By the end of this project we expect to have the capability of designing and fabricating complex integrated circuits in SiC that will be able to operate at >250 o C. We also expect to have a first complete PDK for Cree s SiC design process. Along with our main goal of creating a 50W power converter IC in Silicon Carbide, we will also fabricate, package and test high temperature op-amps and gate drives in SiC. The SiC power converter IC will be fabricated with small variations to act as buck and boost DC-DC converters. Another version of the IC will be an AC-DC converter capable of converting the line voltage to regulated DC voltage which will be used in solid state lighting applications. We will also focus on applying our IC s for power converters in satellites, high temperature sensing and communication units such as found in down-hole applications, and seek to extend the power transfer capability so that they can be used in micro-inverters for solar panels. ii

3 2.3 Research and Development Strategy: a. Innovation: The design and development of an Advanced Prototype SiC power converter chip presents a new generation in innovation as well as challenges. Table 1 shows a list of design specifications we aim to achieve during this project. The key innovative aspects of the IC and the design process we are proposing to achieve in the final product are as follows: Fully-integrated SiC based single chip power converters (DC-DC and AC-DC) in the 10W-50W class; High temperature op-amp integrated circuit in SiC; Integrated control circuit and gate drive in SiC; Verilog-A based behavioral models for SiC devices; Comprehensive Process Design Kit (PDK) for Cree s SiC Process; Coupled electro-thermal simulation capability to create optimized power ICs in SiC; Fabrication know-how and expertise in SiC integrated circuits capable of operating at high temperatures. Existing Silicon based technology is not able to meet all the Table 1. Design Specifications specifications listed in Table 1. While low-power (~1W) Power 50W integrated power converters in Silicon have been demonstrated to Frequency 5MHz have >93% efficiency, their efficiencies at high temperatures are Efficiency >93% significantly lower. Other technologies such as GaN do not have a Temperature >250 o C good MOS based process and therefore are unsuitable for complex control and drive circuit fabrication. SiC is the only technology Power ~ 100 which can meet the high power density, high temperature, and Density W/cm 2 high efficiency requirements described in the table and is the most 120V AC to AC-DC suitable candidate for extending sophisticated power electronics to 5V/12V DC extreme environment operation. The goals of this project will be to develop on-chip AC-DC and DC-DC converters with specifications given in Table 1. Further, we will be prototyping high temperature op-amps and integrated gate drivers as they themselves are marketable products. b. Approach: We aim to create advanced prototypes of SiC power IC s that set a new standard for operating voltages, temperatures, switching frequencies and power transferability. This requires a very comprehensive approach involving modeling, device design, circuit design, fabrication, testing, process optimization, and high temperature packaging. For efficient work flow, DC-DC Boost DC-DC Buck 12V to 36V/100V 100V to 5V/12V Fig. 1. Work flow for SiC Power Converter IC modeling, design and fabrication. we have broadly divided the project s tasks as shown in Fig. I.1, and planned out the technical tasks as follows: 1. TCAD Modeling and Design of SiC MOSFET: The integrated power device will be designed and fabricated as a lateral power MOSFET. We will explore enhancement and depletion mode designs for this structure. Detailed physics based 2D device modeling will be carried out to optimize the device geometry and doping profiles, to create a low capacitance, 1

4 high breakdown voltage, low on-resistance device that will enable us to exceed the efficiency and switching frequency specifications as described in the solicitation. The TCAD designs will be given to Cree for implementation and fabrication of the power device. 2. Physics Based Compact Device and Circuit Modeling: We will build physics based compact behavioral models for SiC devices using the behavioral language Verilog-A. This task will also involve room and high temperature measurement of I-V and C-V characteristics of the SiC devices, and extraction of BSIM parameters using Agilent s IC-CAP extraction software. 3. SiC Process Design Kit (PDK) Development: The compact models will be part of a comprehensive SiC process design kit. Other aspects of the PDK will be developed a for 2-metal IC process, design rules for the active regions, metal-poly and metal-metal spacing, etc. 4. SiC Circuit Design: We will design op-amps, level translators, stable voltage references, gate drives, inverter chains, etc. for this project. We will design unique control and driver circuits using enhancement and depletion mode NMOSFETs. These circuits will be extensively modeled and simulated using the new PDK, and their designs will be optimized for high temperature operation. 5. SiC IC Fabrication: This task will focus on developing a CMOS or NMOS only process for fabricating complex integrated circuits in SiC. Process optimization will be carried out throughout the project to create temperature stable power and control devices and circuits. 6. Thermal Modeling and High Temperature Packaging: We will first explore currently available packaging techniques for high temperature operation. Detailed modeling and testing of the thermal characteristics, flexural fatigue, and other phenomena will be carried out. We will then focus on developing high temperature packages for the SiC power converter ICs. 7. Testing, Validation and Design Optimization: At all stages of the SiC power converter IC development, we will be continuously testing the devices and circuits to optimize our models and our circuit topologies. These tests will be carried out at the die, package and system levels. We will test the packaged SiC power IC thoroughly at the system level. Research Publications: We will actively pursue opportunities to publish the results of our work in industry conferences, peer reviewed technical journals, and as articles in popular magazines such as IEEE Spectrum. We expect to have several publications in the fields of IC design, high temperature electronics, SiC physics, and high temperature packaging. Industry Collaborations: During this project, we will strongly pursue collaborations with other companies and government laboratories working in this area. We will form partnerships to supply these entities with our ICs and evaluation kits to enable testing of our chips in various real-world scenarios. We will focus especially on applying our ICs as power converters in solid state lighting (SSL), high temperature sensing and communication settings such as down-hole applications. We will seek to extend the power ratings so that they can be used in micro-inverters for solar panels. The following sections describe our technical work plan in greater detail. Task 1. TCAD Modeling and Design of SiC MOSFET: Distributed physics-based numerical models can provide significant insights into the operation of Silicon Carbide power devices since they enable probing inside the device for any electrical profile of interest, as shown in Figure 1.1. Therefore, TCAD tools offer ways to engineer devices for optimized performance. Further, Silicon Carbide MOSFETs present unique challenges for distributed modeling due to the presence of interface traps which greatly affect transport in these devices, and may become very important at high switching frequencies [1-3]. We have an established record of creating 2

5 robust physics based TCAD models for SiC vertical power devices. We will leverage this experience [1-7] to create distributed physics-based models for lateral devices operating at high frequencies to aid the design and fabrication of these lateral power MOSFETs for achieving the stated frequency and efficiency goals. To obtain electrostatic potential and carrier concentration profiles inside a Silicon Carbide device, we will solve the coupled differential equations comprising of the Poisson equation, and electron and hole current continuity equations in conjunction with the electron and hole current equations [1-7]. We previously solved these equations for a Cree fabricated vertical Silicon Carbide power DMOSFET for steady state and time-dependent operations, and suggested ways to improve the performance via changing the doping levels and physical dimensions. Figure 1.2 shows the simulated and measured I D -V G characteristics of this 20 A 1200V double diffused MOSFET. The developed device models examine the physics of the interface traps, the channel mobility and the off-state breakdown to extract the threshold voltage, on-resistance, and blocking voltage capabilities, respectively. Fig. 1.1: Electric field profile near breakdown of a 20A SiC DMOSFET operating at 150 o C. Fig. 1.2: I D -V G characteristics of a 20A SiC DMOSFET operating at 150 o C. To design and fabricate optimized SiC devices, we will pursue modeling for the following. Subtask 1: Laterally diffused MOSFETs (LDMOSFETs) for power switching. Subtask 2: Buried and surface channel N-MOSFETs for control circuits. These TCAD modeling efforts will be performed in conjunction with Cree to arrive at optimized application-specific devices through modeling and experiments. Specifically, LDMOSFET modeling will guide the development of low capacitance and on-resistance lateral power devices for fast switching and high efficiency. Modeling and simulation of depletion mode n-channel MOSFETs will be used to achieve fast charging capabilities for these devices when they are used as inverter loads in gate driver circuits or output buffers. In summary, we will develop these Silicon Carbide device TCAD capabilities along with Cree fabrication runs to achieve and possibly surpass design constraints stated in the proposal. Thus we expect the TCAD modeling work start with the program, and continue through the first year, and gradually subside in the second year as we decide on most promising device structures and circuit topologies. Task 2. Physics Based Compact Device and Circuit Modeling: Development of physicsbased analytical compact device models and their use in SPICE-type general purpose analog electronic circuit simulators are necessary to achieve performance prediction of integrated circuits. Even though compact models for Silicon-based technologies are relatively mature, such models for Silicon-Carbide electronics are not readily available; since Silicon-Carbide field effect transistors are currently being developed (high power Silicon Carbide transistor fabrication is in its final stages of development for commercial availability). As this technology is expected to open new paradigms in high power and high temperature electronics, CoolCAD Electronics 3

6 LLC and Cree Inc are planning to offer power converter, gate driver, pulse width modulator, and other power electronics ICs and IC design capabilities that take advantage of Silicon-Carbide s high efficiency and high temperature operation compared to Silicon. To achieve robust, high efficiency energy-saver power converter ICs, careful design and simulation of the devices fabricated in this relatively new technology are required. To this end, we will develop compact models to be used in general purpose circuit simulators. Based on the compact models and the simulation results, new circuit topologies that achieve maximum efficiency, as well as temperature and line voltage independent operation will be determined. To ensure the optimization of inter-related conversion efficiency, high temperature operation, robustness, and reliability of the novel SiC integrated circuits, CoolCAD will follow a multipronged design approach. This will involve SiC device compact model development, integrated circuit (IC) design, as well as electrical simulations of novel power converter ICs and related circuits such as operational amplifiers, gate drivers and pulse width modulators. Subtask 1: Parameter Extraction for Compact Model: We plan to use the BSIM transistor model s equation set as a starting point for compact model comparisons and development for SiC power converter and control circuit designs. Compact models such as BSIM4 have large numbers of parameters (specifically more than five hundred), which characterize field-effecttransistors in various regions of operation based on bias conditions, physical dimensions, and fabrication steps. Thus, the extraction of a parameter set to be used in these models is extremely challenging. To obtain an initial parameter set and the consequent parameter set extractions, as well as to facilitate data collection during measurements, we plan to use the integrated circuit characterization and analysis program ICCAP, which is an advanced, customizable modeling software and includes measurement, simulation, optimization and statistical analysis tools. ICCAP s parameter extraction and optimization for our Silicon devices are screen-captured in Figure 2.1. Due to the unique properties of Silicon Carbide low and high voltage devices, as well as their dependences on various layout and bias parameters, which may be quite different compared to their Silicon counterparts, the extraction will require manual optimization algorithms and clever use of different regions of operation for specific extractions in conjunction with built-in optimization tools of this program. Additionally, the extraction of different model parameters requires the design and fabrication of various structures that are suitable for the extraction of these parameters by providing physical degrees of freedom in addition to electrical. In terms of physical degrees of freedom such as layout dimensions, doping values, and different device configurations, CoolCAD will work with Cree to ensure the most inclusive parameter set development for the model, and the most promising structure selection for the proposed goals and the electrical and thermal requirements. We plan to perform parameter extraction throughout most of the program, with most activity between the third and the eighth quarters. During this period, CoolCAD will receive test structures with devices and sub-circuits from Cree. Subtask 2: Compact Model Development for Silicon Carbide Electronics: Even though the BSIM model set offers a powerful tool to predict transistor operation, unique properties of Silicon Carbide devices may call Fig. 2.1: ICCAP BSIM parameter extraction and data collection window. 4

7 for additional model equations and modifications of the existing models. However, BSIM simulation results can be adjusted only by changing device model parameters (user is not allowed to access BSIM equations which are hardcoded in commercial simulators). BSIM I-V curves are likely to deviate from Silicon Carbide device measurements under extreme bias and temperature conditions. Thus our goal is to obtain a BSIM type model and parameter set that are applicable for Silicon Carbide devices at all temperatures and integrate smoothly into existing compact modeling tools. To develop the expanded BSIM model set required to fully characterize the unique Silicon Carbide devices, we plan to use the analog behavioral modeling language Verilog-A. Verilog-A is an industry-standard compact device simulation modeling language that can easily be coupled and compiled with circuit simulators. First, we plan to develop the capability to import the BSIM models into Verilog-A, which requires translation of the BSIM source code into Verilog-A. Then we will input this Verilog-A program into an IC design system for numerical evaluation [8]. We then can modify BSIM Verilog-A code where necessary to be applicable to Silicon Carbide power and high temperature device conditions. Previously we have developed a preliminary set of compact models for DMOSFET circuit design at high temperatures [9]. More specifically, we have modified compact BSIM models that we imported into Verilog-A to be temperature dependent and reflect operation of a high power Cree fabricated Silicon Carbide DMOSFET. This is achieved by modifying temperature dependence of key terms in the BSIM equations which are now accessible through Verilog-A. Figure 2.2a shows the measured current-voltage curves of a Cree fabricated 20A 1200V vertical DMOSFET along with our fits obtained using a BSIM-based Verilog-A model. By using our simulations and measurements as a guide, we have achieved agreement for temperature dependence of DMOSFET current-voltage characteristics which were not achieved using the standard BSIM. We have also included some preliminary capacitance modeling in this model as shown in Figure 2.2b. Further, we note that for the proposed work, we will develop an all SiC power converter that uses lateral power MOSFETs to achieve the required speed and efficiency. We expect to achieve the SiC Verilog-A modeling capability at least for low voltage devices within the first year. In the second year this Silicon Carbide model library will be expanded by including the high voltage components and the rest of the circuit elements. Subtask 3: Compact Model Refinement and Parameter Extraction: We will simulate various subcircuit and converter designs using the all Silicon Carbide model libraries and cards, which will also be part of our all Silicon-Carbide integrated circuit process design kit. For instance we used the aforementioned DMOSFET model to previously design a 12V/24V SiC DMOSFET based boost converter. This model was used to obtain a boost converter circuit that utilizes this vertical Silicon Carbide power device as the switching element. We expect that the compact model and a) b) Fig. 2.2: a) Measured and Verilog- A simulated current-voltage curves of a Cree fabricated 20A 4H-SiC DMOSFET at 150 o C. b) Gatedrain capacitance of this device. 5

8 the associated parameter refinement will take place in the second and third years with finalized models and the resulting working prototype fabrication in the third year. Fig. 3.1: Screenshot of the Electric VLSI design tool with an op-amp schematic and layout. Task 3. SiC Process Design Kit (PDK) Development: A significant aspect of the proposed research is to experimentally fabricate and evaluate the nascent SiC integrated circuit technology for the design of the next generation of high temperature and high efficiency power conversion circuits. Compared to Silicon, Silicon Carbide technology is in its early stages of development. It presents some currentvoltage characteristics that are unique to its electrical operation and subtly different from those of its Silicon counterparts. Thus to better understand this technology and use its capabilities to the fullest extent, we need to comprehensively model the performance of various structures in the SiC process. We will extract compact model parameters for Silicon Carbide devices such as MOSFETs and components such as resistors and diodes, and develop layout tools to facilitate fabrication of these devices. We will develop SiC process design kits for carrying out simultaneous physical design, electrical simulation and circuit performance prediction. To facilitate Silicon Carbide layout, design and circuit simulation, the development of a SiC process design kit will be achieved by the successful completion of the following tasks. Subtask 1: Silicon Carbide Process Design Kit Development: Layout and Schematic: We will set up tools for laying out test structures and circuit building blocks (op-amps, comparators, voltage/current references, etc.), for the design of all Silicon Carbide power conversion chips. Since the focus of the proposed research is on the development of circuits, SiC technology, and simulation models for SiC devices (MOSFETs and diodes) the time spent setting up supporting computer aided design (CAD) tools to generate chip layouts will be performed within the first two quarters of the project. We will use a free tool called the Electric VLSI system [10]. A screen shot from this tool showing a CMOS op-amp schematic and layout that we have designed can be seen in Figure 3.1. Note that Electric is capable of generating netlists for simulations (from any simulator), performing layout design rule checks (DRCs), performing layout versus schematic (LVS), checking the connection of well tie-downs, and antenna checks. In summary, it is an ideal tool for this project since it will allow very fast turnaround times to generate the proposed mask layouts, won t take long to setup or modify a technology file for the developing SiC process flow, and can ultimately be used to design, layout, and simulate SiC power conversion circuits. Subtask 2: Incorporation of Silicon Carbide Models into PDK: Following the fabrication of test structures and simple circuits, electrical characterization of the components will be performed to provide feedback to the compact model development and the associated PDK refinement. To achieve as-designed operation, the layout tool will be linked to the compact SiC models, and the layouts and schematics will be used in conjunction with these models for performance prediction. The continuous refinement of the Silicon Carbide models, design tools and fabrication techniques is vital for a successful converter chip development. Based on the designs, testing and performance, we will select best device configurations and circuit topologies to be 6

9 used in the control, power and output stages of the Silicon Carbide power converter, between the third and seventh quarters. Subtask 3: Silicon Carbide PDK for Power Converter and IC Design: During the last year of the program, we will focus most of our efforts on the design, fabrication and testing of a working all Silicon Carbide 50W power converter. We will further refine and finalize our PDK layout capabilities as well as PDK compact models, based on the measured electrical IC performance figures, as well as packaged and tested Silicon Carbide power chips. Additionally, during the final phase of the proposed work, as the process technology and circuit topologies mature, focus can be turned towards setting up PDKs for commercial layout tools including Cadence [11]. Task 4. SiC Circuit Design: We plan to develop models for Silicon Carbide low and high voltage devices, Silicon Carbide device and component libraries for use in all Silicon Carbide process design kits that will be developed as part of this project, and circuit topologies that overcome the unique challenges of this technology and exploit its full capacity. More specifically, we plan to develop Silicon Carbide integrated circuit designs, as well as Silicon Carbide component and sub-circuit libraries with an aim to design, fabricate, test and demonstrate fully functional all Silicon Carbide power converter chips and related sub-circuit ICs at the end of this project. To achieve a working 50W Silicon Carbide power converter, we will start with the design, layout, fabrication and testing of fundamental Silicon Carbide devices and circuit building blocks. Silicon Carbide models and design tools will be updated and refined iteratively using the empirical data. This will be followed by the design of more complex power circuit control sub-circuits, core switching power circuit elements and the complete Silicon Carbide power IC. Subtask 1: Design of Test Structures and Circuits: Once the Electric Silicon Carbide VLSI Design CAD tool is setup with the SiC process technology, layouts of test structures and simple circuits such as amplifiers and inverter chains will be generated to pass to Cree for fabrication, and simple building block circuits will be designed. The approach we ve proposed, that is, setting up Electric to generate masks early in the proposed work and then designing various test circuits first in an NMOS-only technology then in CMOS, will allow quick prototyping of SiC integrated circuits so that a comparison between the models developed with this work and the performance of the circuits can quickly be performed. The design team on this proposal has significant experience designing power MOSFETs, NMOS-only circuits, and power conversion circuits. Important circuits to be developed along with the power MOSFET transistors include: gate drivers (to drive the power MOSFETs), comparators, voltage/current references, op-amps, basic logic, and triangle wave generators (used in pulse-width modulation). Initial SiC technology development will focus on NMOS process technology with enhancement and depletion mode MOSFETs, p-type poly thin film transistors, pn junction and Schottky barrier diodes, capacitors, as well as poly and well resistors. The maximum use of the NMOS process technology is due to the relatively less optimized PMOS process flow in Silicon Carbide, and thus is for reducing risk/cost to achieve successful program results. A lower voltage NMOS enhancement device (positive threshold voltage) will be used for general circuit design while a higher-voltage depletion Fig. 4.1: NMOS-only gate driver. device (negative threshold voltage) will be used for switching 7

10 the voltages present when going from the line voltage to some other voltage using a switching power supply topology (e.g., boost, buck, or C uk). Further, we plan to finish the lay out and design of test structures / simple circuits in the third and fourth quarters. Subtask 2: Design, Simulation and Layout of SiC Power Converter IC and Sub-Circuits: After the design, fabrication and testing of simpler components and circuits, we will work on more complicated circuits and the building blocks in our Silicon Carbide switching power supply. In the second year and the first half of the third year, these sub-circuits and the overall Silicon Carbide power converter IC will be designed, simulated using the compact models developed, laid out with the help of Silicon Carbide PDK installed into the Electric VLSI tool, and fabricated by Cree for circuit performance verification. In the following, we briefly present some NMOS-only circuit topologies that can likely be used to demonstrate circuits that will be useful for achieving asdesigned all Silicon Carbide switching power supply. Gate Drivers: A potentially significant limitation towards reaching 5 MHz switching speeds is the ability to turn-on and off the power MOSFETs. The gate of a power MOSFET presents a significant capacitive load that must be driven with transition times of tens of nanoseconds. An example NMOS-only gate driver topology is seen in Figure 4.1. This is a dynamic circuit meaning it requires active input signals, S (set) and R (reset). When this circuit isn t active both S and R can be low. To minimize contention current pulled from the power supply neither S nor R should be high at the same time. Bootstrapping is employed so that the output can swing from ground to VDD. For high-speed operation the ratio of the capacitive load to the driver s input capacitance should be less than or equal to eight, which requires cascading scaled drivers. Voltage/Current Reference: Another extremely important circuit found in a power converter, or any analog circuit, is the voltage/current reference used for analog biasing and/or to ensure a stable regulated output voltage. The reference should change little with temperature and power supply voltage. The reference voltage can generally be trimmed to account for process variations. The challenges found in an NMOS-only reference are the need to operate over a very large temperature swing and the lack of a PMOS device. While most references, e.g. bandgaps, are implemented using a parasitic device here we propose to implement a reference using polysilicon resistors and NMOS devices, Figure 4.2a. The positive temperature coefficient of the polysilicon resistors is used to cancel the negative temperature coefficient of the MOSFET threshold voltage. For power supply insensitivity, a large loop gain is used. We will investigate optimum topologies for very wide-range (temperature and voltage) references. NMOS Operational-Amplifier: A good portion of the circuitry used in the NMOS reference seen in Figure 4.2a (the three differential amplifiers) and the reference itself can be used to implement a general purpose NMOS op-amp, Figure 4.2b. The last diff-amp stage uses a resistive load (e.g. a polysilicon resistor) to both provide a dominant pole (when used with a compensation capacitor Cc) and to increase the op-amp s output swing. The output stage of the op-amp consists of a source-follower amplifier to isolate the gain stages from the load providing current gain. a) b) Fig. 4.2: a) NMOS-only reference. b) A general purpose NMOS Op-Amp. 8

11 Note that by removing the compensation capacitor, Cc, this topology can be used as a continuous-time comparator. Of course determining the best SiC op-amp or comparator topology and design will be a significant focus of the program along with obtaining accurate transistor/resistor models. Triangular-Wave Generation: The reference seen above can be used to bias a circuit to generate a triangle waveform, Figure 4.3a. The triangle-wave is generated using a source cross-coupled oscillator [12]. The two current sinks (NMOS current mirrors connected to Vbias) are used to alternately discharge the capacitor. Applying a constant current to a capacitor causes the voltage across the capacitor to change linearly. In other words, the voltage across the capacitor has a triangular shape and can be used with a comparator in a pulse-width modulation circuit (a fundamental block in a switching power supply). Note that the circuit seen in Figure 4.3a is self-oscillating which is important to minimize power consumption. High-Side Switch Implementation in NMOS: One of the major concerns with implementing highefficiency switching power converters using NMOS-only devices is the implementation of the high-side switch. Figure 4.3b shows one possible implementation of a high-side switch using NMOS depletion devices. AC coupling is used to shift the gate signal upwards. The NMOS-only driver circuit seen in Figure 4.1 is then used to drive the HV depletion switching device through a capacitor (the other MOSFET in the schematic with its source and drain shorted together). The resistive voltage divider is used to ensure that the gate-source potential goes negative enough for complete device shut off. The major concern with this circuit is oxide stress and thus long-term reliability. The large voltage associated with going directly from the line voltage (120 V RMS or 170 V peak) may appear across a gate oxide if a resonant switching converter topology is used with zero voltage switching. Since the SiC process technology is being developed along with circuit topologies for high-efficiencies, approaches such as devices with thicker oxides will be investigated to mitigate these problems. Task 5. Silicon Carbide Integrated Circuit (IC) Fabrication: Our goal is to fabricate single chip 4H-SiC power converter. To achieve this, we need to develop a high voltage power switch structure that can be integrated with low voltage control circuitry. The power switching elements are expected to operate at higher junction temperature (>200 o C) due to higher power density and reduced cooling requirements. Hence, the controlling circuitry, to be integrated on chip, must also be capable of operating at high temperatures. To realize a fully integrated, high performance power converter in 4H-SiC requires the following components. High temperature capable digital and analog circuit technology. Easy to control power switch and diodes to be integrated. Integration of high and low voltage components with sufficient isolation between them. Analog and Digital Circuit Technology: Cree has a significant effort towards the commercialization of the discrete power DMOSFET in 4H-SiC. During the developments, Cree established most of the infrastructure required to develop control and gate drive ICs, such as a) b) Fig. 4.3: a) Triangle-wave generator. b) High side switch. 9

12 Modeling, Design and Fabrication of 50W Single-Chip Integrated selective impurity doping process and gate oxidation process. A simplified cross-section of the power DMOSFET, and some common circuit configurations are shown in Figure 5.1. The digital/analog circuit configurations available from the Silicon Carbide power DMOSFET infrastructure include saturated/non-saturated enhancement load NMOS logic circuits [13], depletion load NMOS logic circuits [14], and CMOS logic circuits [15,16]. For digital applications, the NMOS circuits can be formed using much simpler fabrication processes. However, the logic levels in the NMOS circuits depend on the ratio between pull-up and pulldown transistors ( R = (W/L)pullup / (W/L)pulldown), and also a strong function of junction temperature. The CMOS circuits provide ratio-less logic levels, which is also independent of the junction temperature. However, the complexity of the fabrication process is much higher for CMOS devices. In both cases, the control of threshold voltage (VTH) is most important, since it controls the noise margins and the voltage transfer characteristics (VTC). (a) (b) (c) (d) Fig. 5.1: (a) Simplified power DMOSFET cross-section, and circuits using the same fabrication process. (b) Saturated enhancement load NMOS, (c) depletion load NMOS, and (d) CMOS inverters. The requirements for the devices used in analog circuits are slightly different. Although threshold voltage is very important, more emphasis is given to small signal load resistance, and transconductance (gm) of the devices. The characteristics of the devices used in the circuit must match quite closely with each other, and their repeatability is very important. The enhancement load NMOSFET device has quite low output resistance; hence, this configuration is not suitable for analog applications. The PMOSFET in the CMOS setup can serve as an excellent active load for analog circuits. It should be noted that a depletion mode NMOSFET, with gate shorted to source, can also function as the high output resistance active load, but requires simpler fabrication process compared to the PMOS load. One other factor to consider is the source/drain resistances of the devices. The p+ implants in 4H-SiC have a typical sheet resistance of 40 k per square [17], where n+ implants in 4H-SiC can have a sheet resistance of 160 per square [18]. The PMOS pull-up devices may have significantly lower current capability compared to the NMOS due to these internal resistances, and result in slower circuits. In addition, transconductance (gm) and parasitic capacitances must be minimized to improve the frequency responses. The gate length must be minimized, and gate oxide thickness and source/drain junction depths should scale accordingly. The improvement in the MOS channel mobility is also strongly desired. The challenges of SiC control and gate drive circuit development, and our approaches to overcome the issues, are summarized below. VTH control of the MOSFETs -Aluminum channel implants will be used to adjust VTH positive. -VTH of depletion mode transistors will be optimized for the analog designs using nitrogen channel implantations. Increase in NMOSFET transconductance 10

13 -Optimize nitrogen post oxidation anneals -Pursue novel anneal methods, including Phosphorus post oxidation anneals [19] -Optimize buried channel implants for higher MOS mobility, especially for the depletion load and high current gate drive buffer. Selection of circuit technology -Initial design will include all circuit technologies, including NMOS only and CMOS -Optimum circuit technology will be selected by initial experiments and modeling analysis Development of High Performance, Integrable Power Switch: The development of lateral Fig. 5.2: Simplified cross-section of a 4H-SiC RESURF lateral DMOSFET, integrated with NMOS circuits. Fig. 5.3: Simplified cross-section of a quasi-lateral 4H-SiC DMOSFET. power MOSFET is essential to the single chip power converters. The most common power MOSFET structure is the RESURF (REduced SURface Field) [20] lateral DMOSFET, as shown in Figure 5.2. Integrating low voltage components to a RESURF lateral DMOSFET is relatively easy, since the device is built on a lightly doped p-layer, which is grounded. A drawback of this structure is that the MOS gate packing density is very low compared to a vertical DMOSFET. This can be an issue in 4H-SiC because the n-channel MOS channel mobility is low (~15cm 2 /Vs), and the MOS channel resistance can dominate the on-resistance of the device. The other possibility is to form a quasi-lateral DMOSFET, as shown in Figure 5.3. This structure can provide increased gate packing density, compared to the RESURF structure. It is a non-planar device, which is not desirable for integration. However, for a blocking voltage of 200V, a trench edge termination can be used, and the etch depth will be limited to 2 3µm, which is manageable in terms of step coverages of metal lines or trench filling/planarization processes. Both structures will be evaluated, and the optimal structure will be selected by the end of the first year. A recent analysis of a 1200 V 4H-SiC DMOSFET revealed that the MOS channel resistance can account for up to 75% of the total on-resistance. For 200 V devices, where the drift resistance is less than 5% of that of the 1200 V devices, the MOS channel resistance is expected to account for more than 95% of the total on-resistance. Therefore, any improvement in the MOS channel resistance will have a big impact on reducing the specific on-resistance of the power MOSFET, resulting in smaller chip size and reduction in parasitic capacitances. High density designs, as well as improvements in MOS channel mobility are strongly desired. The approaches to optimize the power MOSFET performances are given below. Increase in NMOS channel density -Minimize cell pitch / design tolerances for RESURF DMOSFETs -Use advanced 2D device layouts for high channel density for quasi-lateral DMOSFETs Increase in NMOS channel mobility -Pursue novel anneal methods, including Phosphorus post oxidation anneals -Optimize buried channel implants for higher MOS mobility, allowing a small negative threshold voltage. This will be addressed by the design of control circuitry and gate drives. Process Integration and Developments of Design Rules and Models: One of the key items to develop in this program is to modify the power DMOSFET fabrication and generate an adequate design rules for the low voltage integrated circuits. The 4H-SiC power DMOSFET fabrication 11

14 Modeling, Design and Fabrication of 50W Single-Chip Integrated process, in the current form, is not optimum for the fabrications of high density integrated circuits. Figure 5.4 shows the process flow of a 4H-SiC power MOSFET, and how each step would be used for low voltage circuits. Here, RESURF type lateral power MOSFETs and depletion load NMOS circuits are used as an example. As shown in Figure 5.4, most of the regions in the NMOS circuit can be implemented with the RESURF power MOSFET process. In this example, we used the same power MOSFET threshold adjust implants on the pull-down transistor, and RESURF implants for the buried channel pull-up transistor to reduce process complexity and minimize processing cost. However, separate threshold implants maybe necessary to optimize the transistors for the low voltage circuits. (a) (b) (c) (d) (e) (f) (g) (h) Fig. 5.4: Process flow for a lateral power MOSFET and depletion load NMOS circuit. (a) Source/Drain implants, (b) p-well/vth adjust implants, (c) RESURF/buried channel implants, (d) field Oxide, (e) gate oxide, (f) gate deposition, (g) ohmic contacts, and (h) IMD and final metallization. The smallest feature definable using photolithography in the current process is approximately 1µm. For consistency and repeatability of high density circuits, using a minimum feature size of 2µm is recommended. Hence, starting with MOSIS Scalable CMOS design rules [21] or comparable design rules with λ = 1 µm, with minor modifications, will be a reasonable approach. Structures to test critical dimensions will be implemented on each generation of mask designs. These structures will be designed by CoolCAD, and Cree will also provide design for additional structures. The measurements of final dimensions, and the test structures, will be provided to CoolCAD. This feedback will help us make adjustments in the design rules, and tune in process biases for future mask designs. This will continue throughout the program, but we expect a stable design rule established within 3-4 iterations. It should be noted that for more accurate modeling of the ICs, precise models of interconnect lines are required, in addition to the device models. The test devices in each MOSFET fabrication run will include structures to characterize parasitic resistances, inductances, and capacitances of each layer, in addition to the MOS capacitors and MOSFETs. These structures will be designed by CoolCAD, and Cree s standard designs will also be implemented. After the completion of each fabrication run, initial characterizations of these structures will be performed at Cree. Measurement data as well as test chips will be provided to CoolCAD, where 12

15 optimization of the device models will be performed. Once the characterizations and model optimizations are complete, a device extraction task should be performed in the layout, which will update the circuits used in the SPICE simulations. The differences in simulated and experimental waveforms will be analyzed, and will be utilized for fine tuning of the device modeling. This will also benefit the understanding of the SiC physics. Threshold Voltage Control: The threshold voltage of NMOSFETs on 4H-SiC was evaluated as a function of the p-well doping concentration [22]. A lateral MOSFET structure, shown in Figure 5.5, (W/L=400µm/400µm) was used for this experiment. The p-well doping concentration varied from cm -3 to cm -3. The impurity doping was performed by either in-situ doping during the epitaxial growth, or aluminum ion implantation followed by a high temperature (>1600 o C) activation anneal. A 50 nm thick thermally grown oxide, with a post-oxidation anneal in NO was used as the gate dielectric. Figure 5.6 shows the I D -V GS characteristics, with a V DS of 50 mv, of the MOSFETs with different p-well doping concentrations. As expected, the IV characteristics shifted positive with increasing p-well doping concentration. The threshold voltage and peak MOS channel mobility are plotted as a function of p-well doping concentrations in Figures 5.7 and 5.8. It should be noted that the positive shift of threshold voltage can be achieved by using heavier p-well doping concentration; it is accompanied by a reduction in the peak MOS channel mobility. For the IC, we believe the optimum p-well doping concentration is approximately cm -3, which give a threshold voltage of 7 V, and a MOS mobility of 18 cm 2 /Vs. However, improvements in channel mobility are desired for greater performance of the control circuits and power MOSFETs. MOS Channel Mobility Improvements: The standard process for MOSFETs in 4H-SiC uses high temperature post oxidation anneals in NO, which provides acceptable MOS channel mobility but not sufficiently high for high performance devices. Recently, it was reported that the post oxidation anneals in POCl 3 gives very promising results with high MOS channel mobility of 90cm 2 /Vs being reported [19]. Cree performed a similar experiment in house, and verified that the phosphorus annealed gate oxide results in a higher MOS channel mobility than the gate oxides annealed in NO. The MOS channel mobility extracted from MOSFETs with phosphorus annealed and NO annealed gate oxides are shown in Figure 5.9, with Fig.5.5: Test MOSFET used in [22]. Fig. 5.7: Threshold voltage vs. doping. Peak Mobility (cm 2 /V*s) Increasing p-well concentration Fig.5.6: I D -V GS characteristics of the MOSFETs as a function of doping concentration at 27 o C Implanted Epitaxial E+15 1.E+16 1.E+17 1.E+18 1.E+19 - N A (cm -3 ) Fig. 5.8: Peak mobility vs. doping. 13

16 phosphorus annealed oxide showing more than double the peak mobility than that of the NO annealed oxide. Phosphorus post oxidation anneals, and optimizations of NO anneals will be pursued. Figure 5.10 shows the I D -V GS characteristics of a buried channel MOSFET in 4H-SiC [23]. The total charge in the buried channel was cm -2. A peak MOS channel mobility of 192cm 2 /Vs was measured at room temperature, and a pinch-off voltage of -2V was observed. The effects of negative body bias, which has an equivalent effect of reducing the buried channel charge, are also shown. The results suggest that a substantial increase in MOS channel mobility, with a positive threshold voltage, can be achieved by optimizing the buried channel implants in 4H-SiC MOS devices. This method will also be used to improve the power MOSFET performance, and to provide a suitable active load for the control circuitry. Demonstration of IC Technology in Silicon Carbide: High temperature CMOS technology in Silicon Carbide operating at junction temperatures up to 350 o C was developed during a Ballistic Missile Defense Organization sponsored Phase II SBIR program, conducted during the Fig.5.9: MOS channel mobility from 4H-SiC MOSFETs with P- and NOpost oxidation anneals. Fig. 5.10: Channel mobilities from buried channel 4H-SiC MOSFETs. W/L=100µm/100µm [23]. period June 1997 December An n-well based CMOS technology on 6H-SiC was developed. The PMOS devices were formed in nitrogen implanted n-wells, and the NMOS devices were formed on lightly doped p-type epilayer grown on heavily doped p-type substrates. The thickness of the gate oxide was approximately 30nm. A PMOS threshold voltage of -3.5V, and a p-channel MOS mobility of 3.6cm 2 /Vs were achieved. On the NMOS side, an NMOS threshold voltage of 3.3V, and an n-channel MOS mobility of 26.3cm 2 /Vs were measured. The minimum channel length was 4 m. The high temperature SiC op-amp schematic and photomicrograph are shown in Figures 5.11 and 5.12, respectively. The circuit comprised of a differential gain stage, a high gain cascode gain stage and a source follower output buffer stage. The amplifier is compensated by an on-chip capacitor of 9pF formed with the n + source/drain implant for the bottom plate, the gate oxide and the gate metal. This circuit was designed to operate on a single supply voltage of 12V and achieve at least an open loop gain of 80dB, a slew rate of 1V/µs, a unity gain frequency of 1MHz and a phase margin of 60 degrees when driving a 20pF load. Figure 5.13 shows the unity gain frequency (UGF) of the op-amp. In a unity gain configuration, a 200mV pp sinusoid was applied at the input, and the frequency was increased until the output degraded to about 142mV pp or 71% of the input signal. This is the point the voltage gain is 3dB lower than at low frequency. With an I REF = 30µA, a UGF of 289kHz was observed. The large signal slew rate for a load capacitance of about 15pF is 1-2V/µs, as shown in Figure Fabrication of test structures, power converter sub-circuits, and control sub-circuits will be performed throughout the program with a goal of achieving an all SiC power converter that meets and possibly surpasses the stated proposal goals. 14

17 Task 6. Thermal Modeling and High Temperature Packaging: The high speed power converter ICs developed in this program will require equally novel packaging to improve thermal-electrical performance and to reduce parasitics. This packaging is expected to be planar, high density and utilize stacked and embedded components. This integrated three-dimensional power supply in package (PSiP) design will unite switching devices, embedded passives, planar inductors, and driver circuitry into a single, reliable unit. Further, to achieve high switching and temperature operation, and to optimize thermal and electrical performance, we plan to develop electro-thermal, packaging, reliability and fatigue simulators, as well as to perform thermal/mechanical testing. Subtask 1: Die and Package Level Thermal-Electrical Modeling: A detailed consideration of the coupled thermalelectrical effects at power chip and module levels is crucial for the performance prediction of power devices. Any temperature increase may adversely affect the electrical performance, and lead to a catastrophic failure once a critical temperature is reached beyond which the negative feedback between the electrical and thermal dynamics turns into a positive feedback, causing a thermal runaway and irreversible damage to power IC components. To determine self-heating at the chip and package levels, we will develop detailed distributed thermal simulators that are based on differential and lumped versions of the heatflow equation. At the device level, we solve the differential heat-flow equation, and couple it to semiconductor performance equations. At the IC level, we use the lumped thermal network to solve for the temperature variations on the chip surface. Finally, at the package and module levels, we combine the thermal network that is used to describe the power device with those used for the package and power module. At each level, we provide a feedback to the electrical performance of the power devices, and iterate Fig. 5.11: CMOS op-amp schematic. ESD protection circuits for -v IN, +v IN and I REF are not shown. -v IN +v IN V SS I REF V DD Fig. 5.12: Microphotograph of a completed SiC CMOS OP-AMP. Fig. 5.13: Input/output (top/bottom) traces of a SiC UGF for V DD =7V, V SS =-7V & I REF ~30µA. Fig. 5.14: Input/output (top/bottom) traces of the OA slewing 1-2V/µs for V DD =7V, V SS =-7V & I REF ~30µA. between the electrical and thermal levels until a self-consistent solution is obtained [24-27]. Figure 6.1 depicts a thermal IC we designed, laid out, and fabricated for initial development of our thermal-electrical simulator. Figure 6.2 shows an example thermal map, our in-house simulator calculated for a Cree fabricated 20A 1200V 4H-SiC DMOSFET in a TO247 package attached to an aluminum heat sink. The power versus temperature characteristics was first calculated by carrying out mixed-mode simulation of a boost converter circuit. A network of thermal resistors was then constructed using information about the thermal conductivity of the die, the package and the heat sink. In this program, after we select SiC devices for the power IC v O 15

18 in the second year, we will perform thermal analyses for the devices and the die. Also, thermal-electrical simulators will be developed to aid package development, in the second and third years. Subtask 2: On-Chip Temperature Sensor Design: To calibrate our thermal-electrical models, and to determine the localized power IC temperatures, we plan to design and fabricate on-chip temperature sensors, as shown in Figure 6.1. This will provide readings for localized temperatures, Fig. 6.1: Temperature IC and enable us to quantify die heating in excess of the designed, laid laid out and out fabricated and ambient. These on-chip thermometers will also enable us to for fabricated our thermal for our simulator thermal more accurately extract temperature dependent power calibration simulator calibration [24]. [24]. MOSFET performance, to guide the power IC designs that are less susceptible to hot spots, as well as to investigate the effects of different packages and encapsulates on the internal temperature map. Previously, we have developed on-chip thermal sensors for silicon ICs to access the effects of metal layout on the heat flow [24], and to obtain a temperature resolution that is generally much higher than the commercial infrared cameras can achieve for an IC during operation. As temperature sensors, we used diodes that have a large Fig. 6.2: Calculated 6.2: temperatures Calculated temperature coefficient of resistance which indicates that the (above temperatures ambient) (above of a power ambient) IC diode current changes significantly with temperature and of a package power [25]. IC and package (specifically, it varies exponentially with temperature). Also, poly resistor lines can be used to measure the localized IC temperatures; however, the temperature coefficients of resistors are less than those of diodes. To be used in the SiC power converter IC, we will design, lay out, fabricate and test SiC diodes and poly lines, and embed them close to structures-under-test to verify their actual performance and temperature. Subtask 3: High Temperature Packaging: Interconnection will be accomplished using new technologies including integrated modular approaches. Further, this high density package will also require thermal management as well to dissipate the high heat loads that will accompany such increases in density. Without improved cooling, the increase in power dissipation density can lead to increases in device power losses, potentially leading to thermal runaway and eventual failure of the device. High junction temperatures also tend to degrade the device reliability by increasing their susceptibility to failure. It is anticipated that such a packaged device unit will be quite thin and minimize the number of packaging layers required to perform the electronic functions in order to reduce the passive thermal resistance between the power switching devices and the exterior cooled surface. Even with advanced cooling techniques [28], the high density of the package may cause the temperatures inside the package to become quite elevated, leading to the use of packaging materials that have both high thermal conductivity and high thermal stability. This may include such materials as copper heat spreaders, polyimide boards, and novel low temperature processed, high temperature stable attach materials [29]. Polyimide boards provide the flexibility of standard organic board design with a low dielectric constant for high signal speed and are stable to 300 o C. 16

19 Packaging designs also need to be robust against high fields and high current densities. These issues would be addressed first by using design rules that eliminate sharp corners and long, close, parallel runs for all metal traces, along with modeling field strengths for all vias and interconnections. Second, conditions of silver migration (the formation of thin silver filaments at high temperatures and high voltages) and metal electromigration (the preferential motion of some metals (e.g Pb, Sn) in the direction of electron flow) would also be considered in all attach and trace material selections. [30, 31]. Even with the use of advanced packaging techniques, the importance of package reliability under the harsh environmental and operational loading conditions typical of power electronics applications will require the calibration of physics-offailure based reliability models for failure mechanisms specific to the designs, and validation of the models by accelerated testing. Models for these failure mechanisms incorporate both stress model components, which take into account module design, and damage model components, which are based solely on material properties. [32,33] Concurrent with the modeling effort is a program of materials characterization that permits the determination of the fatigue durability properties of interconnect materials. Further, the PoF models combined with the materials characterization can be used to assess the reliability of electronics during the design phase, before a single prototype is manufactured or procured. Using this approach, the reliability of power converter designs can be assessed and compared early, quickly and at a minimum cost. Combining these PoF models with CoolCAD s electrothermal modeling provides a tool that can be used to assist in the complex tradeoffs that must be optimized in choosing component, package, and cooling system technologies and integrating them into a power packaging and thermal management solution to achieve cost, performance, and reliability goals. Throughout the program, we will (1) package ICs developed in this program for test using standard packaging technology (2) characterize relevant failure mechanisms in existing < 50 W power converter packaging. (3) characterize phenomena responsible for aging and fatigue effects in the packaged single chip SiC IC power converters; (4) suggest new package designs for high speed power converter IC s (5) utilize thermal-mechanical electrical models. Task 7. Testing and Design Validation: During the three years of this project, we plan to implement detailed test procedures at all levels of the SiC power converter IC design and development process. These tests will include on-chip die testing of individual devices, on-chip testing of sub-circuits, on-chip testing at high temperatures, packaged device and circuit testing at high temperatures, and PCB level testing of finished product at high temperatures. The final prototype SiC power converter ICs will be packaged and integrated with some passive components on a high temperature PCB to create evaluation boards for our product. These evaluation boards will be made available along with the packaged IC itself through our company to our beta test site partners. Throughout the three years of this project, we will be constantly interacting with government laboratories such as the Army Research Laboratory (ARL), Air Force Research Laboratory (AFRL), Oakridge National Laboratory (ONL), and others, who will have applications for a high temperature single chip SiC power converter. Further, we will develop partnerships with oil exploration companies such as Baker-Hughes and provide them with the prototype ICs and evaluation boards for testing and validation purposes. The evaluation boards and ICs will be made available free of charge to various universities for evaluation. Testing of our products will be carried out throughout the project to enable data collection for optimizing our models, process, circuit designs, and package designs. Here we briefly summarize the electrical testing tasks we have planned for this project. 17

20 Subtask 1: High Temperature On-chip (Bare Die) Electrical Testing: Electrical characterization of SiC MOSFETs, lateral power DMOSFETs, poly-silicon resistors and other on-chip components will be carried out using a probe station and semiconductor parameter analyzer. We plan to use a 4155 semiconductor parameter analyzer we have access to right now for the initial I-V testing. For more sophisticated IV and CV test and characterization we plan to buy a better semiconductor parameter analyzer (eg. Agilent B1500A). We will be using Agilent IC-CAP parameter extraction software for measurement and parameter extraction. We will also be carrying out high temperature on-chip measurements of sub-circuits such as inverters, op-amps, and gate drives. These electrical tests will provide us with device characteristics, temperature variations, statistical variation across die and process variations. The results of these tests will be used to validate and improve our device models and design better circuits. Evaluating high temperature stability of the chips will be a critical component of our tests. Subtask 2: High Temperature Packaged Chip Electrical Testing: Long term high temperature testing of packaged SiC ICs will be carried out during the course of this project. Long term testing of the packaged chips will include thermal cycling as well as voltage and current stressing. These tests will help us to optimize the IC for operation in harsh environments. Subtask 3: High Temperature Evaluation Board Design and System Level Testing: During the last part of the project, we will concentrate on creating evaluation boards for all the SiC ICs we fabricate. These evaluation boards will be fabricated on high temperature PCBs and will include high temperature passives required for the full application. These evaluation boards will be provided to our partners acting as beta test sites for real-world applications. The evaluation boards will also be provided to companies such as Baker-Hughes (manufacturers of oil well drilling equipment) and others who have need of high temperature small form-factor power electronics. The evaluation boards will also be made available to research laboratories and legitimate university teams investigating high temperature electronics and systems. c. Preliminary Results: Significant amount of research in Silicon Carbide electronics has been carried out by members of this team. Specifically previous research and development has been carried out in the areas of 2D device modeling [1-8], Verilog-A based compact modeling [9,34], process characterization [35-40], device fabrication [35-40] and high temperature packaging [28-33]. The team at CoolCAD has published several papers on characterization of 4H-SiC lateral and vertical MOSFETs. Detailed physics based modeling and simulation capability has been developed for SiC MOS devices. Further, team members at CoolCAD have worked with Verilog-A based behavioral modeling for SiC devices [25], cryogenic operation of Silicon MOSFETs [8,34,41] and DC-DC converter circuits [25]. Cree Inc. has several years of experience on fabrication of SiC MOSFET structures. Cree already has SiC Schottky diodes in production and they are used in a variety of high power converter systems [35-39]. Cree is also close to releasing a 1200V 20A SiC DMOSFET for high temperature operation. Cree also has had previous experience with developing simple integrated circuits in SiC [22-23]. These preliminary results on SiC device modeling and fabrication will serve as the basis of building more sophisticated compact models and integrated circuits that are required for successful completion of this project. Details of our previous work and results are given in the description of the tasks above. 18

21 d. Significance with Respect to FOA Requirements and Targets: This project addresses the requirement of single-chip power converters suitable for applications including solid state lighting drivers, solar micro-inverters and computer power supplies. This project aims to create 50W DC-DC and AC-DC power converters ICs using Silicon Carbide that are suitable for operation at high temperatures. The project seeks to extend the secondary requirements specified in the solicitation by designing integrated circuit power converters capable of working at >200 o C that can be used in down-hole drilling applications, geothermal measurement and communications, satellites, and also high temperature power sub-systems in aircraft and hybrid/all-electric vehicles. The sub-circuit components on the chip will be designed such that with minimal reformulation of the layout, we can create DC-DC as well as AC-DC converters. The proposed SiC power converter IC will be designed for 5MHz switching speeds and will have conversion efficiency in excess of 93%. We will implement voltage and current regulation using an analog feedback and control circuit. The chip will have an integrated gate drive capable of switching at 5MHz and will drive a lateral power MOSFET on the same die. This integration of control circuit, gate drive and power device on the same die represents a significant advancement in Silicon Carbide technology and will lead to a wide range of IC products for high power electronic applications. Finally, the AC-DC and DC-DC converter ICs will have thermal runaway protection, over-voltage and short circuit protections, soft-start and auto shutdown capabilities as part of its design. With a design goal of 93% efficiency at 50W, and a maximum 5mm 2 die area, the power density for the chip is estimated to be in the 100W/cm 2 range. e. Milestones: Following the major tasks and milestones for our project. The first table shows the tasks and milestones for design, and testing of the power converters, op-amps and gate drives. The second table shows a milestone chart for the fabrication runs for the three years. Program Element 1: Develop a 50W Single Chip Power Converter using Silicon Carbide for operation at high temperatures with a 5MHz switching frequency and >90% conversion efficiency Qtr. 1,2 3,4 5,6 7,8 Table 1. Overall Program Milestones Major Tasks Key Milestones & Deliverables 1. High temperature measurements of SiC chips 1. SiC Verilog-A high 2. High temperature Verilog-A model temperature models development 2. SiC test chips with discrete 3. TCAD design of SiC lateral power MOSFET devices 4. Fabrication of SiC chips with test devices 3. Q1 and Q2 reports 1. Sub-circuit designs using Verilog-A models 1. Final design of power 2. PDK development for SiC process MOSFET 3. Fabrication of op-amps in SiC 2. Selection of logic process 4. Improved design of lateral power MOSFET 3. Q3 and Q4 reports 1. Next generation design of op-amps in SiC 2. Level translators, error amplifiers and gate drive circuit design 3. Thermal mapping of sub-circuits in SiC 4. Parasitic effects extraction and improvement of device models and PDK 1. Fabricate power converter with gate drive, control circuit and power device 2. Thermal mapping of the power IC o C packaging and test of SiC IC 1. Op-amp test results 2. Integrated gate-drive 3. Thermal mapping of SiC ICs 4. Improved SiC PDK 5. Q5 and Q6 reports 1. First version of SiC power converter IC 2. Packaged ICs for 175 o C 3. Q7 and Q8 reports 19

22 2: Develop a PWM gate drive integrated circuit with voltage and current control using Silicon Carbide for operation at high temperatures 3: High temperature high gain operational amplifier IC using Silicon Carbide 9,10 11, 12 5,6 7,8 9,10 11, 12 3,4 5,6 7,8 11, Fabrication of second generation of SiC power converter IC 2. Stress and thermal cycling tests of high temperature packaging 3. Evaluation board for SiC IC testing 4. >250 o C package design for SiC IC 5. Finalize process for SiC IC fabrication 1. Final version of SiC power converter IC 2. Beta testing of SiC power converter IC at partner locations 3. >250 o C lab and on-site beta testing of IC 1. Fabricate sub-circuits like inverter chains and alternative gate drives 2. High temperature testing of the gate drive 1. Integrate gate drive and control circuit o C testing of gate drive and control circuit with an off-chip power device 1. Final version of PWM SiC gate drive with voltage and current control 2. Partner site testing of SiC PWM driver IC 3. >250 o C package design for SiC driver IC 1. Site testing of 175 o C, >250 o C SiC gate driver 2. Ready for manufacture SiC PWM gate driver 1. First generation op-amp in SiC 2. High temperature testing of SiC op-amp 1. Second version of SiC power IC 2. Datasheet for SiC power IC 3. Stress and thermal cycling results 4. Evaluation boards 5. Q9 and Q10 reports 1. Final version of SiC power converter IC 2. Final datasheets 3. Q11 and Final reports 1. First version of integrated gate drive in SiC 1. High temperature test results of a PWM SiC IC gate driver 1. Final version of SiC PWM gate driver and control IC 2. Test results at 175 o C 1. Test results of >250 o C 2. Evaluation board for SiC PWM gate driver 1. High temperature test results of SiC op-amp 1. High temperature test results of SiC op-amp 1. Packaged SiC op-amp 2. Evaluation board 1. Design and fabrication of second generation of SiC op-amp 1. Fabrication of final version of op-amp 2. Testing of SiC op-amp at 175 o C 1. Testing of SiC op-amp at >250 o C 1. Final SiC op-amp IC Program Element SiC IC fabrication & integration of power converters, gate drive and op-amps Major Qtr Tasks 1, 2 SiC IC Run #1 3,4 SiC IC Run #2 Table 2: Fabrication Milestones: Key Milestones & Deliverables Generate initial design rules, Complete initial mask design Complete SiC MOSFET Run #1, Analysis of devices from Fab Run #1 Establish IC design rules based on experimental results Delivery: Discrete devices, including lateral MOSFETs and MOS capacitors, from SiC MOSFET Run#1 Design/Process modification for SiC MOSFET Run #2 SiC MOSFET Fab Run #2 Delivery: Discrete devices (low and high voltage) and simple gates on ICs 20

23 5,6 SiC IC Run #3, #4 7,8 SiC IC Run #4, #5 9, 10 11, 12 SiC IC Run #6,#7 SiC IC Run #8 Complete mask design for Run #3 for small scale integration SiC MOSFET Fab Run #3 Redesign SiC MOSFET mask for Run #4 based on feedback SiC MOSFET Run #4 Delivery: SiC test chips containing analog and digital functional blocks, high voltage MOSFETs On-wafer device and sub-circuit evaluation SiC MOSFET Run #5 and Start SiC MOSFET Run #6 Redesign SiC MOSFET mask for Run #6 based on feedback Delivery: SiC chips with small scale power converters, functional blocks, and discrete devices Complete SiC MOSFET Run #6 Delivery: SiC power IC with 1/3 power rating and functionality SiC MOSFET Run #7 and redesign SiC MOSFET mask for Run #8 Delivery: SiC power IC with 2/3 power rating and functionality Complete SiC MOSFET Run #8 Delivery: SiC power converter chips with full power rating f. Performance Team: Dr. Neil Goldsman, Dr. Siddharth Potbhare, Dr. Akin Akturk and Dr. Jim McGarrity are the key members of the CoolCAD Electronics team. Goldsman and Akturk are also faculty members at the University of Maryland. The CoolCAD team members are internationally recognized experts in device and material modeling. They have developed the world s most sophisticated device and thermal modeling codes for SiC transistors, which has helped give rise to approximately 50 publications in the area, under an Army Research Laboratory supported program at UMD. More recently they have developed compact models for SiC circuits under the support of an NSF SBIR program. Drs. David Grider, Sei-Hyung Ryu and Anant K. Agarwal will lead the Cree team, which clearly stands out as the world s leading group in the field of SiC device processing and fabrication. They have a combined experience of more than twenty years in SiC process development. They have published approximately fifty papers and hold more than twenty patents in the area of SiC device and material processing. The University of Maryland team will be lead by Dr. Patrick McCluskey, who is an expert in electronics packaging design for high temperature and high power applications as well as the computer aided design of risk assessment in microelectronics. He has numerous publications in the area including the editorship of the book High-Temperature Electronics. Dr. R. Jacob Baker is a world recognized expert in IC CMOS design. He is the author of CMOS, Circuit Design, Layout and Simulation, which is one of the leading electronic texts in the area with more than 30,000 copies being sold world-wide. Dr. Baker has 98 patents granted and over 100 pending in circuit design, as well as numerous publications, including a best paper award from the IEEE Power Electronics Society. 21

24 2.4 Transition/Commercialization Strategy Enabling Technology for New Commercial Development: The development of SiC power converter circuits on a single chip represents a transformational technology that will extend the microelectronics revolution to significantly higher powers and temperatures. This will enable the development of numerous products that will satisfy the need of efficient power and/or high temperature electronics packaged with minimal form factors. Current Status (TRL 4) Current Status: SiC MOSFET fabrication process technology has been developed but not fully optimized. State of the art device modeling tools for SiC MOSFETs have been developed. Circuit designs for fundamental blocks including op-amps, gate drives, and references have been put forth, but require optimization with newly developed models. Phases of Development (TRL 4-7) The following first five phases of development will be achieved during the ARPA-E program. The sixth stage listed below is the manufacturing phase which will be reached after prototypes are delivered at the end of the ARPA-E program. 1. Performance of lateral control devices and power devices should be further optimized for single chip power converter prototype. 2. Detailed characterization of the devices needs to be performed 3. Compact models, design rules and a process design kit need to be developed. 4. Power converter IC design needs to be finalized and then prototyped. 5. Die packaging needs to be optimized for reliability, as well as electro-thermal-mechanical performances. 6. Volume manufacturing of SiC ICs needs to be implemented for commercialization. Market: According to [42], the global electronics market is approximately $2 trillion. The world market for electrical power supplies is approximately $15 billion [43], while the market for power management and driver integrated circuits is in the range of $11 billion [44]. This should yield a high temperature, high/power integrated circuits market that is uniquely satisfied by SiC MOSFET based integrated circuits to be in the $5 billion range. Applications for SiC ICs will be found in single chip power converters for oil-well drilling applications, solar panels, LED lighting as well as high temperature sensors and control electronics. The initial commercialization plan will focus on identifying customers in the down-hole drilling, solid state lighting and solar panel micro-power converter areas. We have begun initial interactions with potential customers including government laboratories and oil well drilling equipment manufacturers. We will provide highly efficient SiC IC s of extremely small form factor which will enable creation of final systems with compact packages, without the need for bulky external power conversion circuits. This will significantly increase system efficiency while reducing cost. In addition to these specific products, perhaps even more important in the long term will be that this program will be instrumental in developing the technology of SiC integrated circuits which will find customers in many of the markets discussed above. Subsequent investment to reach these markets will be totally within the realm of the major team members in this program since most of the development will be achieved during the present program. 22

25 2.5 Additionality and Risk Critical Milestone of High Impact Technology: This project enables numerous energy savings applications and high temperature operation of electronics in industries. The proposed project is very important since it represents the next critical major milestone in electronics development for SiC. Currently, SiC electronics development has almost exclusively been focused on discrete power transistors, with the control electronics developed on another chip, which is typically formed out of Silicon on Insulator. However, to move the technology forward and realize the true benefits of SiC, integration of power electronics and control electronics on a single chip needs to be realized. Reaching this critical stage will allow for the development of an entirely new area of electronics that is based on its ability to handle higher power and high temperatures in a single location. One of the key benefits of realizing this critical technology is that it will allow for the miniaturization and increased efficiency of power converter components and thereby enable entirely new applications and even industries. For example, low voltage lighting applications often require the use of bulky power converters to switch from relatively high AC line voltages to just several volts DC. If such power transformation can be achieved in very small volumes and without the waste of energy, it will greatly facilitate the adoption of highly efficient lighting systems. Thus, the development of very small, highly efficient SiC power converter integrated circuits can provide a pivotal component that can enable an entirely new highly efficient emerging solid-state lighting industry. Other examples include integration of SiC high temperature sensors and control electronics for applications in oil-well drilling, aircraft engines, hybrid vehicles, nuclear reactors and geothermal energy sources. Risks and How ARPA-E Investment Overcomes Them: The devotion of resources to this technology represents investment related risks for CoolCAD Electronics and Cree Inc. Currently, Cree Inc. and CoolCAD Electronics have invested their resources in the design, analysis and fabrication of very high power discrete transistors. These new transistors are about to enter the market soon. Thus, most resources are being directed toward achieving market penetration for SiC discrete devices. There has been a relatively costly research and development stage for the SiC discrete devices. Therefore, until discrete SiC devices begin generating revenues which can be reinvested in R&D, funding will not be available to perform the next critical step which is the integration of SiC power and control electronics into a single unit. This is not expected to take place until 3-5 years from now. For small or startup companies like CoolCAD, venture capital will be extremely scarce with respect to limited valuation during these conservative economic times since the product is at an early stage. Thus, to continue providing entrepreneurial incentives, CoolCAD chooses to invest in its own in-kind labor and complement that with ARPA-E and resources from Cree, University of Maryland and Boise State University, to actively succeed in this program. To leverage the ARPA-E investment Cree will commit the services of highly trained process engineers and scientists who have a unique specialization in SiC fabrication. CoolCAD Electronics will provide the unique capabilities of high trained scientists and engineers who have specialization in the modeling of SiC based devices and circuits. The University of Maryland and Boise State will provide highly trained professors and facilities whose time will be largely leveraged by investments from the States of Maryland and Idaho. 23

26 2.6 Management Plan All the team members associated with this project have a long history of working together on Silicon Carbide device design and characterization. CoolCAD members have worked with Cree and the US Army Research Laboratory on characterizing SiC lateral and vertical power MOSFETs. For this particular project, we plan to actively work together and share information and progress on the tasks on a regular basis. A website will be established for project where reports and meeting notes will be shared and monthly and quarterly reports uploaded. Regular visits between CoolCAD, Cree, Boise State and UMD team members will be organized so that the progress in all aspects of the project is closely tracked. Point of Contact from Each Member Team: (1) CoolCAD Electronics: Dr. Neil Goldsman; (2) Cree Inc: Dr. David Grider (3) Univ. of Maryland: Dr. Patrick McCluskey (4) Boise State Univ.: Dr. R. Jacob Baker Roles of Team Members: CoolCAD Electronics: (1) SiC power MOSFET design using detailed physics based modeling; (2) Device characterization and parameter extraction; (3) SiC device and circuit model development; (4) Co-develop the SiC PDK with Cree and Boise State; (5) Perform circuit design together with Boise State; (6) Team with Boise State to implement the PDK in the VLSI Simulator Electric for creating layouts and design rule checks (DRC). Cree Inc: (1) Perform process development for SiC IC s; (2) Process design and fabrication of SiC lateral power MOSFET for fast, low loss switching of power converters; (2) Fabricate regular and buried channel SiC N-MOSFETs, PMOSFETs and CMOS circuit blocks (3) Fabrication of SiC integrated circuits; (4) Provide CoolCAD with devices for testing, modeling and co-development of PDK. Boise State University: (1) Develop designs of advanced integrated circuit topologies for power converters using SiC; (2) Design and develop fundamental circuit blocks for fabrication using compact models from CoolCAD; (3) Work with CoolCAD to develop PDK and establish Electric VLSI design environment. University of Maryland: (1) Package test IC s; (2) Characterize existing packaging with respect to thermal cycling, wire bonding to establish limits. (3) Understand phenomena responsible for aging and fatigue effects in packaged SiC IC s; (4) Develop new package designs for high speed power converter IC s (5) Work with CoolCAD to combine thermal-mechanical electrical models into design software. Critical Handoff and Interdependencies between Team Members: The overall project will be managed by CoolCAD (POC Neil Goldsman). There will be continuous communication between team members. Simple test circuit designs and layouts will be generated by CoolCAD and Boise State and then provided to Cree for fabrication. Cree will provide the test IC s to CoolCAD for probe testing and evaluation. Model development for the devices will then performed by CoolCAD and then transmitted to Boise State for circuit design. In addition, where necessary, CoolCAD will transfer chips to UMD for packaging, package testing and design. New circuit designs and layouts will be provided by Boise State and CoolCAD and the cycle will be repeated for prototype optimization. Each year the complexity of the chips will be increased. The last year focus will be on prototyping the full power converter circuit. 24

27 2.7 Budget Summary: Qtr. Start Milestones Setup detailed progress charts with team members 1. SiC Verilog-A high temperature models; 2. SiC test chips with low and high power devices; 3. Q1 & Q2 reports 1. Final design of power MOSFET; 2. Final selection of logic device process; 3. Q3 and Q4 reports 1. Test results of SiC opamp; 2. Integrated gatedrive in SiC; 3. Power analysis and thermal mapping of SiC IC's; 4. Improved SiC PDK; Q5 and Q6 Reports 1. First version of SiC power converter IC; 2. Packaged IC's for 175 o C operation; 3. Q7 and Q8 reports 1. Second version of SiC power IC; 2. Datasheet for SiC power converter IC; 3. Stress and thermal cycling results; 4. Evaluation boards; 5. Q9 and Q10 reports 1. Final version of SiC power converter IC; 2. Final datasheets; 3. >250 o C version of SiC IC package; 4. Q11 and Final Reports Total Project Cost: $ 4,500, Total ARPA-E Funding: $ 3,600, Total Cost Share: $ 900, Major ARPA-E Payments (in $) Equipment Purchases CoolCAD Cree UMD Boise State CoolCAD: Semiconductor Parameter Analyzer , , , , CoolCAD: LCR Meter 145, , , , CoolCAD: Thermal Imager CoolCAD: High Temp. Oven 147, , , , , , , , , , , , , , , , End Total Payments ($): 899, ,099, , ,

28 3. APPENDICES Appendix 1: Qualifications, Experience and Capabilities a. Personnel Involved CoolCAD Electronics LLC: Dr. Neil Goldsman, Dr. Siddharth Potbhare, Dr. Akin Akturk and Dr. Jim McGarrity are the key members of the CoolCAD Electronics team. Goldsman and Akturk are also faculty members at the University of Maryland. The CoolCAD team members are internationally recognized experts in device and material modeling. Team members have developed the world s most sophisticated device and thermal modeling codes for SiC transistors, which have helped give rise to approximately 50 publications in the area, under an Army Research Laboratory supported program at UMD. More recently they have developed compact models for SiC circuits under the support of an NSF SBIR program. Cree Inc.: Dr. David Grider, Dr. Sei-Hyung Ryu, Dr. Anant K. Agarwal and Dr. Sarit Dhar are the key members of the Cree team, which clearly stands out as the world s leading group in the field of SiC device processing and fabrication. They have a combined experience of more than twenty years in SiC process development. They have published approximately fifty papers and hold more than twenty patents in the area of SiC device and material processing. University of Maryland: The University of Maryland team will be lead by Dr. Patrick McCluskey, who is an expert in electronics packaging design for high temperature and high power applications as well as the computer aided design of risk assessment in microelectronics He has numerous publications in the area including the editorship of the book High-Temperature Electronics. Boise State University: Dr. R. Jacob Baker is a world recognized expert in IC CMOS design. He is author of the book CMOS, Circuit Design, Layout and Simulation, which is one of the leading electronic texts in the area with more than 30,000 copies being sold world-wide. Dr. Baker has 98 patents granted and over 100 pending in circuit design, as well as numerous publications, including a best paper award from the IEEE Power Electronics Society. Detailed qualifications of these key team members are given next. 26

29 Neil Goldsman, Ph. D President, CoolCAD Electronics LLC Point of Contact Professional Summary: Dr. Neil Goldsman is Co-Founder and President of CoolCAD Electronics. He is also a professor in the Electrical and Computer Engineering Department at the University of Maryland at College Park. At the University, Dr. Goldsman directs the Mixed Signal VLSI Design Laboratory, the Semiconductor Simulation Laboratory. His recent work has focused on ad-hoc sensor networks, high temperature and cryogenic electronics, power electronics and semiconductor device modeling. His main focus lately has been on SiC device modeling and electronics. He regularly serves on the executive, technical and organizing committees of leading international professional conferences, including the International Semiconductor Device Research Symposium and the International Conference on Simulation of Semiconductor Processes and Devices. Prof. Goldsman was the technical director for the Maryland Governor's Institute of Technology program. His research has attracted more than $4 million of support to the University of Maryland. His work has been sponsored by leading governmental and industrial organizations including NSF, SRC, NSA, ARL, ONR, ARO, DHS, NIH, Intel Corp. and LSI Logic Corp. Dr. Goldsman is the recipient of the IEEE Dasher Award; the NSF Research Initiation Award; the University of Maryland s George Corcoran; Invention the Year and Business Plan Awards; and Cornell University s Post Foundation Scholarship. Goldsman has published more than one hundred fifty peer-reviewed technical papers, and supervised the design of over fifty ICs. He has authored two electronics texts that have been used for courses at the University of Maryland. Recently, Dr. Goldsman has focused on commercializing his research, whereupon he received 8 patents and provisional patents in the last several years. Dr. Goldsman is also a serial entrepreneur. In 2004, Dr. Goldsman and a colleague founded TRX Systems, where he served as president. In 2007 he sold his portion of TRX, and focused on establishing two new high-tech companies, namely CoolCAD Electronics LLC and FlexEl LLC. Dr. Goldsman received his Ph.D from Cornell University with a minor in Applied Physics and major in Electrical Engineering. 1. Education 1989 Ph.D. in Electrical Engineering, Cornell University 1984 M.E. in Electrical Engineering, Cornell University 1981 B.A. in Physics, Cornell University 2. Work Experience 2006 Present: President: CoolCAD Electronics LLC 1989 Present: Professor: Department of Electrical and Computer Engineering, University of Maryland, College Park Director: Mixed Signal Design Laboratory: ECE Dept. Univ. of Maryland. Director: Semiconductor and Nanostructure Device Modeling Laboratory: ECE Dept. Univ. of Maryland : Co-Founder & President: TRX Systems (Employs approx. 10 FTE.) 2008 Present: Co-Founder: FlexEl, LLC (Employs approx. 5 FTE) 27

30 3. Awards and Honors 1. Post Merit Scholarship awarded by the Post Foundation 2. George Corcoran Award: University of Maryland EE faculty member for outstanding contributions to electrical engineering education. 3. NSF Research Initiation Award: Project Title: Efficient and Comprehensive Semiconductor Device Modeling.'' 4. Best Professor of the Year Award 5. Benjamin Dasher Award for best paper at IEEE Frontiers in Education Conference : Member of Technical Committee for International Conference of Simulation of Semiconductor Processes and Devices : Device Committee Chair: International Conference of Simulation of Semiconductor Processes and Devices : Program Chair: International Semiconductor Device Research Symposium : Symposium Chair: International Semiconductor Device Research Symposium Invention of the Year Award, University of Maryland. Publications Dr. Goldsman has published more than 150 papers in the leading peer-reviewed scientific journals and proceedings. He has also given over a hundred professional presentations, including numerous invited talks. Representative publications are listed below: 4. Peer-Reviewed Journal Publications Specifically Related to this Project 1. Powell SK, Goldsman N, Lelis A, et al. High-temperature modeling and characterization of 6H Silicon Carbide metal-oxide-semiconductor field-effect transistors, Journal of Applied Physics, 97 (4): Art. No , M. Huang, I. Mayergoyz, and N. Goldsman, Numerical simulation of small-signal microwave performance of 4H-SiC MESFET, Solid State Electronics, vol. 44, pp , G. Pennington and N. Goldsman, "Empirical Pseudopotential Band Structure of 3C, 4H, and 6H SiC Using Transferable Semiempirical Si and C Model Potentials," Physical Review B, 64, pp to , S. K. Powell, N. Goldsman, C.J. Scozzie, et al. ``Characterization and Physics-Based Modeling of 6H-SiC MOSFETs," Journal of Applied Physics, vol. 92, no. 7, pp , G. Pennington and N. Goldsman, ``Self-consistent calculations for n-type hexagonal SiC inversion layers Journal Applied Physics, 95 (8), pp , Potbhare S, Goldsman N, et al, A quasi-two-dimensional depth-dependent mobility model suitable for device simulation for Coulombic scattering due to interface trapped charges, Journal of Applied Physics, 100 (4): pp to , S. Potbhare, N. Goldsman, et al., A Physical Model of High Temperature 4H-SiC MOSFETs, IEEE Trans. on Electron Devices, vol. 55, pp (2008) 8. S. Potbhare, N. Goldsman, et al., Energy and Time Dependent Dynamics of Trap Occupation in 4H-SiC MOSFETs, IEEE Trans. on Elect. Devices, vol. 55, pg (2008) 9. M. Gurfinkel, N. Goldsman, et al, Characterization of transient gate oxide trapping in SiC MOSFETs using fast I-V techniques, IEEE Trans. on Elect. Devices, vol. 55 pg (2008) 10. A. Lelis, N. Goldsman, et al Time dependence of bias-stress-induced SiC MOSFET threshold-voltage instability measurements, IEEE Trans. on Elect. Dev. vol. 55 pg Other Peer-Reviewed Journal Publications in the Broad Field 1. G. Pennington and N. Goldsman, Semiclassical transport and phonon scattering of electrons in semiconducting carbon nanotubes," Phys Rev. B, 68 (4): ,

31 2. Pennington G, Goldsman N, Low-field semiclassical carrier transport in semiconducting carbon nanotubes," Phys. Rev B, 71 (20): pp to , Akturk A, Goldsman N, Self-consistent modeling of heating and MOSFET performance in 3-D integrated circuits," IEEE Trans. on Elect. Dev. 52 (11): , A. Akturk, N. Goldsman, G. Pennington, A. Wickenden, Terahertz current oscillations in single-walled zig-zag carbon nanotubes, Physical. Rev. Letters, 98, , A. Akturk, N. Goldsman, Device modeling at cryogenic temperatures: effects of incomplete ionization, IEEE Transactions on Electron Devices, 54 (11), (2007). 6. T. Salter, N. Goldsman, G. Metze, RF energy scavenging system utilizing switched capacitor DC-DC converter, ELECTRONICS LETTERS Vol 45 Pages: , C. Shen, R. Kupershtok, N. Goldsman, and M. Peckerar. Sensor support systems for asymmetric threat countermeasures. IEEE Sensors Journal, 8(6): , June Z. Dilli, N. Goldsman, G. Metze, Controlled on-chip heat transfer for directed heating and temperature reduction, Solid-State Electronics,Volume: 53 Issue: 6, , Z. Dilli, N. Goldsman, M. Peckerar, Design and testing of a self-powered 3-d integrated SOI CMOS system, Microelectronic Engineering 85(2), (2008). 10. B. Yang, X. Shao, Q. Balzano, N. Goldsman, G. Metze, 916 MHz F-Inverted Compact Antenna (FICA) for Highly Integrated Transceivers, IEEE Antennas and Wireless Propagation Letters, Volume: 8 Pages: , 2009 Education Texts Written in Circuit Design: Dr. Goldsman has written two works in electronic circuit design that are used as texts for at the University of Maryland. [1] Neil Goldsman, Electronics Analysis and Design: Dept. course text for ENEE 306. [2] Neil Goldsman and Zeynep Dilli, Introduction to Electrical and Computer Engineering: An Experiential Approach, an introduction to Electrical and Computer Engineering written for Maryland Governor's Institute of Technology at the University of Maryland. 6. Patents and Provisional Patents Filed 1. Method and System for Locating and Monitoring First Responders, 2007 (Co-Inventor). 2. Use of thermally conductive vias to extract heat from microelectronic chips, 2004,Patent Issued (Co-Inventor). 3. Low Profile F-Inverted Compact Antenna, U.S. Provisional Patent Filed 2007 (Co-Inventor) 4. Pedestrian Indoor Navigation and Tacking Device and Method, 2006 (Co-Inventor). 5. A High Performance EEPROM Cell, U.S. Provisional Patent, Filed 1998 (Co-Inventor). 6. Improved RF Power Harvesting Circuit Design, 2009, Patent Filed (Co-Inventor). 7. Technique for Improving the Supercapacitance of Ruthenium Oxide Based Capacitors, Provisional (Co-Inventor). 8. A Flexible, High Specific-Energy Density, Rechargeable Battery. 2008, Patent Filed (Co- Inventor). Integrated Circuits (Chips) Designed and Fabricated Under Supervision of Neil Goldsman: More than 50 chips have been designed under his supervision. The chips have been fabricated under the services of the TAPO Program and the MOSIS IC Fabrication Clearinghouse. 29

32 Siddharth Potbhare, Ph. D Senior Scientist, CoolCAD Electronics, LLC. Principal Investigator Professional Summary Dr. Siddharth Potbhare is a Senior Scientist and Vice President at CoolCAD Electronics. He received his Ph.D. in Electrical Engineering from the University of Maryland, College Park in He is working on developing advanced physical models and characterizing the operation of Silicon Carbide MOSFETs and DMOSFETs at high temperatures. His research is focused on understanding the physics of transport in SiC devices, and on modeling their performance in DC and switching environments such as power converter circuits. He has published many papers on SiC device modeling, algorithm development, and device characterization in peer-reviewed journals and different industry conferences. His interests include novel semiconductor materials, and design of advanced energy efficient microelectronic devices and circuits. He earned the B.E. (B.S.) degree in electronics engineering from the M. S. University, Vadodara, India in 2001 and the M.S. degree in electrical engineering from the University of Maryland in Education 2008 Ph.D. in Electrical Engineering, University of Maryland, College Park 2005 M.S. in Electrical Engineering, University of Maryland, College Park 2001 B.E. in Electronics Engineering, M. S. University, Vadodara, INDIA 2. Employment History 2008-Present Senior Scientist CoolCAD Electronics 2008-Present Research Associate University of Maryland, College Park 2007 Guest Researcher National Institute of Standards and Technology (NIST), Gaithersburg Graduate Research Assistant University of Maryland, College Park Lecturer Dharmsinh Desai Institute of Technology, Nadiad, INDIA 3. Awards and Honors: 4. Peer-reviewed publications specifically related to this project 1. M. Gurfinkel, S. Potbhare, et al., Ion Implantation and SiC Transistor Performance,, J. of Appl. Phys., 105, (2009) 2. A. Akturk, N. Goldsman, S. Potbhare, A. Lelis, High field density-functional-theory based monte carlo: 4h-sic impact ionization and velocity saturation, J. of Appl. Phys. 105, (2009) 3. S. Potbhare, N. Goldsman, et al., A Physical Model of High Temperature 4H-SiC MOSFETs, IEEE Trans. on Electron Devices, vol. 55, pp (2008) 4. S. Potbhare, N. Goldsman, J. Suehle, et al., Energy and Time Dependent Dynamics of Trap Occupation in 4H-SiC MOSFETs, IEEE Trans. on Electron Devices, vol. 55, pp (2008) 30

33 5. S. Potbhare, N. Goldsman, et al., A quasi-two-dimensional depth-dependent mobility model suitable for device simulation for Coulombic scattering due to interface trapped charges, J. Appl. Phys., Vol. 100, (2006) 6. S. Potbhare, N. Goldsman, et al., Numerical and experimental characterization of 4H-Silicon Carbide lateral metal-oxide-semiconductor field-effect transistor, J. Appl. Phys., Vol. 100, (2006) 7. S. Potbhare, N. Goldsman, et al., Modeling and Design of High Temperature Silicon Carbide DMOSFET Based Medium Power DC-DC Converter, IMAPS High Temperature Electronics (HiTEC) conference, Albuquerque NM (May 2010) 8. S. Potbhare, N. Goldsman, et al., Mixed Mode Modeling and Characterization of a 4H-SiC Power DMOSFET Based DC-DC Power Converter, Mat. Sci. Forums, vol , pg (2010) 9. S. Potbhare, N. Goldsman, et al., Effect of Band-edge Interface Traps and Transition Region Mobility on Transport in 4H-SiC MOSFETs, Mat. Sci. Forums, vol , pg. 975 (2010) 10. S. Potbhare, N. Goldsman, et al., Modeling the Effect of Conduction Band Density of States of Interface Trap Occupation and its Influence on 4H-SiC DMOSFET Performance, SISPAD 2009, USA (2009) 5. Other publications demonstrating capabilities in the broad field 1. S. Potbhare, N. Goldsman, et al., Investigation of ON and OFF State Characteristics of 4H-SiC DMOSFETs, ECSCRM 2008, Barcelona, Spain (2008) 2. S. Potbhare, N. Goldsman, et al., Effects of Quantum Confinement on Interface Trap Occupation in 4H-SiC MOSFETs, SISPAD 2008, Japan (2008) 3. S. Potbhare, N. Goldsman, A. Lelis, Modeling and Characterization of a 4H-SiC DMOSFET, MRS Spring 08 Workshop, San Francisco, CA (2008) 4. S. Potbhare, N. Goldsman, A. Lelis, High Temperature High Field Numerical Modeling and Experimental Characterization of 4H-SiC MOSFETs, Proc. of ISDRS 2007, College Park, MD (2007) 5. S. Potbhare, N. Goldsman, et al., Transient Characterization of Interface Traps in 4H-SiC MOSFETs, Proc. of SISPAD 2007 (2007) 6. S. Potbhare, N. Goldsman, et al., Time Dependent Trapping and Generation- Recombination of Interface Charges: Modeling and Characterization for 4H-SiC MOSFETs, Mat. Sci. Forums, Vols , pg. 847 (2007) 7. S. Potbhare, N. Goldsman, et al., Using a First Principles Coulomb Scattering Mobility Model for 4H-SiC MOSFET Device Simulation, Mat. Sci. Forums, Vols , pg (2006) 8. S. Potbhare, N. Goldsman, et al., Characterization of 4H-SiC MOSFET Interface Trap Charge Density Using a First Principles Coulomb Scattering Mobility Model and Device Simulation, Proc. of SISPAD 05, pp Japan (2005) 9. A. Lelis, S. Potbhare, et al., Modeling and Characterization of Bias Stress-Induced Instability of SiC MOSFETs, Proc. of IIRW 06, pg. 160 (2006) 10. G. Pennington, S. Potbhare, et al., Electron Transport at Technologically Significant Stepped 4H-SiC/SiO 2 Interfaces, Proc. of SISPAD 2006, pg. 236 (2006) 31

34 Akin Akturk, Ph. D Senior Scientist, CoolCAD Electronics, LLC. Professional Summary: Dr. Akin Akturk is co-founder and Vice President of CoolCAD Electronics. Dr. Akturk earned his Ph.D. at the end of spring 2006 from the University of Maryland, College Park, which also awarded him with an M.S. degree in His recent research/work interests include performance modeling of nanoscale MOSFETs, and coupled thermal modeling of devices, and planar and three-dimensional integrated circuits. He has done extensive non-isothermal modeling of devices such as SOI-MOSFETs and MOSFETs, with Silicon or heterojunctions in their channels. His analyses cover a wide temperature spectrum ranging from cryogenic temperatures to couple hundred degrees above room temperature. Additionally, he developed novel algorithms to couple device operation to chip heating and performance. He participated in the design and investigation of three-dimensional heterogeneous integration technologies, where he mainly focused on self-heating effects. Through simulation, he demonstrated the concept of using thermal conduits to remove heat from the hot spots of the chip. He along with his colleagues was awarded a provisional patent for heat removal by US patent office. In addition, he investigated novel device designs including carbon nanotubes and carbon nanotube embedded transistors. He has published various papers on full-chip heating and novel MOSFET configurations. He also has done several circuit and layout designs, some of which were fabricated through a fabrication service. 1. Education 2006 Ph. D., Electrical & Computer Engineering, University of Maryland, College Park 2001 M.S., Electrical & Computer Engineering, University of Maryland, College Park 1999 B.S., Electrical & Electronics Engineering, Bilkent University, Ankara, Turkey 2. Work Experience 2006 Present Vice President/Senior Scientist, CoolCAD Electronics 2007 Present Assistant Research Scientist, ECE Department, University of Maryland Research Associate, ECE Department, University of Maryland Graduate Research Assistant, University of Maryland Graduate Teaching Assistant, University of Maryland 3. Awards and Honors 4. Peer-reviewed publications specifically related to this project 1. A. Akturk, M. Holloway, S. Potbhare, D. Gundlach, B. Li, N. Goldsman, M. Peckerar, K. P. Cheung, Compact and distributed modeling of cryogenic bulk mosfet operation, accepted for publication in IEEE Transactions on Electron Devices, vol. 57, pg (2010). 2. A. Akturk, N. Goldsman, S. Potbhare, A. Lelis, High field density-functional-theory based monte carlo: 4h-sic impact ionization and velocity saturation, Journal of Applied Physics 105, (2009). 32

35 3. Z. Dilli, A. Akturk, N. Goldsman, G. Metze, Controlled on-chip heat transfer for directed heating and temperature reduction, Solid State Electronics 53(6), (2009). 4. A. Akturk, N. Goldsman, S. Aslam, J. Sigwarth, F. Herrero, Comparison of 4h-sic impact ionization models using experiments and self-consistent simulations, Journal of Applied Physics 104, (2008). 5. S. Potbhare, N. Goldsman, A. Akturk, M. Gurfinkel, A. Lelis, J. Suehle, Energy and time dependent dynamics of trap occupation in 4h-sic mosfets, IEEE Transactions on Electron Devices 55(8), (2008). 6. Z. Dilli, N. Goldsman, M. Peckerar, A. Akturk, G. Metze, Design and testing of a selfpowered 3-d integrated soi cmos system, Microelectronic Engineering 85(2), (2008). 7. A. Akturk, J. Allnut, Z. Dilli, N. Goldsman, M. Peckerar, Device modeling at cryogenic temperatures: effects of incomplete ionization, IEEE Transactions on Electron Devices 54(11), (2007). 8. A. Akturk, N. Goldsman, L. Parker, G. Metze, Mixed-mode temperature modeling of full-chip based on individual non-isothermal device operations, Solid-State Electronics 49(7), (2005). 9. A. Akturk, N. Goldsman, G. Metze, Self-consistent modeling of heating and MOSFET performance in three-dimensional integrated circuits, IEEE Transactions on Electron Devices 52(11), (2005). 5. Other publications demonstrating capabilities in the broad field 1. M. Dandin, A. Akturk, B. Nouri, N. Goldsman, P. Abshire, Characterization of singlephoton avalanche diodes in a 0.5 micrometer standard cmos process. Part 1: perimeter breakdown suppression, accepted for publication in IEEE Sensors Journal (2010) 2. A. Akturk, N. Goldsman, Electron transport and full-band electron-phonon interactions in graphene, Journal of Applied Physics 103, (2008). 3. A. Akturk, N. Goldsman, Single-walled zig-zag carbon nanotube steady state transport characteristics, Special issue of the Journal of Computational and Theoretical Nanoscience on Semiconductor Device Modeling and Simulation 5(6), (2008). 4. Z. Dilli, N. Goldsman, M. Peckerar, A. Akturk, G. Metze, Design and testing of a self powered 3-D integrated SOI CMOS system, Microelectronic Engineering 85(2), (2008). 5. A. Akturk, N. Goldsman, G. Pennington, A. Wickenden, Terahertz current oscillations in single-walled zig-zag carbon nanotubes, Physical Review Letters 98, (2007). 6. G. Pennington, N. Goldsman, A. Akturk, A. Wickenden, Deformation potential carrierphonon scattering in semiconducting carbon nanotube transistors, Applied Physics Letters 90(2), (2007). 7. A. Akturk, N. Goldsman, G. Pennington, A. Wickenden, Electron transport and velocity oscillations in a carbon nanotube, IEEE Transactions on Nanotechnology 6(4), (2007). 33

36 8. A. Akturk, N. Goldsman, G. Pennington, Self-consistent ensemble Monte Carlo simulations show terahertz oscillations in single-walled carbon nanotubes, Journal of Applied Physics 102, (2007). 9. A. Akturk, G. Pennington, N. Goldsman, Quantum modeling and proposed designs of carbon nanotube (CNT) embedded nanoscale MOSFETs, IEEE Transactions on Electron Devices 52(4), (2005). 10. A. Akturk, N. Goldsman, G. Metze, Increased CMOS inverter switching speed with asymmetrical doping, Solid-State Electronics 47(2), (2003). 6. Non-Peer-Reviewed Publications and Patents 1. Use of thermally conductive vias to extract heat from microelectronic chips and method of manufacturing United States Patent: 7,286,359 Inventors: Michael Khbeis, George Metze, Neil Goldsman, Akin Akturk 2. A. Akturk, N. Goldsman, Single-walled zig-zag carbon nanotube steady state transport characteristics, to appear in a special issue of the Journal of Computational and Theoretical Nanoscience on Semiconductor Device Modeling and Simulation June, 1-7 (2008). 3. A. Wickenden, B. Nichols, M. Ervin, S. Kilpatrick, A. Akturk, G. Pennington, N. Goldsman, G. Esen, A. Manasson, M. Fuhrer, Carbon nanotube devices for sensing and communications applications, Proc. of 211th Electrochemical Society (ECS) Meeting H4, 1052 (2007). 4. N. Goldsman, A. Akturk, Analysis and design of key phenomena in electronics: nanostructures and devices, Proc. of Int. Society for Optical Eng. (SPIE) Conf., I (2006). 34

37 James M. McGarrity, Ph. D Director, CoolCAD Electronics LLC Professional Summary: Dr. James M. McGarrity is a Director at CoolCAD Electronics LLC. Prior to his current position, Dr. McGarrity was Senior Research Scientist (ST) for the Sensors and Electron Devices Directorate of the Army Research Laboratory, Adelphi, Maryland. This position was attained in April 1991 in recognition of his career achievements in the study of radiation effects in semiconductor devices and radiation hardening of integrated circuits. As Senior Research Scientist, Dr. McGarrity performed research to improve the survivability of electronics and has served as technical advisor to the several other government agencies. Prior to that assignment he served as the Chief of the Radiation Effects Physics Branch of the former Harry Diamond Laboratories. From 1983 to 1988 he served as Deputy for Radiation Hard Technology for the OSD Very High Speed Integrated Circuits (VHSIC) Office and R&D supervisor and researcher in radiation effects in electronics at HDL. Since 1992 he managed SiC programs and performed research focused on the development of SiC Power devices especially for extreme environments for DOD and DOE. Dr. McGarrity is a Fellow of the IEEE for his radiation effects research on Silicon metal oxide semiconductor (MOS) devices and has over eighty journal publications. He is the recipient of the prestigious 2010 Harry Diamond Award for contributions to the field of electronics by a U.S. government employee. 1. Education 1969 PhD. Nuclear Engineering, University of Maryland, College Park, MD 1958 B.S. Physics/Electronics, St. Joseph s University, Philadelphia, PA 2. Work Experience 2009 Present Director, CoolCAD Electronics LLC, Takoma Park, MD Consultant on SiC to Army Research Laboratory, Adelphi, MD Army Research Laboratory, Sensors and Electron Devices Directorate, Adelphi, MD U.S. Army Harry Diamond Laboratories, Nuclear Survivability Division, Adelphi, MD 3. Honors, Awards and Notable Professional Appointments 2010 IEEE USA Harry Diamond Award for contributions to electronics by a government employee 1991 U.S. Army Senior Research Scientist (ST) for Electronic Survivability Chairman, IEEE Radiation Effects Committee 1985 IEEE Fellow Award for contributions to the understanding of the effects of radiation on MOS devices Deputy for Radiation Hardened Technology for the OSD Very High Speed Integrated Circuits (VHSIC) Office 35

38 1977 & 1980 Awards for the Best Paper at the IEEE Nuclear and Space Radiation Effects Conference 4. Peer-Reviewed Journal Publications Specifically Related to this Project 1. S. Potbhare, N. Goldsman, A. Lelis, J. McGarrity, et. al., A Physical Model of High Temperature for H-SiC MOSFETs, IEEE Trans. on Electron Devices, vol. 55 (2008) 2. S. K. Powell, N. Goldsman, J. McGarrity, et. al., Characterization and Physics-Based Modeling of 6H-SiC MOSFETs, Journal of Applied Physics, vol.92, no. 7 (2002) 3. C. J. Scozzie and J. M. McGarrity, Charge Pumping Measurements on SiC MOSFETs, Proc. of International Conf. on Silicon Carbide and Related Materials, Institute of Physics, London (1997) 4. C. J. Scozzie, F. B. McLean, and J. M. McGarrity, Modeling the Temperature Response of 4H SiC Junction Field-Effect Transistors, J. Appl. Phys., vol. 81, no. 11 (June, 1997) 5. C. J. Scozzie, J. M. McGarrity, et. al., Silicon Carbide FETs for High Temperature Nuclear Environments, IEEE Trans. Nucl. Sci., vol. 43, no.4 (August 1996) 6. F. B. McLean, C. W. Tipton, J. M. McGarrity, and C. J. Scozzie, Modeling the Electrical Characteristics of n-channel 6H SiC Junction Field-Effect Transistors as a Function of Temperature, Appl. Phys. Let., vol 79, no. 1 (January 1996) 7. J. M. McGarrity, C. J. Scozzie, et. al., A Silicon Carbide FET Amplifier for High Temperature and High Radiation Environments, AIP Proc. Int. Symposia on Space, Nuclear Power and Propulsion (January 1995) 8. F. B. McLean, J. M. McGarrity, et. al., Analysis of Neutron Damage in Silicon Carbide JFETs, IEEE Trans. Nucl., Sci., vol. 41, no. 6 (1994) 9. C. J. Scozzie, C. W. Tipton, J. M. McGarrity and F. B. McLean, High Temperature Stressing of Silicon Carbide JFETs at 300C, Proc., IEEE, Int l., Reliability Physics Symposia (1994) 10. J. McGarrity, F. B. McLean, et. al., Silicon Carbide JFET Radiation Response, IEEE Trans., Nucl., Sci. vol. 39, no. 6 (1992) 5. Other Peer-Reviewed Journal Publications in the Broad Field 1. J. R. Srour and J. M. McGarrity, Radiation Effects on Microelectronics in Space, Spec. Proc. of IEEE, vol. 76, no. 11 (1988) (Thirty-five papers on radiation effects in Silicon electronics referenced over 1300 times.) 6. Patents and Provisional Patents Filed 1. J. M. McGarrity and H. E. Boesch, Method for Electrically Simulating Radiation Susceptibility in MOS Gate Devices Patent no. 4,323,842. (April 1982) 36

39 David E. Grider, Ph. D Power Program Manager, Cree Inc. Principal Investigator at Cree Inc. 1. Education / Training 1980 Ph.D. - Solid State Physics, Iowa State University, Ames, Iowa 1975 B.A. - Physics, cum laude, McMurry College, Abilene, Texas 1997 Hughes Management Development Program, University of Southern California, Marshall School of Business 2. Employment History 2004-Present Power Program Manager, Cree, Inc. Durham, North Carolina Senior R&D Programs Manager, RF Micro Devices Charlotte, North Carolina Research Project Manager, HRL Laboratories, LLC Formerly Hughes Research Labs, Malibu, California Department Manager, Hughes Research Laboratories Malibu, California Research Staff Scientist, Honeywell Technology Center Bloomington, Minnesota Adjunct Associate Professor, University of Minnesota Department of Electrical Engineering, Minneapolis, Minnesota Senior Principal Research Scientist, Honeywell Systems and Research Center Bloomington, Minnesota Principal Research Scientist, Honeywell Physical Sciences Center Bloomington, Minnesota Assistant Professor, Georgia Institute of Technology School of Physics, Atlanta, Georgia Post Doctoral Research Associate, University of Liverpool Donnan Laboratories, Liverpool, England Post Doctoral Research Scientist, Fritz-Haber-Institute Max-Planck-Gesellschaft, West Berlin, West Germany 3. Peer-Reviewed Publications Related to this Project 1. Invited Presentation on Recent Advances and Applications of SiC Power Device Technology at the Government Microelectronics Technology Conference - GOMACTech-2009 (Orlando, FL March, 2009). 2. Invited Presentation on Recent Advances in SiC Power Device Technology at the Energy 2030 IEEE Conference on Global Sustainable Energy Infrastructure (Atlanta, GA November, 2008). 3. Invited Presentation on SiC Power Devices and Applications Outlook at the 2008 Industrial Applications Society (IAS) Annual Meeting (Edmonton, Alberta, Canada October, 2008). 4. Invited Presentation on The Progress In SiC Materials and Devices, at the 2008 Electronic Materials Conference (University of California at Santa Barbara - June, 2008). 5. Invited Presentation on SiC Power Device and Material Technology at the Department of Energy (DOE) High Megawatt Converter Technology R&D Roadmap Workshop (NIST, Gaithersburg, MD - April, 2008). 37

40 6. Invited Presentation on SiC Power Device Technology for High Power Applications at the Government Microelectronics Technology Conference - GOMACTech-2008 (Las Vegas, NV March, 2008). 7. Invited Presentation on SiC Devices for High Power Applications at the Government Microelectronics Technology Conference - GOMACTech-2007 (Orlando, FL March, 2007). 8. Invited Presentation on Recent Developments in SiC Power Device Technology at the Department of Energy (DOE) High Megawatt Converter Technology Workshop (NIST, Gaithersburg, MD - January, 2007). 9. Invited presentation on High Power SiC Power Device and Module Development at the DARPA/MTO Wide Bandgap High Power Electronics Meeting (St. Louis, MO October, 2005). 6. Non-Peer-Reviewed Publications and Patents 1. U.S. Patent No. 7,514,759: Piezoelectric MEMs Integration with GaN Technology, Sarabjit Mehta, David E. Grider, Wah S. Wong. 2. U.S. Patent No. 7,459,356: High Voltage GaN-Based Transistor Structure, Joseph Smart, Brook Hosse, Shawn Gibb, David Grider, Jeffrey Shealy. 3. U.S. Patent No. 7,408,182: Surface Passivation of GaN Devices in Epitaxial Growth Chamber, Joseph Smart, David Grider, Shawn Gibb, Brook Hosse, Jeffrey Shealy. 4. U.S. Patent No. 7,247,893 B2: Non-Planar Nitride-Based Heterostructure Field Effect Transistor Field Effect Transistor, Jeong Sun Moon, Paul Hashimoto, Wah S. Wong, David E. Grider. 5. U.S. Patent No. 7,052,942 B1: Surface Passivation of GaN Devices in Epitaxial Growth Chamber, Joseph Smart, David Grider, Shawn Gibb, Brook Hosse, Jeffrey Shealy. 6. U.S. Patent No. 7,033,961: Epitaxy/Substrate Release Layer, Joseph Smart, Brook Hosse, Shawn Gibb, David Grider, Jeffrey Shealy. 7. U.S. Patent No. 7,026,665 B1: High Voltage GaN-Based Transistor Structure, Joseph Smart, Brook Hosse, Shawn Gibb, David Grider, Jeffrey Shealy. 8. U.S. Patent No. 6,830,945 B2: Method for Fabrication a Non-Planar Nitride-Based Heterostructure Field Effect Transistor Field Effect Transistor, Jeong Sun Moon, Paul Hashimoto, Wah S. Wong, David E. Grider. 9. U.S. Patent No. 5,298,772: Integrated Heterostructure Acoustic Charge Transport (HACT) and Heterostructure Insulated Gate Field Effect Transistor (HIGFET) Devices, Andrzej Peczaqlski, David E. Grider, James F. Detry, Geore Kilgore, William J. Tanski, Thomas We. Grudkowski, Robert N. Sacks. 38

41 Anant Agarwal, Ph. D R&D Manager, SiC Power Devices, Cree Inc. Professional Summary: Dr. Anant K. Agarwal received the B.E. degree in Electrical Engineering from MNR Engineering College, University of Allahabad, India, in 1978, the M.S. degree in Electrical Engineering from University of Tennessee Space Institute, Tn, in 1981, and the Ph.D. degree in Electrical Engineering from Lehigh University, Bethlehem, Pa, in From 1984 to 1985, he was with The Bell Laboratories, Murray Hill, NJ where he developed high speed GaAs digital circuits for optical communication circuits. From 1985 to 1990, he was an Assistant Professor with the MNR Engineering College, Allahabad, India. From 1990 to 1999, he was with Northrop Grumman Science and Technology Center (formerly, Westinghouse STC), Pittsburg, PA, where his research interests included SiC power and microwave device design and processing, design and process of SiC GTOs, UMOSFETs, DMOSFETs and SITs for a variety of externally and internally sponsored programs and development of SiGe HBTs for X-band power amplifiers. Since 1999, he has been with Cree Inc., Durham, NC, where his research interests include SiC high-power high-temperature devices. He has authored or coauthored over 200 technical papers and conference presentations, and holds 15 U.S. patents. Dr. Agarwal is a Senior Member of the IEEE Electron Device Society. 1. Education 1984 Ph.D. in Electrical Engineering, Lehigh University 1980 M.S. in Electrical Engineering, University of Tennessee Space Institute 1978 B.S. in Electrical Engineering, University of Allahabad, India 2. Work Experience 1999 Present: Senior Scientist and R&D Manager, SiC Power Devices, CREE, Inc : Fellow Engineer, Principal Investigator of SiC power switching devices and X- band SiGe MMIC development, Northrop Grumman Science & Technology Center, Pittsburgh (formerly Westinghouse) : Assistant Professor, M.N.R. Engineering College, Allahabad, India : Member of Technical Staff, AT&T Bell Laboratories, Murray Hill, New Jersey 3. Honors, Awards and Notable Professional Appointments 1. Technical Program Committee Member of the IEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD), Technical Program Committee Member of the International Conference on Silicon Carbide and Related Materials, Technical Program Committee Member of the Device Research Conference, Symposium Organizer, SiC Materials, Processing, and Devices, MRS, Boston, Fall Guest Editor, Special Issue on SiC IEEE Ele. Dev. Trans., published in April Reviewer for IEEE Electron Device Letter, Applied Physics Letters, Journal of Applied Physics and Solid State Electronics 39

42 7. George Westinghouse Signature Award (STC only) for work on UHF SiC Static Induction Transistor, Feb Chaired Technical Session IV B on Wide Bandgap and Power Devices, 53rd Annual Dev. Res. Conference, University of Virginia, Charlottesville, Virginia, June 19-21, Corporate George Westinghouse Innovation Award for a disclosure on SiC Static Induction Transistor, May Co-Chaired Technical Session on SiC Devices, at WOCSEMAD, New Orleans, 02, Westinghouse EISD Outstanding Performance Recognition for formulation of a viable approach to SiC NVRAM, August Senior Member of IEEE Electron Device Society 13. Sherman Fairchild Fellowship, Lehigh University, Peer-Reviewed Journal Publications Specifically Related to this Project 1. Q. Zhang and A. Agarwal, Design and technology considerations for SiC bipolar devices: BJTs, IGBTs, and GTOs, physica status solidi (a), Vol. 206, No. 10, (2009), pp Q. Zhang, M. Das, A. Agarwal, et al 12-kV p-channel IGBTs with Low On-resistance in 4H-SiC, IEEE Eletron. Dev. Lett., v. 29, no. 9, pp , Sept Q. Zhang, S. Ryu, A. Agarwal, et al, Design and Characterization of High-Voltage 4H- SiC p-igbts, IEEE Trans. on Elec. Dev., v. 55, Issue 8, pp , Aug Y. Gao, A. J. Richmond, A. K. Agarwal, et al Comparison of Static and Switching Characteristics of 1200 V 4H-SiC BJT and 1200 V Si-IGBT, IEEE Trans. on Industry App., v. 44, No. 3, pp , May-Jun A. Agarwal, H. Fatima, et al, "A New Degradation Mechanism in High-Voltage SiC Power MOSFETs", IEEE Electron Dev. Letters, Vol. 28, pp , Q. Zhang, C. Jonas, A. Agarwal, et al, 12 kv 4H-SiC p-igbts with Record Low Specific On-resistance, Mat. Sci. Forum, Vols (2009), pp Q. Zhang, C. Jonas, M. Das, A. Agarwal, et al New Improvement Results on 7.5 kv 4H- SiC p-igbts with R diff, on of 26 mω-cm 2 at 25 C, IEEE Proceedings of Power Semiconductor Devices and IC's (ISPSD '07), pp , Q. Zhang, M. Das, S.-H. Ryu, A. Agarwal, et al 9 kv 4H-SiC IGBTs with 88 mω-cm 2 of R diff,on, Mat. Sci. Forum, Vols (2007), pp Q. Zhang, A. Agarwal, et al Design and Fabrications of High Voltage IGBTs on 4H- SiC, IEEE Proceedings of Power Semiconductor Devices and IC's (ISPSD '06), Q. Zhang, S.-H. Ryu, C. Jonas, A. Agarwal, and John Palmour, Simulation of 10 kv Trench Gate IGBTs on 4H-SiC, Mat. Sci. Forum, Vols (2006), pp Other Peer-Reviewed Journal Publications in the Broad Field 1. J. Wang; F. Husna, A. Agarwal, et al 10-kV SiC MOSFET-Based Boost Converter, IEEE Trans. on Industry App., v. 45, Issue 6, pp , Nov-Dec, D. J. Lichtenwalner, V. Misra, S. Dhar, S.-H. Ryu, and A. Agarwal, High-mobility enhancement-mode 4H-SiC lateral field-effect transistors utilizing atomic layer deposited Al 2 O 3 gate dielectric, App. Phys. Lett., 95, p , Oct J. D. Caldwell, A. Agarwal, et al Recombination-induced stacking fault degradation of 4H-SiC merged-pin-schottky diodes, J. of App. Phys. 106, p , Aug

43 4. T. L. Biggerstaff, C. L. Reynolds, T. Zheleva, A. Lelis, D. Habersat, S. Haney, S.-H. Ryu, A. Agarwal, and G. Duscher, Relationship between 4H-SiC/SiO2 transition layer thickness and mobility, App. Phys. Lett., 95, Issue 3, p , Jul Q. Zhang, R. Callanan, A. Agarwal, et al A 10-kV Monolithic Darlington Transistor with β forced of 336 in 4H-SiC, Eletron. Dev. Lett., v. 30, no. 2, pp , Feb J.A. Carr, D. Hotz, A. Agarwal, et al Assessing the Impact of SiC MOSFETs on Converter Interfaces for Distributed Energy Resources, IEEE Trans. on Power Electron., v. 24, Issue 1, pp , Jan P. G. Muzykov, R. M. Kennedy, Q. Zhang, C. Capell, A. Burk, A. Agarwal, and T. S. Sudarshan, Physical phenomena affecting performance and reliability of 4H SiC bipolar junction transistors, Microelectronics Reliability, v. 49, pp 32-37, Jan A. Grekov, Q. Zhang, H. Fatima, A. Agarwal, and T. Sudarshan, Effect of crystallographic defects on the reverse performance of 4H SiC JBS diodes, Microelectronics Reliability, v. 48, issue 10, pp , Oct Q. Zhang, A. Agarwal, A. Burk, B. Geil and C. Scozzie, 4H-SiC BJTs with Current Gain of 110, Solid State Electronics, v. 52/7, (2008). 10. J. Wang; T. Zhao, J. Li, A.Q. Huang, R. Callanan, F. Husna, and A. Agarwal, Characterization, Modeling, and Application of 10-kV SiC MOSFET, IEEE Trans. on Electron Dev., v. 55, Issue 8, pp , Aug Non-Peer-Reviewed Publications and Patents 1. S.-H. Ryu, J. R. Jenny, M. K. Das, A. K. Agarwal, J. W. Palmour, and H. McD. Hobgood, High voltage Silicon Carbide devices having bi-directional blocking capabilities, U. S. Patent# 7,615,801, Nov. 10, A. Hefner, S.-H. Ryu and A. K. Agarwal, Power switching semiconductor devices including rectifying junction-shunts, U. S. Patent# 7,598,567, Oct. 6, A. Agarwal, S.-H. Ryu, and M. Donofrio, Methods of processing semiconductor wafers having Silicon Carbide power devices thereon, U. S. Patent# 7,547,578, Jun. 16, A. Agarwal, S. Krishnaswami, S.-H. Ryu, and D. C. Capell, Silicon Carbide bipolar junction transistors having a Silicon Carbide passivation layer on the base region thereof, U. S. Patent# 7,345,310, Mar. 18, A. Agarwal, S. Krishnaswami, S.-H. Ryu, and E. H. Hurt, Silicon Carbide bipolar junction transistors having epitaxial base regions and multilayer emitters and methods of fabricating the same, U. S. Patent# 7,304,334, Dec. 14, A. Agarwal, S.-H. Ryu, and J. W. Palmour, Manufacturing methods for large area Silicon Carbide devices, U. S. Patent# 7,135,359, Nov. 14, S.-H. Ryu and A. K. Agarwal, "Multiple Floating Guard Ring Edge Termination for Silicon Carbide Devices," U. S. Patent# 7,026,650, Aug. 03, A. Agarwal, S.-H. Ryu, and J. W. Palmour, Large area Silicon Carbide devices, U. S. Patent# 6,770,911, Apr. 11, Q. Zhang, S.-H. Ryu, C. Jonas, and A. K. Agarwal, High Power Insulated Gate Bipolar Transistors, U. S. Patent application #: Q. Zhang, and A. Agarwal, Mesa terminaiton structures for power semiconductor devices, U. S. Patent application #: , May 8,

44 Sei-Hyung Ryu, Ph. D Senior Research Scientist, Cree Inc. Professional Summary: Dr. Sei-Hyung Ryu is a Senior Research Scientist at Cree, Inc. He received his Ph.D. degree in Electrical and Computer Engineering from Purdue University, West Lafayette, IN in 1997, where he developed the world s first p-well CMOS integrated circuit technology in 6H-Silicon Carbide (SiC). From 1997 to 1999, he worked as a post-doctoral research associate at Purdue University, where he developed RESURF power MOSFETs in 6H- and 4H-SiC. In 1999, he joined Cree, Inc., as a research scientist. His responsibility included developments of high performance power switching devices in 4H-SiC. His contribution was critical for successful for the successful commercialization of high voltage Schottky diodes in 4H-SiC, and he also lead the power MOSFET development team. In 2006, he joined the Department of Electrical and Computer Engineering of Wayne State University, Detroit, MI as an Associate Professor in power electronics. He rejoined Cree, Inc., in 2007 as a Senior Research Scientist, and currently working on the development of next generation power switches in 4H-SiC. Dr. Ryu is a senior member of IEEE, and currently serving as an editor for IEEE Electron Device Letters. He also hold 19 US patents. 1. Education 1997 Ph.D. Electrical and Computer Engineering, Purdue University, W. Lafayette, IN 1993 M.S., Electrical Engineering, Purdue University, W. Lafayette, IN 1992 B.S., Electronics Engineering, Seoul National University, Seoul, Korea 2. Work Experience 2007 Present: Senior Research Scientist, Cree, Inc : Associate Professor, Wayne State University, Detroit, MI : Research Scientist, Cree, Inc., February : Post Doctoral Research Associate, Purdue University 3. Honors, Awards and Notable Professional Appointments Best Paper Award 13 th International Symposium on Power Semiconductor Devices and Integrated Circuits: K. Asano, Y. Sugawara, S. Ryu, R. Singh, J. Palmour, T. Hayashi, and D. Takayama, 5.5 kv Normally-Off Low RonS 4H-SiC SEJFET, ISPSD 01. June 4-5, 2001, Osaka, Japan. 4. Peer-Reviewed Journal Publications Specifically Related to this Project 1. S. Ryu, S. Dhar, S. K. Haney, A. Agarwal, A. J. Lelis, B. Geil, and C. J. Scozzie, Critical Issues for MOS Based Power Devices in 4H-SiC, Materials Science Forums, Vols (2009), pp S. Ryu, Q. Zhang, H. Fatima, S. Haney, R. Stahlbush, and A. Agawal, Degradation of Majority Carrier Conductions and Blocking Capabilities in 4H-SiC High Voltage Devices Due to Basal Plane Dislocations, Mater. Res. Soc. Symp. Proc. Vol.1069, 2008 Materials Research Society, pp

45 3. S. Ryu, F. Husna, S. Haney, Q. Zhang, R. Stahlbush, and A. Agarwal, Effect of Recombination-Induced Stacking Faults on Majority Carrier Conduction and Reverse Leakage Current on 10 kv SiC DMOSFETs, Materials Science Forums Vols (2009), pp S. Ryu, S. Krishnaswami, B. Hull, J. Richmond, A. Agarwal, and A. Hefner, 10 kv, 5A 4H-SiC Power DMOSFET, Proceedings of the 18 th International Symposium on Power Semiconductor Devices & IC's, pp , Naples, Italy, June 4-8, Q. Zhang, C. Jonas, S. Ryu, A. Agarwal, and J. Palmour, Design and Fabrications of High Voltage IGBTs on 4H-SiC, Proceedings of the 18 th International Symposium on Power Semiconductor Devices & IC's, pp , Naples, Italy, June 4-8, S. Ryu, S. Krishnaswami, M. O'Loughlin, J. Richmond, A. Agarwal, J. Palmour, A. R. Hefner, 10 kv, 123 mω cm 2 4H-SiC Power DMOSFETs, IEEE Electron Device Letters, Vol. 25, issue 8, Aug. 2004, pp S.-H. Ryu, A. Agarwal, S. Krishnaswami, J. Richmond, and J. Palmour, "Development of 10 kv 4H-SiC Power DMOSFETs," Materials Science Forum Vols (2004), pp Y.Sugawara, D.Takayama, K.Asano, A.Agarwal, S. Ryu, J.Palmour and S.Ogata, "12.7kV Ultra High Voltage SiC Commutated Gate Turn-off Thyristor : SICGT,"presented at the16 th IEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD 04), KITAKYUSHU International Conference Center, Japan, May 24-27, Other Peer-Reviewed Journal Publications in the Broad Field 1. B. Hull, C. Jonas, S. Ryu, M. Das, M. O Loughlin, F. Husna, R. Callanan, J. Richmond, A. Agarwal, J. W. Palmour, and C. J. Scozzie, Performance of 60 A, 1200 V 4H-SiC DMOSFETs, Materials Science Forums Vols (2009), pp L. C. Yu, K. P. Cheung, J. S. Suehle, J. P. Campbell, K. Sheng, A. J. Lelis, S. Ryu, Channel Hot-Carrier Effect of 4H-SiC MOSFET, Materials Science Forums Vols (2009), pp S. Haney, S. Ryu, S. Dhar, A. Agarwal, M. Johnson, Effective Channel Mobility in Epitaxial and Implanted 4H-SiC Lateral MOSFETs, Mater. Res. Soc. Symp. Proc. Vol.1069, 2008 Materials Research Society, pp S. Ryu, S. Krishnaswami, M. Das, B. Hull, J. Richmond, B. Heath, A. Agarwal, J.Palmour and J. Scofield, "10.3 mω-cm 2, 2 kv Power DMOSFETs in 4H-SiC," Proceedings of the 17 th International Symposium on Power Semiconductor Devices & IC's, pp , Santa Barbara, CA, May 23-26, A.K. Agarwal, S. Krishnaswami, J. Richmond, C. Capell, S. Ryu, J. W. Palmour, S. Balachandran, T. P. Chow, S. Bayne, B. Geil, C. Scozzie and K. A. Jones, "Evolution of the 1600 V, 20 A, SiC Bipolar Junction Transistors," Proceedings of the 17 th International Symposium on Power Semiconductor Devices & IC's, pp , Santa Barbara, CA, May 23-26, A. K. Agarwal, B. Damsky, J. Richmond, S. Krishnaswami, C. Capell, S. Ryu and J. W. Palmour, "The First Demonstration of the 1 cm x 1 cm SiC Thyristor Chip," Proceedings of the 17 th International Symposium on Power Semiconductor Devices & IC's, pp , Santa Barbara, CA, May 23-26,

46 7. S. Krishnaswami, M. Das, B. Hull, S. Ryu, J. Scofield, A. Agarwal, and J. Palmour, "Gate Oxide Reliability of 4H-SiC MOS Devices," IEEE 43 rd Annual International Reliability Physics Symposium, pp , April 17-21, S. Ryu, S. Krishnaswami, M. Das, J. Richmond, A. Agarwal, J. Palmour and J. Scofield, "4H-SiC DMOSFETs for High Speed Switching Applications," Materials Science Forum Vols (2005), pp M. A. Capano, S. Ryu, M. R. Melloch, J. A. Cooper, Jr., and M. R. Buss, Dopant Activation and Surface Morphology of Ion Implanted 4H- and 6H-Silicon Carbide, Journal of Electronic Materials, Vol. 27, no. 4, pp , April S. Ryu, K. T. Kornegay, J. A. Cooper, Jr., and M. R. Melloch, Digital CMOS ICs in 6H- SiC Operating on a 5V Power Supply, IEEE Transactions on Electron Devices, Vol. 45, no. 1, pp , Jan Non-peer-reviewed Publications and Patents 1. U.S. Patent # 7,074,643: Silicon Carbide power devices with self-aligned source and well regions and methods of fabricating same, by S. Ryu. 2. U.S. Patent # 7,026,650: Multiple floating guard ring edge termination for Silicon Carbide devices, by S. Ryu and A. Agarwal. 3. U.S. Patent # 6,979,863: Silicon Carbide MOSFETs with integrated antiparallel junction barrier Schottky freewheeling diodes and methods of fabricating the same, by S. Ryu. 4. U.S. Patent # 6,956,238: Silicon Carbide power Metal-Oxide Semiconductor Field Effect Transistors having a shorting channel and methods of fabricating Silicon Carbide Metal-Oxide-Semiconductor Field Effect Transistors having a shorting channel, by S. Ryu, A. Agarwal, M. Das, L. Lipkin, J. Palmour, and R. Singh. 5. U.S. Patent # 6,770,911: Large area Silicon Carbide devices, by A. Agarwal, S. Ryu, and J. Palmour. 6. U.S. Patent # 6,653,659: Silicon Carbide inversion channel mosfets, by S. Ryu, J.J. Sumakeris, A. K. Agarwal, and R. Singh. 7. U.S. Patent # 6,514,779: Large area Silicon Carbide devices and manufacturing methods therefor, by S. Ryu, A. Agarwal, C. Capell, and J. W. Palmour. 8. U.S. Patent # 6,429,041: Methods of fabricating Silicon Carbide inversion channel devices without the need to utilize P-type implantation, by S. Ryu, J.J. Sumakeris, A. K. Agarwal, and R. Singh. 9. U.S. Patent # 6,329,675: Self-aligned bipolar junction Silicon Carbide transistors, by R. Singh, A. K. Agarwal, and S. Ryu. 10. U.S. Patent # 6,218,254: Method of fabricating a self-aligned bipolar junction transistor in Silicon Carbide and resulting devices, by R. Singh, A. K. Agarwal, and S. Ryu. 44

47 Sarit Dhar, Ph. D Research Scientist, Cree Inc. 1. Education / Training 2005 Ph.D. Materials Science, Vanderbilt University, Nashville, TN (2005) 2000 M.Sc. Physics, Indian Institute of Technology, Kharagpur, India (2000) 1998 B.Sc. Physics, Indian Institute of Technology, Kharagpur, India (1998) 2. Employment History 2008 Present: Research Scientist, Cree, Inc : Research Associate, Dept. of Physics, Vanderbilt University, Nashville, TN : Research Assistant, Interdisciplinary Materials Science, Vanderbilt University, Nashville, TN, 06/01-02/05 3. Awards and Honors 4. Peer-Reviewed Publications Related to this Project 1. S.-H. Ryu, S. Dhar et.al., Performance, reliability and robustness of 4H-SiC power DMOSFETs, Materials Science Forum, , 969 (2010) 2. S. Dhar, S.-H. Ryu, A. K. Agarwal, A study on pre-oxidation N implantation for the improvement of channel mobility in 4H-SiC MOSFETs accepted for publication in IEEE Trans. Elec. Dev., June (2010) 3. S.-H. Ryu, S. Dhar et al., Critical issues for MOS based power devices in 4H-SiC, Materials Science Forum, , 743 (2009) 5. Peer-Reviewed Publications Demonstrating Capabilities 1. S. Dhar et.al., O. Seitz, M. D. Hall et. al. Chemical properties of oxidized Silicon Carbide surfaces upon etching in hydrofluoric acid J. American Chemical Society, 46, (2009) 2. J. Rozen, S. Dhar, M. E. Zvanut, et. al. Density of interface states, electron traps, and hole traps, as a function of the nitrogen density in SiO 2 on SiC Journal of Applied Physics, 105, issue 10, (2009) 3. S. Dhar, X.D. Chen, P. M. Mooney et. al., Profiling ultra-shallow interface states at the SiO 2 /4H-SiC interface, Applied Physics Letters, 92, (2008) 4. J. Rozen, S. Dhar, S. K. Dixit et. al., Increase in hole trap density associated with nitrogen incorporation at the SiO 2 /SiC interface Journal of Applied Physics, 103, (2008) 5. X.D. Chen, S. Dhar, T. Isaacs-Smith et.al., Electron capture and emission properties of interfaces states in thermally oxidized and NO annealed SiO 2 /4H-SiC, Journal of Applied Physics, 103, (2008) 6. E. Ray, J. Rozen, S. Dhar, et.al., Pressure dependence of SiO 2 growth kinetics and electrical properties of SiC Journal of Applied Physics, 103, (2008) 7. S. Wang, S. Dhar, S. Wang, A. C. Ahyi, et.al., Bonding at the SiO 2 /SiC interface and the effects of nitrogen and hydrogen, Physical Review Letters, 98, (2007) 45

48 8. S. Dhar, R. P. Davis and L. C. Feldman, A novel technique for fabrication of nanostructures on Silicon Carbide using amorphization and oxidation, Nanotechnology, 17, 4514 (2006) 9. S. K. Dixit, S. Dhar, J. Rozen et.al., Total dose radiation response of nitridated and nonnitridated SiO 2 /4H-SiC MOS capacitors, IEEE Transactions on Nuclear Science, 56, 3687 (2006) S.Dhar, Y.W. Song, L.C. Feldman, et.al., Effect of nitric oxide annealing on the interface trap densities near the conduction band-edge at the oxide/ (11-20) 4H- SiC interface Applied Physics Letters, 84, 1498 (2004) 6. Non-Peer-Reviewed Publications and Patents 1. S. Dhar, S.-H. Ryu, Transistors with a gate insulation layer having a channel depleting interfacial charge and related fabrication methods (Pending) 2. S. Dhar, S.H-Ryu, D. Lichtenwalner, V. Mishra, Transistors with a dielectric channel depletion layer and related fabrication methods (Pending) 3. Q.Zhang, S.-H. Ryu, A.K. Agarwal and S. Dhar, Transistors with semiconductor interconnection layers and semiconductor channel layers of different semiconductor materials (Pending) 46

49 Russel Jacob Baker, Ph. D Professor, Boise State University Professional Summary: Dr. Russel Jacob Baker (S 83-M 88-SM 97) was born in Ogden, Utah, on October 5, He received the B.S. and M.S. degrees in electrical engineering from the University of Nevada, Las Vegas, in 1986 and He received the Ph.D. degree in electrical engineering from the University of Nevada, Reno in From 1981 to 1987, he served in the United States Marine Corps Reserves. From 1985 to 1993, he worked for E. G. & G. Energy Measurements and the Lawrence Livermore National Laboratory designing nuclear diagnostic instrumentation for underground nuclear weapons tests at the Nevada test site. During this time he designed over 30 electronic and electro-optic instruments including high-speed (750 Mb/s) fiber-optic receiver/transmitters, PLLs, frame- and bit-syncs, data converters, streak-camera sweep circuits, micro-channel plate gating circuits, and analog oscilloscope electronics. From 1993 to 2000, he served on the faculty in the department of electrical engineering at the University of Idaho on the Boise State campus. In 2000, he joined a new electrical and computer engineering program at Boise State University, where he served as department chair from 2004 to At Boise State he helped establish graduate programs in electrical and computer engineering including, in 2006, the university s second PhD degree. Also, since 1993, he has consulted for various companies and laboratories including Amkor, Lawrence Berkeley Laboratory, Micron, Nascentric, Rendition, Sun, and Tower. His research interests lie in analog/mixed-signal integrated circuit design (combining analog circuit design with digital signal processing) and the design of memory/displays (arrays) in new and emerging fabrication technologies. Professor Baker holds over 200 granted or pending patents in integrated circuit design. Among his inventions is the K- Delta-1-Sigma modulator topology used in the Baker analog-to-digital converter. He is a member of the electrical engineering honor society Eta Kappa Nu, a licensed Professional Engineer, and the author of the books CMOS Circuit Design, Layout, and Simulation, CMOS Mixed-Signal Circuit Design, and a coauthor of DRAM Circuit Design: Fundamental and High- Speed Topics. He received the 2000 Best Paper Award from the IEEE Power Electronics Society and the 2007 Frederick Emmons Terman Award. 1. Education 1986 B.S. Electrical Engineering, University of Nevada, Las Vegas 1988 M.S. Electrical Engineering, University of Nevada, Las Vegas 1993 Ph.D. Electrical Engineering, University of Nevada, Reno 2. Work Experience 2000 Present Professor, Electrical Engineering, Boise State University Assistant and then Associate Professor, University of Idaho Engineer, E. G. & G. and Lawrence Livermore National Laboratories 3. Honors, Awards and Notable Professional Appointments 1. Terman Award Winner, Honored Faculty Member - Boise State University Top Ten Scholar/Alumni Association

50 3. Outstanding department of electrical engineering faculty, Boise State prize paper award from the IEEE Power Electronics Society 5. University of Idaho, Department of electrical engineering outstanding researcher award, University of Idaho, College of engineering outstanding young faculty award, Peer-Reviewed Journal Publications Specifically Related to this Project 1. Leslie, M.B., and Baker R. J., (2006) "Noise-Shaping Sense Amplifier for MRAM Cross-Point Arrays," IEEE Journal of Solid State Circuits, Vol. 41, No. 3, pp Hess, H.L., and Baker R. J., (2000) "Transformerless Capacitive Coupling of Gate Signals for Series Operation of Power MOS Devices," IEEE Transcactions on Power Electronics, Vol. 15, No. 5, pp Lin, F., Miller J., Schoenfeld A., Ma, M. and Baker R. J., (1999) "A Register-Controlled Symmetrical DLL for Double-Data-Rate DRAM," IEEE Journal of Solid State Circuits, Vol. 34, No. 4, pp Harvard, Q., Baker R. J., and Drost, R., Main Memory with Proximity Communication: A Wide I/O DRAM Architecture, Proceedings of the IEEE/EDS Workshop on Microelectronics and Electron Devices (WMED), pp , April 16, Yap, K.M. and Baker R. J., Gain Error Correction for CMOS Image Sensor using Delta-Sigma Modulation, Proceedings of the IEEE/EDS Workshop on Microelectronics and Electron Devices (WMED), pp , April 16, Gagliano, C. and Baker R. J., A Compact Delay-Locked Loop for Multi-Phase Non- Overlapping Clock Generation, Proceedings of the IEEE/EDS Workshop on Microelectronics and Electron Devices (WMED), poster, April 16, Regner, J., Balasubramanian, M., Cook, B., Li, Y., Kassayebetre, H., Sharma, A., Baker, R. J., Campbell, K.A., Integration of IC Industry Feature Sizes with University Back- End-of-Line Post Processing: Example Using a Phase-Change Memory Test Chip, Proceedings of the IEEE/EDS Workshop on Microelectronics and Electron Devices (WMED), pp , April 3, Gupta, S. Saxena, V., Campbell, K.A., and Baker R. J., W-2W Current Steering DAC for Programming Phase Change Memory, Proceedings of the IEEE/EDS Workshop on Microelectronics and Electron Devices (WMED), pp , April 3, Saxena, V. and Baker R. J. Indirect Compensation Techniques for Three-Stage CMOS Op-amps, proceedings of the 52nd Midwest Symposium on Circuits and Systems, pp. 9-12, August 2-5, Saxena, V., Li, K., Zheng, G., and Baker R. J., A K Delta 1 Sigma Modulator for Wideband Analog to Digital Conversion, proceedings of the 52nd Midwest Symposium on Circuits and Systems, pp , August 2-5, Other Peer-Reviewed Journal Publications in the Broad Field 1. Li, K., Saxena, V., Zheng, G., and Baker R. J., Full Feed-Forward K-Delta-1-Sigma Modulator, 4 th Annual Austin Conference on Integrated Circuits & Systems, Oct , Ande, H.K., Busa, P., Balasubramanian, M., Campbell, K.A., and Baker R. J., "A New Approach to the Design, Fabrication, and Testing of Chalcogenide-Based Multi-State 48

51 Phase-Change Nonvolatile Memory,", proceedings of the 51stMidwest Symposium on Circuits and Systems, pp , August 10-13, Saxena, V., and Baker R. J., "Compensation of CMOS Op-Amps using Split-Length Transistors,", proceedings of the 51st Midwest Symposium on Circuits and Systems, pp , August 10-13, Estrada, D., Ogas, M.L., Southwick III, R.G., Price, P.M., Baker, R.J., and Knowlton, W.B., Impact of Single pmosfet Dielectric Degradation on NAND Circuit Performance, Microelectronics Reliability, 48(3) (2008) pp Saxena, V., and Baker, R.J., "Indirect Compensation Technique for Low-Voltage Op- Amps,", proceedings of the 3rd Annual Austin Conference on Integrated Systems and Circuits (ACISC), May 7-9, Cahoon, C., and Baker, R.J., "Low-Voltage CMOS Temperature Sensor Design using Schottky Diode-Based References," proceedings of the IEEE/EDS Workshop on Microelectronics and Electron Devices (WMED), pp , April, Keeth, B., Baker, R.J., Johnson, B., and Lin, F., DRAM Circuit Design: Fundamental and High-Speed Topics, Wiley-IEEE, ISBN Non-Peer-Reviewed Publications and Patents 1. Baker, R.J., "CMOS Circuit Design, Layout and Simulation, Revised Second Edition" Wiley-IEEE, 2008, 1039 pages. ISBN Over 30,000 copies in print of the 3 editions. 2. Baker, R.J., CMOS Mixed-Signal Circuit Design, Second Edition Wiley-IEEE, 2009, 330 pages. ISBN Over 10,000 copies in print of the 2 editions. 3. Keeth, B., Baker, R. J., Johnson, B., and Lin, F. DRAM Circuit Design: Fundamental and High-Speed Topics, Wiley-IEEE, 2007, 440 pages. ISBN Over 3,000 copies in print. 4. Baker, R.J. Quantizing circuits for semiconductor devices, 7,667,632, February 23, Baker, R.J. and Beigel, K. D., Multi-resistive integrated circuit memory, 7,642,591, January 5, Baker, R.J. Offset compensated sensing for a magnetic random access memory, 7,616,474, November 10, Baker, R.J. Resistive memory element sensing using averaging, 7,577,044, Aug. 18, Baker, R.J. Quantizing circuits with variable parameters, 7,538,702, May 26, Baker, R.J. Method and system for reducing mismatch between reference and intensity paths in analog to digital converters in CMOS active pixel sensors, 7,528,877, May 5, Baker, R.J. Method and system for reducing mismatch between reference and intensity paths in analog to digital converters in CMOS active pixel sensors, 7,515,188, April 7, 2009.Taylor, J. and Baker, R.J. Method and apparatus for sensing flash memory using delta-sigma modulation, 7,495,964, February 24,

52 Patrick McCluskey, Ph. D Associate Professor, University of Maryland Professional Summary: Prof. Patrick McCluskey is an Associate Professor of Mechanical Engineering at the University of Maryland, College Park where he is associated with the CALCE Electronic Products and Systems Center. He has published extensively in the area of packaging and reliability of electronics and microsystems for high power and extreme temperature environments, including three books and numerous book chapters. He has also served as general or technical chairman for numerous conferences in these research areas. Dr. McCluskey is an associate editor of the IEEE Transactions on Components and Packaging Technologies. He received his Ph.D. in Materials Science and Engineering from Lehigh University. 1. Education: 1991 Ph.D. Materials Science and Engineering, Lehigh University, Bethlehem, PA 1986 M.S. Materials Science and Engineering, Lehigh University, Bethlehem, PA 1984 B.S. Metallurgical Engineering (Summa Cum Laude), Lafayette College, Easton, PA 2. Work Experience: 2002 Present: Associate Professor, Mechanical Engineering, Univ. of Maryland, College Park : Assistant Professor, Mechanical Engineering, Univ. of Maryland, College Park : Assistant Research Scientist, CALCE EPSC, Univ. of Maryland, College Park : Materials Technologist, W. L. Gore and Associates, Inc., Elkton, MD 3. Honors, Awards, and Notable Professional Appointments: 1. National Science Foundation Graduate Fellowship, September August AT&T Bell Laboratories Fellowship, September July Literati Society Award for Best Paper of 1997 in Microelectronics International for: 4. F. P. McCluskey, R. Munamarty, and M. Pecht, Popcorning in PBGA Packages During IR Reflow Soldering, Microelectronics International, Vol. 42, Jan. 1997, pp Best Paper in Session, 1996 International Electronics Packaging Society Annual Technical Meeting, 6. U.S. Navy BMP Award for Methodology for High Temp Electronics Design for Reliability, (2004). 7. 2nd Place in Best Student Chapter Contest at IMAPS National Meeting University of Maryland Physical Science Invention of the Year Finalist 9. Best Paper in Session, SPIE Smart Structures Conference Best Paper in Session WP3, IMAPS Symposium Best Paper in Session WA5, IMAPS Symposium nd Place in Best Student Chapter Contest at IMAPS National Meeting Peer-Reviewed Journal Publications Specifically Related to This Project: 50

53 1. P. Quintero, F. P. McCluskey, Silver-Indium Transient Liquid Phase Sintering for High Temperature Die Attachment, J. Microelectronics and Electronic Packaging, vol 6, pp (2009) 2. R. W. Chang and F. P. McCluskey, Reliability Assessment of Indium Solder for Low Temperature Electronic Packaging, Cryogenics, 49 (11), pp (2009). 3. P. Quintero, T. Oberc, F. P. McCluskey, Reliability Assessment of High Temperature Lead-free Device Attach Technologies, Proc. of the IEEE Electronic Components and Technology Conference, ECTC 08. Orlando, FL. May S. Sivaswamy, R. Wu, C. Ellis, M. Palmer, R. W. Johnson, P. McCluskey, and K. Petrarca, System-in-Package for Extreme Environments, Proc. of the IEEE Electronic Components and Technology Conference, ECTC 08, Orlando, FL. May P. Hansen and P. McCluskey, Failure Models in Power Device Interconnects, Proceedings of EPE 2007, the 12th European Conference on Power Electronics and Applications, Aalborg, Denmark, Sept Paper # F. P. McCluskey, M. Dash, Z. Wang, and D. Huff, Reliability of High Temperature Solder Alternatives, Microelectronics Reliability, Vol. 46, No. 9-11, pp (2006). 7. K. Meyyappan, P. McCluskey, and L-Y Chen, "Thermo-Mechanical Analysis of Gold based SiC Die Attach Assembly," IEEE Trans. on Device and Material Reliability, Vol. 3., No. 4, pp (2003). 5. Other Peer Reviewed Journal Publications in the Broad Field: 1. A. Chandrasekaran and F. P. McCluskey, Effect of Green Molding Compounds on High Temperature Wirebond Reliability, Micromaterials and Nanomaterials. Issue 3. Vol pp (2004) 2. K. Meyyappan, P. McCluskey, and L. Chen, Thermomechanical Analysis of Gold- Based SiC Die Attach Assembly, IEEE Trans Device and Materials Reliability, Vol 3, No. 4. pp (2003) 3. H. Ardebili, C. Hillman, M. Natishan, P. McCluskey, M. Pecht, and D. Peterson. "A comparison of the theory of moisture diffusion in plastic encapsulated microelectronics with moisture sensor chip and weight -gain measurements" IEEE Trans. On Components and Packaging Technology, Vol. 25. No.1, pp March F.P. McCluskey, Y.D. Kweon, H.J. Lee, J.W. Kim, and H.S. Jeon, Method for Assessing Remaining Life in Electronic Assemblies, Microelectronics Reliability, Vol. 40, No. 2, pp (2000) 5. F. P. McCluskey, K. Mensah, C. O Connor, A. Gallo, Reliable Use of Commercial Technology in High Temperature Environments, Microelectronics Reliability, Vol. 40, pp (2000). 6. Non-Peer Reviewed Paper and Patents: 1. P. McCluskey and P. Quintero, High Temperature Lead-Free Solder Paste, Provisional Patent US60/891,763 (filed February 2007). U.S. Patent Filed January

54 b. Organizations Involved CoolCAD Electronics LLC, Cree Inc, University of Maryland and Boise State University are the organizations involved in this project. These organizations have several decades worth of experience in various aspects of the work required for this project. CoolCAD Electronics is the lead organization for this project. CoolCAD is a high-technology startup company located in Maryland that has unique algorithms, software and IC design capability for extreme environment electronics. It s core team is made up of scientists and engineers from the University of Maryland s Semiconductor Simulation Laboratory group. They have >50 years of cumulative experience in modeling and design of Silicon Carbide lateral and power MOSFETs. CoolCAD has worked over the past decade with the US Army Research Laboratory on the development of sophisticated models for high temperature characterization of SiC devices. Through this collaboration, CoolCAD personnel have also actively worked with Cree Inc. on characterizing their power SiC DMOSFET devices. Team members at CoolCAD have also been actively working with NASA on developing physics based compact modeling of cryogenic temperature operation of Silicon devices. These models and PDK development are being carried out for bulk CMOS, SOI and SOS technologies for operation at <20K operation in radiation rich environments. This has given CoolCAD extensive experience in compact modeling and Verilog-A based behavioral model development. Members of CoolCAD also have designed various IC s in Silicon using the AMI0.6 micron and IBM s 130nm and 65nm processes. These chips were fabricated through MOSIS and tested at low and high frequencies at CoolCAD. Thus, CoolCAD is uniquely positioned in terms of modeling and PDK development related to high temperature Silicon Carbide electronics, and IC design using this technology which is required for successful completion of this project. Cree Inc. is a world leader in Silicon Carbide technology fabrication. It supplies high quality SiC wafers to various SiC device manufacturers, universities and government laboratories. It also fabricates and markets highly efficient SiC Schottky diodes for applications in solar panel inverters, hybrid vehicles, etc. Cree has all the facilities for fabricating and testing IC s and devices in Silicon Carbide. It will serve as the fabrication house for the devices and circuits designed by the other team members. In addition, it will devote extensive resources to fabricating a lateral power MOSFET that will be integrated with the control and drive circuits on a single chip. Cree is also the world leader in solid state lighting products. This project may also help their solid-state-lighting business in the future. It also develops power and radio frequency (RF) products, including power switching and RF devices. The majority of Cree, Inc. products are manufactured at its main production facility in North Carolina. It also operates research and development facilities in North Carolina, California, Hong Kong and China. In February 2008, the Company acquired LED Lighting Fixtures, Inc. (Cree LED Lighting Solutions, Inc.). Boise State University professor Dr. R. Jacob Baker is a leading expert on CMOS digital, analog and mixed-signal designs. He has published best-selling books on this subject and holds several patents on various circuit designs. Since Silicon Carbide is a nascent technology where sophisticated circuits have not been developed yet, his experience and creativity in designing novel circuits will be invaluable. Dr. Baker will work closely with CoolCAD in developing circuits for op-amps, gate drives, voltage references, and other circuits that will be fabricated in Cree s SiC process. In addition, he will assist CoolCAD engineers in developing the first 2-metal Process Design Kit (PDK) for Cree s process. This PDK will be extensively used throughout the project for circuit designs. 52

55 University of Maryland professor Dr. Patrick McCluskey is an expert on designing, testing and validating high temperature packaging. He is a recognized authority on thermal analysis, fatigue modeling, and package design for extreme environment applications of electronics. He regular acts as a conference and session chair in the prestigious High Temperature Electronics (HiTEC) conference. HiTEC brings together companies, universities and government departments carrying out research on high temperature electronics and packaging. The University of Maryland CALCE center has several professors and researchers that work on efficient package designs for extreme environment electronics. c. Facilities CoolCAD Electronics, Cree, University of Maryland and Boise State have extensive facilities for accomplishing the various tasks described above. In addition we have budgeted for equipment purchases that will help us successfully accomplish the tasks of this project. CoolCAD Electronics LLC: CoolCAD Electronics and the University of Maryland have substantial resources and facilities for high temperature electrical testing of Silicon Carbide bare die and packaged chips. Test Equipment: 4155 Semiconductor Parameter Analyzer HP Logic Analyzer HP High Frequency Spectrum Analyzer Techtronix High Frequency Scope Agilent High Frequency Network Analyzer Alessi High Temperature Probe Station with RF and DC Probes Zeiss Stemi high magnification microscope ideal for examining integrated circuits and microsensors. Collection of function generators, oscilloscopes, power supplies, etc. Commercial IC and PCB Design and Characterization Software: Agilent IC-CAP Semiconductor Parameter Extraction Software Cadence Spectre: Analog and mixed-signal simulation tool Cadence Virtuoso Schematic Editor XL: Computer interface for inputting a circuit schematic Cadence Virtuoso Analog Design Environment GXL: Circuit simulation tool for analyzing the circuit schematic Cadence Virtuoso Layout Editor GXL: Takes schematic and turns it into a layout, performs parasitic parameter extraction, layout versus schematic and design rule checks. Encounter Digital Design Platform GXL: Verilog Hardware Description and Synthesis Place and Route Eagle Printed Circuit Board Layout and Routing Software Printed Circuit Board Design and Populate Facility: Eagle layout and routing software for PCBs 53

56 Essemtec Pick and Place Machine for high volume high accuracy PCB assembly and prototyping Reflow Oven for PCB prototyping Evaluation Boards for Numerous Networking IC s and Microcontrollers: Texas Instruments TMS320C5509A DSP processor, MSP430 microcontroller, CC2430 Microchip dspic30f bit microprocessor IAR Embedded Workbench for CC2430 Texas Instruments Code Composer Studio MPLAB ICD 3 for Microchip PICs and dspics LINX RF Transmitter and Receiver Modules Computing Facilities: Numerous personal computers Numerical analysis and graphing software such as MATLAB Chip Fabrication: By using resources available through the University of Maryland, we can have chips fabricated that use state-of-the art fabrication processes. These processes include the 0.13 micron IBM 8RF-DM process. New Equipment: In addition to the equipment listed above, we plan to buy other equipment for high temperature measurement and characterization of SiC IC s. These include the following: Semiconductor parameter analyzer capable of high voltage wafer probing. LCR meter for CV characterization Laboratory oven allowing for 300C testing Cree Inc.: Cree, Inc. owns facilities located at 4600 Silicon Drive, Durham, NC with buildings totaling over 400,000 ft 2 on 30 acres of land. Cree has a neighboring building with 120,000 ft. 2 and 17 acres of land to house corporate offices and administration. Cree has also recently added a 200,000 ft 2 facility which is located at 3026 E. Cornwallis Rd, Research Triangle Park (RTP), NC This new Cree RTP facility is dedicated to the fabrication, packaging, and testing of high power SiC and GaN products. 54

57 Cree RTP facility for the fabrication and test of high power SiC and GaN products located in Research Triangle Park, NC. Pertinent equipment currently available at Cree for SiC and GaN material growth and characterization is shown in Table D1: Silicon Carbide Bulk Crystal Growth Systems. SiC Epitaxial Deposition Systems. Precision X-Ray Crystal Orientation System. Wafering Saws. Lapping/Polishing Systems. Hall Effect Measurement System w/ Cryostat. High Voltage-Capacitance Measurement Systems. Auger Electron Spectrometer 0.5 m Spectrometer & Element Detector Array. 325 nm and 275 nm lasers for PL characterization. FTIR film thickness and doping measurement tool. Automated microscopic inspection system. High-temperature Hall effect ( K) Low-temperature Hall effect (80K-700K) Electron paramagnetic resonance High-temperature deep level transient spectroscopy Low-temperature optical absorption Photoluminescence (4K) system Contactless high-resistivity (2E9 Ω-cm) mapping Robotic, high-throughput CV and FTIR PL based MCL measurements Molten KOH etch for defect characterization Table D1. Equipment for SiC substrate and epitaxial material growth and characterization available at Cree. 55