FPGA-based High Performance AC Servo Motor Drive Accelerator TM configurable servo drive design platform

Transcription

1 FPGAbasd High Prformanc AC Srvo Driv Acclrator TM configurabl srvo driv dsign platform Toshio Takahashi, Intrnational Rctifir Abstract: In rcnt yars, a Digital Signal Procssor (DSP) or Microcontrollr has bn widly usd for implmnting th digital motor control algorithm in th motor driv industry. Application spans widly from a low prformanc applianc AC invrtr driv to a high prformanc srvo driv. Today s digital AC driv consists of th implmntation of torqu control by mans of rgulating th motor currnt which rquirs vry high spd computation in th rang of tns of microsconds, and spd control which rquirs rlativly modrat computation intnsity in th rang of hundrds of microsconds. All ths functions hav bn implmntd in on DSP or on microcontrollr with/without a sparat motion ASIC which prforms much fastr tasks such as th PWM (Puls Width Modulatd wavform gnrator), ncodr signal, tc. This popularity has bn du partly to availability and flxibility of dsird algorithm implmntation. Howvr, as th prformanc nvlop is furthr xpandd and application is furthr divrsifid, nw issus aris to satisfy th nd for nw prformanc challngs. 1) Traditional DSP and microcontrollr hav th fixd motion priphral hardwar logic and communication ports. Constraint on ths fixd hardwar logics insid a DSP and microcontrollr imposs limit on th adaptation of diffrnt typs of fdback dvics and ntwork connctivity, and uniqu customization of motion priphral hardwar logics. 2) Inadquat prformanc du to a lack of computation powr for highnd srvo torqu control rsults in a multipl DSP or microcontrollr 1 implmntation mixd with spcific motion priphral ASIC(s); On for torqu control and th othr for othr controls. This crats additional complxity associatd with functional partitioning and intrconnctivity among split moduls/functions. 3) Impdd procss and challng to mt fastr timtomarkt dvlopmnt. Exponntial ffort in programming is alrady invitabl in today s driv dvlopmnt procss. A Spcific coding tchniqu is oftn usd to mt dmanding challngs, and to satisfy nw computational spd rquirmnts. Cod maintnanc ability is furthr dtrioratd if a cryptic assmbly languag is usd as opposd to a high lvl languag, such as C, in ordr to mt th spd rquirmnt. In rality, th torqu control algorithm is particularly writtn in th ddicatd assmbly languag, which advrsly affcts programming productivity. In ordr to solv th arising problms stmmd from th traditional DSP and microcontrollr approach, a nw mthod of hardwar control has bn dvlopd. Intrnational Rctifir rcntly introducd th Acclrator TM dsign platform for a flxibl high prformanc srvo driv systm. Th systm is basd on th latst gnration of th FPGA which rcntly bcam affordabl for implmnting complicatd closd loop currnt control and vlocity control with dsird motion priphral and communication ports. Rviw of th today s srvo driv digital control architctur and functional partitioning Today, most srvo motor driv systms ar implmntd by digital closd loop control

2 instad of analog control. This has bn du primarily to th rapid advancmnt of a Digital Signal Procssor (DSP) and microcontrollr applid to motor control applications. In a typical srvo control systm, svral functions ar dividd into tasks which run at a diffrnt updat rat dpnding on th rquird bandwidth and natur of procssing priority nd raltim opration vrsus dlayd batch procss, scannd task vrsus ontim vnt drivn task. Each task is controlld by a multitask oprating systm closly coupld with a DSP or microcontrollr intrrupt structur. Figur 1 shows a typical structur of a srvo driv systm in trms of function. Functional lmnt, which dals with much closr machin control, rquirs fast procssing, fast updat rat and raltim procssing. Thy ar closly tid with a spcific motion priphral hardwar and it somtims rquirs spcific coding uniqu to th priphral hardwar and intrrupt structur insid th DSP or microcontrollr. On th contrary, tasks that ar far apart from th machin sid and clos to th host communication or manmachin sid, rquir lss frqunt updating and slow procssing. Howvr, it rquirs mor mmoryintnsiv calculation sinc rfrnc command gnration ovr th controlling paramtr is mor complicatd than thos, which ar clos to th machin sid. For xampl, position rfrnc command is much mor complx as sophisticatd motion profil gnration advancs. Howvr, torqu command is producd in a simpl stp function. Th fact is that torqu is th fastst machin paramtr, and nds to b controlld much mor quickly than th spd of th motor shaft. Intgral of torqu is spd. Intgral of spd is position. Intgral of powr rsults in motor tmpratur ris. Bcaus of this chain of physical motor paramtrs, ach paramtr rquirs diffrnt spd of procssing. It is typical that a raltim multitasking oprating systm is usd to satisfy ach rquird procssing powr. Howvr, today s DSP or microcontrollr is facing a mor difficult and fundamntal challng to dal with all ths tasks rquiring diffrnt procssing powr. Today s srvo driv rquirs diffrnt ffort and nhancmnt in two divrsifid dirctions. ling torqu rquirs a much fastr computation updat rat to sustain th closd loop bandwidth and th incrasing dmand of dynamics of th machin. For xampl, in ordr to achiv 4kHz torqu bandwidth, th torqu control loop computation updat rat rquirs 25 microsconds rang. Th rol of th powr managmnt function incrass. Mor advancd dadtim compnsation, clos monitoring of tmpratur ris of powr dvics, accurat motor phas voltag fdback snsing, currnt snsing, and motor machin paramtr stimats ar mrging functions which rquir mor spcific programming, fast computation, uniqu digital hardwar logic and analog circuit. Procssing spd daling with ths logic rachs nanosconds ordr and is usually implmntd by th ddicatd ASIC. On th othr hand, th task of daling with position control and host communication rquirs mor mmoris and programming ffort. Mor sophisticatd motion profiling rquirs mor mmoris in both instruction and data with complx programming and a dcnt computation updat rat. 2

3 Softwar Intnsiv Environmnt Lots of mmory Fast computation No ddicatd hardwar Hardwar Rich Environmnt Lss Mmory Fastst computation Motion Ppriphral Hardwar Powr Modul MultiAxis Drop Usr I/O Ntworking Squncing PLC Host COMM Position Coordinat Spd & Intrpolation Closd Loop Torqu Gat Drivr Powr and ManagmntProtction Priphral Currnt Snsing BLDC Srvo Encodr Hundrds of millisconds micro microsocnds Tns of sconds microsocnds Tns of nano sconds nano sconds PC Programmr Figur 1. Srvo driv functions As shown in Figur 1, computation rquirmnt is basically dividd into two parts. A hardwar rich nvironmnt rquirs fast computation and mor intnsifid ddicatd hardwar logic in powr managmnt priphrals. A softwar intnsiv nvironmnt rquirs a lot of mmoris with mor programming ffort. It is impossibl to achiv both sids of th function altogthr in on DSP or microcontrollr. Today s mostly availabl motiondsp dos not adquatly satisfy this nd. Lack of computation powr, xponntially incrasing dmand of mmory for programming and data, and nw hardwar logic in motion priphral ar difficult to implmnt without a compromis in prformanc. If today s motiondsp tris to satisfy th nd without modifying th fundamntal structur of th DSP, th chip bcoms impractical and lss conomical. It also bcoms difficult to implmnt all th motion functions in ASIC plus DSP in th framwork of traditional functional partitioning, whr all of th closd control including torqu control, spd control, and 3 positioning control ar implmntd in on DSP or microcontrollr, whil th motion priphral function is implmntd in th ddicatd ASIC. This is du largly to th fact that toqu control dmands a much fastr computation updat rat thus it bcoms difficult to prform th torqu control function along with othr control functions within a DSP or microcontrollr softwar computation nvironmnt. Th traditional approach is quickly approaching th limit of not bing abl to satisfy prformanc dmands, fastr dvlopmnt tim, and asy and low cost softwar maintnanc. Acclrator TM srvo driv architctur Intrnational Rctifir has rcntly introducd th Acclrator TM systm. It is an uniqu srvo driv dvlopmnt systm that simplifis th dvlopmnt procss of th digital srvo driv systm whil achiving high bandwidth in torqu control rspons and flxibl customization of th motion priphral and communication port. Th hart of th flxibility is achivd by a configurabl FPGA combind with svral prprovidd

4 objct cod sts. Figur 2 shows a basic block diagram of th Acclrator TM systm. All ncssary control algorithms ar implmntd in th FPGA including communication protocol logics. Th FPGA can b dirctly d with highvoltag ICs which control and sns lctrical powr to th motor. AC Powr MultiAxis Host or othr host controllr FPGA(Spartan2300) RS232C or RS422 SPI Paralll Host Rgistr TM Acclrator Chip St Configuration Monitoring Ks dt DC bus dynamic brak control 2/3 Spac Vctor PWM FLT_CLR Dad tim Priod/Duty countrs Priod/Duty countrs slct BRAKE FAULT Analog Spd Rfrnc MUX IR2137 DC bus fdback 1/T countr spd masurmnt Quadratur Dcoding Analog Filtr Rsolvr Rfrnc Encodr or Rsolvr Figur 2. Basic block diagram of Acclrator systm Prformanc advantag hardwar torqu loop. Tim critical control xcution is implmntd by hardwar rathr than by softwar. No instruction xcution is rquird to prform this function. It rathr dirctly xcuts functions by th ddicatd hardwar logics. Latncy and xcution tim dos not vary. It is inhrntly fast and dtrministic. Computation spd of th whol currnt control is xcutd wll blow 5 microsconds nabling a high PWM carrir frquncy updat. Th rsult of torqu control loop rspons rachs 5kHz at 3dB point. This high bandwidth torqu control allows intrfacing with rcnt lowinductanc srvomotors such as linar motors in ordr to achiv lss harmonic currnt rippl. All control algorithms ar implmntd in th Xilinx Spartan2300 FPGA. Flxibility customizabl motion priphral logic Th Srvo application rquirs many diffrnt variations of th circuit of th snsor and fdback dvics. Th motor position snsor can b ithr an ncodr or rsolvr dvic, dpnding on application nds. For xampl, thr ar many diffrnt typs of ncodrs: incrmntal typ or absolut typ or sin/cosin typ or srial data ncodr. Each position fdback dvic rquirs a uniqu hardwar logic structur to within a controllr. Th Acclrator systm provids th ability to configur diffrnt typs of fdback dvics such as rsolvr and incrmntal ncodr without changing hardwar pics. All ar configurabl with th onboard FPGA. Acclrator TM hardwar construction Figur 3 shows th Acclrator TM srvo driv dsign platform. Th systm can handl up to 4

5 1.5kW output with 300%/1 scond ovrload yilding 230V/7Arms continuous powr rating. Th position fdback is an incrmntal ncodr with an indx markr puls. Input voltag can b AC115V or AC230V and ithr singl phas or thrphas configuration. Th systm is quippd with a varity of protction circuitry ranging from ovrcurrnt/short circuit protction circuit, ovrtmpratur protction circuit, and ovrvoltag protction circuit. Figur 3. Acclrator TM dsign platform Th systm mploys th latst chip st consisting of th IR2137 and th from Intrnational Rctifir. Th IR2137 is a monolithic 600V highvoltag gat drivr IC and has builtin ovrcurrnt protction. Th is a monolithic 600V currntsnsing IC in th small SO8 packag. Ths highvoltag ICs, togthr with th Acclrator TM FPGA, will simplify th complicatd dsign task of analog and powr lctronics circuits such as gat driv, protction, and currnt snsing functions. Th IGBT modul, ratd at 600V/30A, is an industry standard ECONO PIM2 modul and has all th ncssary IGBTs, diods and a thrmistr tmp snsors. Th systm coms with complt schmatics, layout Grbr fil and Bill of Matrials so that th usr can modify/crat his/hr own vrsion of th PCB. Acclrator TM systm Dsign Flow and configuration Th Acclrator TM systm coms with th prloadd objct cod, which contains all th ncssary lmnts of a srvo control. Thr ar thr typs of objct cods availabl today for licnsing: IRACO201(ncodr basd srvo amplifir), IRACO202(rsolvr basd srvo amplifir), and IRACO203(snsorlss control algorithm). With ach objct cod, th usr can configur th control structur, tun th rgulator control loop, and choos th communication protocol without going through th rstlss ffort of programming. Configuration dtails ar dpictd in Figur 4 whr configurabl switchs ar locatd at ach control sction. For xampl, th induction machin can b configurd by nabling th slipgain block and adjusting th ID and IQ currntfdback scaling gains. 5

6 Closd Loop Vlocity, Squncing Closd Loop Currnt Updat Rat = PWM carrir frquncy / 2 Updat Rat = PWM carrir frquncy x1 or x 2 EXT_REF Fdforward path nabl DCV_FDBK 2 2 MUX CNVST CLK DATA 8 channl Srial START STOP DIR FLTCLR SYNC FAULT PWM ACTIVE RCV SND RTS CTS SCK SDO SDI CS Data Addrss 17 INT_REF Rfrnc Slct RS232C/ RS422 SPI Slav Paralll Squnc RAMP Accl Rat Dcl Rat Host Rgistr SPDKI SPDKP PI VQLIM CURKI IQLIM IQLIM Vlocity Enabl IDREF Configuration Monitoring IQREF Slip gain CURKP I2 I3 I1 x I2 I1 O I3 IQ ID 4096 VDLIM PI PI VQLIM VDLIM dt 0 IQ scal 4096 I2 I3 I1 x I2 O I1 I3 I1 x I2 O I1 I2 I3 I3 VQ VD Slip gain nabl DC bus dynamic brak control 2/3 VQS VDS IV IW Optional CurrntSns GSnsU GSnsL ModScl Spac Vctor PWM PWMmod PWMn 2Pn AnglScal SpdScal EncTyp Optional CurrntSns Quadratur Dcoding Dad tim Dtim MaxEncCount InitZval InitZ Zpol BRAKE Gat Signals FAULT Encodr A/B/Z Encodr Hall A/B/C Phas Currnt V Phas Currnt W ID scal 4096 Communication Moduls Currnt Offst W Currnt Offst V Figur 4. Dtaild control block diagram with configuration capability In ordr to assist configuration, th PC basd configurator program is providd. This Window basd configuration tool allows th usr to configur th srvo amplifir and motor, tun th closd loop control rgulators, and monitor any signals within th control. Typical configuration dos not rquir vn a day to complt a dsird srvo driv systm. Whn compard against traditional programming approach basd on a DSP or a microcontrollr, th Acclrator approach savs significant amount of dsign tim by liminating programming, coding, dbugging, and cod maintnanc. Figur 5 shows a dsign procss comparison btwn th Acclrator systm and a traditional DSP basd systm. If a usr nds to chang som mchanical structur of th hardwar (i.. diffrnt typ of connctors), th usr can asily crat his/hr own PCB basd on th providd layout dsign. If a situation ariss to chang th objct cod, Intrnational Rctifir also licnss th sourc cod in addition to th objct cod. Each datasht is also providd. If ndd, ach associatd tstbnch fil is also availabl as an option. All sourc cods ar writtn in th high lvl Vrilog cod and highly modularizd for asy xpansion. Intrnational Rctifir also has a plan to nhanc functionality for futur rlas. On of thm is th ntwork connctivity in ordr to satisfy th nd for multiaxis motion control application. 6

7 Acclrator Approach IRACS201/IRACO201 Dsign Platform Total Man Powr = 1.2 manwk Hardwar Dsign 28 manwk Traditional Approach Softwar Dsign 44 manwk Mchanical Dsign 9 manwk Configuration (1 manday) Mchanical part adaptation 1 manwk Low Cost Customizd Srvo Ntworking Host Total Man Powr = 105 manwk Driv Intgration/ Vrification Tst 24 manwk High Cost, High Risk Customizd Srvo Ntworking Host Motion Profil/Squncing Systm Intgration Motion Profil/Squncing Systm Intgration Figur 5. Srvo Driv systm dsign procss comparison 7