Polyphase Modulation Using a FPGA for High-Speed Applications

Transcription

1 Polyphas Modulation Using a FPGA or High-Spd Applications Fbruary 008, vrsion.0 Application ot 5 Introduction Polyphas Modulation This application not rviws and analys a polyphas modulation schm that gnrats high-rquncy intrmdiat rquncy IF carrir signals in digital IF modms using an Altra FPGA. Modulating IF signals to highr carrir rquncis tas ull advantag o th high sampling rat o modrn digital-to-analog convrtrs and ass th rquirmnt or analog voltag-controlld oscillators VCO and mixrs. This application not prsnts a mathmatical modl o th polyphas systm which provids insights into systm paramtr slctions. In particular, this application not discusss th polyphas iltr dsign. In modrn digital communication systms, IF modulation is otn implmntd in th digital domain to as th rquirmnt or analog dvics. For instanc, in digital transmission, basband signals ar up-convrtd to IF rquncy, thn modulatd by IF sinusoidal carrirs. Th digital IF carrirs and inormation signals ar convrtd to analog signals by a high-spd, digital-to-analog convrtr DAC, and inally modulatd onto carrir signals by an analog voltag-controlld oscillator. An IF modm usually uss a numrically controlld oscillator CO to gnrat digital IF carrirs. As a rsult, th IF Carrir rquncy is limitd by th yquist thorm to hal th sampling rat o th CO. This otn lavs th high-spd DAC undrutilid, bcaus many modrn DACs can support up to GH sampling rquncis. To solv this issu, an ovr-sampling polyphas modulation schm was proposd [] that utilis th high-spd, low-voltag dirntial srialir LVDS mbddd in th Altra FPGA to achiv highr-than-yquist rquncy IF carrirs. Th y is to xploit th priodicity o sinusoidal signals and th high sampling rquncy o th LVDS srialir. This application not rviws th thory usd in Implmnting an FPGA-Basd Broadband Modm Using Modl-Basd Dsign, and provids a dtaild discussion about dsign considrations whn implmnting th proposd schm. Altra Corporation A-5-.0

2 Application ot 5: Polyphas Modulation Using a FPGA or High-Spd Applications Systm Modl Convntional IF Modulation A convntional variabl-rat, digital-up convrtr or communications systms is shown in Figur. I dnots th inphas signal; Q dnots th quadratur signal. Atr puls shaping, th basband signal is otn up-convrtd by a cascad o two hal-band iltrs. For mor inormation, rr to Multirat Signal Procssing or Communication Systms. Figur. Convntional Digital-Up Convrsion Systm I FIR FIR/CIC 4 I CIC FIR cos CO DAC Q FIR FIR/CIC 4 Q CIC FIR sin A variabl rat, cascadd intgrator-comb CIC iltr can urthr provid a larg rang o rat chang. It is otn accompanid by a compnsating init impuls rspons FIR iltr. Th intrpolatd digital signal is thn modulatd by IF sinusoidal carrirs. Th basband and IF band signal spctrums ar shown in Figur. In this systm, th basband signal is modulatd to a carrir that is lss than hal o th rquncy o th CO cloc rquncy. Altra Corporation

3 Application ot 5: Polyphas Modulation Using a FPGA or High-Spd Applications Figur. Basband and IF Band Signal Spctrum o th Convrsional Systm Shown in Figur F 0 s, slow/ F s, slow Basband signal spctrum 0 F s, ast/ F s, ast IF signal spctrum Architctur o th Polyphas Modm Th coniguration shown in Figur usually gnrats carrir signals that do not xcd 50 MH. To ta ull advantag o th high sampling rat o th DAC, which can oprat at GH, a polyphas up-convrtr is proposd, as shown in Figur 3. For mor inormation, rr to Implmnting an FPGA-Basd Broadband Modm Using Modl-Basd Dsign. In th nw polyphas systm, th I and Q signals ar procssd by -paralll sub-up convrtrs sub-duc. Each sub convrtr is ssntially a polyphas componnt. A high-spd LVDS srialir acts as a multiplxr to sampl outputs rom th -polyphas componnts. Altra Corporation 3

4 Application ot 5: Polyphas Modulation Using a FPGA or High-Spd Applications Th ollowing sction xplains how th moduls highlightd in Figur 3 modulat th intrpolatd input signals to carrirs that can xcd th yquist rquncy o a CO. Figur 3. Polyphas-Up Convrsion Systm with Aliasing I FIR FIR/CIC I Polyphas FIR0 cos Sub-DUC0 CO Phas0 Q FIR FIR/CIC Q Polyphas FIR0 sin Sub-DUC LVDS Srialir DAC Sub-DUC Sub-DUC3 Altra Corporation 4

5 Application ot 5: Polyphas Modulation Using a FPGA or High-Spd Applications Polyphas Modulation Algorithm High-Frquncy Carrir Gnration To undrstand th polyphas modm, it is bst to irst invstigat how to gnrat a high-rquncy carrir using a modrat-spd FPGA. Suppos -paralll COs with dirnt phass ar sampld by a LVDS, as shown in Figur 4. Figur 4. Polyphas COs CO Phas0 CO Phas LVDS Srialir DAC CO Phas CO Phas3 I th cloc rat o th CO is ƒ CO, th sampling rat o th LVDS srialir is ƒ CO, which quals th sampling rat o th high-spd DAC ƒ dac. Dnot ƒ out as th output signal carrir rquncy in H o th LVDS srialir. Din th normalid digital rquncy as: = out dac = out CO Th goal is to achiv a high ƒ out that is not limitd to ƒ CO /. To gnrat a sinusoidal output signal with rquncy, control th paramtrs o th -th polyphas CO so that it gnrats cos and sin. is an intgr btwn [0, -]. Altra Corporation 5

6 Application ot 5: Polyphas Modulation Using a FPGA or High-Spd Applications ot that th polyphas COs oprat at low rquncy ƒ CO. Thror, th signal modl o Figur 4 is givn in Figur 5. Figur 5. Polyphas CO with Aliasing cos n Cn cos n D cos n - D - Th multiplx opration o th LVDS srialir in Figur 4 can b modld as a dlayd sum o -upsampld data sourcs. Thror, th inal output data o th FPGA to DAC is upsampld by an additional actor o. D dnots -sampl dlay. Bcaus dlay is asily modld in th Z-transorm domain, you will xprss th signals in th Z-domain. Rcall that th Z-transorm o a cosin signal is givn by [3] cosn u n Ζ with un dnoting th stp unction. You can xprss upsampling by a actor o by raising th powr o th dlay actor - to -. 6 Altra Corporation

7 Application ot 5: Polyphas Modulation Using a FPGA or High-Spd Applications Thror, th Z-transorm o th combind signal at th output o th LVDS srialir can b writtn as: 3 C = = = 0 C is th Z-transorm o a sinusoidal signal cos. Mor importantly, th output o th LVDS srialir has a high sampling rat ƒ CO ; thror, th output carrir signal rlativ to this high sampling rquncy can xcd th FPGA cloc. For instanc, at ƒ dac = GH, = 4, and = /5, th output carrir rquncy quals 400 MH. In contrast, th polyphas COs oprat at mrly 50 MH, giving th CO yquist rquncy ƒ CO / at 5 MH. Ect o Aliasing Atr th DAC sampling rquncy and dsird output carrir rquncy ar dcidd, dtrmin th polyphas actor and digitid output rquncy. xt, conigur th polyphas COs to gnrat propr sinusoidal signals. Whn using th Altra CO MgaCor, not that th discrt normalid rquncy is in th rang 0, ½. Thror, whn xcds ½, cos is an aliasd signal. Suppos = m ω, whr m is an intgr m can b non-positiv, ω is a ractional numbr in th rang 0,. W hav: 4 cosω n cosn = cosω n = cos ω n i 0 < ω < / i / < ω < 5 sinω n sinn = sinω n = sin ω n i 0 < ω < / i / < ω < For xampl, at = /5 and = 4, th discrt CO carrir rquncy is - ω = /5. I th CO cloc is 50 MH, th polyphas cosin and sin signals ar cntrd at 00 MH. In othr words, whn xploiting th high sampling rquncy o th LVDS srialir which can rach up to GH, you can gnrat a ro-phas 400 MH carrir signal using our 00 MH sinusoidal signals with dirnt phass. Altra Corporation 7

8 Application ot 5: Polyphas Modulation Using a FPGA or High-Spd Applications Polyphas Modulation Using th polyphas tchniqu discussd in th prvious sctions, modulat an IF signal to a high-rquncy carrir by adding a low-pass polyphas iltr, as shown in Figur 6. Figur 6. Inphas Signal Path o th Polyphas Up-Convrtr h 0 n cos n y0n n h n cos n y n D yn h - n cos n - D - y - n In th ollowing, w analy th inphas signal path. Th quadratur signal path can b analyd similarly. Dnot th impuls rspons o th -th sub-duc polyphas componnt in Figur 3 as h n. Aggrgat th -paralll paths o th inphas signal, as shown in Figur 6. Lt xn dnot th intrpolatd inphas signal at th output o th variabl rat CIC iltr. ot that th polyphas FIR iltrs ar singl rat; thror, th upsampling ct is du to th high-spd sampling by th LVDS srialir. 8 Altra Corporation

9 Altra Corporation 9 Application ot 5: Polyphas Modulation Using a FPGA or High-Spd Applications You can now driv th spctrum o th LVDS srialir output. Th Z-transorm o ach polyphas signal y n is: 6 H is th Z-transorm o th -th polyphas iltr, and is th input signal. Lt = ƒ, whr ƒ is th digitid rquncy. With th sum rom quation 6 ovr -polyphas componnts, w hav: 7 Equation 7 indicats that th squd input spctrum imags ar shitd to cntr at [4], thn low-pass iltrd by th intrpolation iltr H. Th output signal spctrum, whr = 4 and = /5, is shown in Figur 7. H H Y = 0 0 = = = = H H H H Y

10 Application ot 5: Polyphas Modulation Using a FPGA or High-Spd Applications Figur 7. Polyphas Modm Output Signal Spctrum CO a Polyphas Modm Input Signal Spctrum x dac b dac c - a b dac d - H- H Polyphas Filtr Dsign Equation 7 and Figur 7 show that th input signal is modulatd onto a carrir that cntrs at ƒ dac. Thror, th dsird nrgy clustrs appar at and whn th rquncy is normalid. Howvr, in addition to th dsird signal spctrum, pairs o imags o th input signal spctrum ar also obsrvd du to th -actor intrpolation mbddd 0 Altra Corporation

11 Application ot 5: Polyphas Modulation Using a FPGA or High-Spd Applications in th LVDS -actor srialiation. Ths imag nrgy clustrs appar at: m/ ±, whr m is an intgr, which satisis 0 m/ ±. Du to modulation, som o th imag spctrum may appar vry clos to th dsird signal spctrum. Dnot m 0 as th intgr that givs th closst imag to th dsird signal. m 0 can b ound as th intgr that minimis: 8 β = min m 0, m= m0 m ± For instanc, in th xampl shown in Figur 7, th dsird signal spctrum occurs at m = 0 and ƒ = = 0.4. Its closst imag occurs at m 0 = 3 and ƒ = β = To rct th imags, a wll-dsignd, polyphas low-pass iltr is ncssary. Suppos th signal rquncis ar normalid by ƒ dac. Th input signal to th polyphas modm is band limitd to α. Thror, choos th pass band dg o th low-pass iltr H to b: 9 w p = α Th stop band dg dpnds on whr th closst imag occurs; thror, it is a unction o th LVDS srialiation actor and th dsird output rquncy. Suppos th distanc btwn th dsird signal and th closst imag is β, which is dind in Equation 8. Th stop band dg o th polyphas iltr is givn by: 0 w s = β α Combin quations 9 and 0, and th transition bandwidth o th polyphas iltr is β α. ot that this transition bandwidth is usually much sharpr than th transition bandwidth o a convntional intrpolation iltr in an IF modm. In a convntional IF modm, whthr it is a hal-band iltr cascad or an intrpolation FIR iltr cascad, th last stag iltr usually has a rlaxd transition bandwidth rquirmnt [] du to th spctrum squing ct o intrpolation. [4] Unortunatly, this is not th cas or th polyphas modm iltr. Altra Corporation

12 Application ot 5: Polyphas Modulation Using a FPGA or High-Spd Applications Although th polyphas iltring opration happns bor polyphas modulation, th ovrall iltring ct xhibits som band-pass iltring proprtis. This causs th polyphas iltr to hav a highr ordr and to hav nough stop-band attnuation or imag rction. Filtr Dsign Exampl A proo o concpt polyphas modm is implmntd on an Altra Cyclon II dvic C70F67C6, clocd at 00 MH. Th LVDS srialir has a srialiation actor o = 4 and a high-spd sampling rquncy o 400 MH. Th normalid output rquncy is = 0.4. Figur 8 shows th simulatd LVDS srialir output or a polyphas CO systm dscribd in Figur 4. Obviously, by taing sampls rom phas-shitd cosin signals, you can construct a highr rquncy sinusoidal signal. Figur 8. Simulation o High Frquncy Carrir Gnration rom Phas-Shitd Sinusoidal Signals Whn random input data with 3.85 MH bandwidth ar usd, you can st up th systm as in Figur 3. In this cas, th polyphas modm modulats th 3.85 MH input signal onto 60 MH carrirs, wll xcding th dvic cloc rat o 00 MH. Th output signal spctrum ollows Figur 7. Altra Corporation

13 Application ot 5: Polyphas Modulation Using a FPGA or High-Spd Applications You can ind a dsign xampl implmnting th polyphas schm in Polyphas Modulation With Aliasing or Data Up-Convrsion. To obtain a clan output signal spctrum, th polyphas iltr dsign is basd on: w p = 3.85/400 = w s = w p = Our simulation shows that a low-pass iltr at ordr 00 givs suicint stop band attnuation with pass-band rippl at approximatly db. Th signal spctrum at th LVDS output is shown in Figur 9. otic that no visibl intrring imag spctrums ar obsrvd. Figur 9. Simulation o LVDS Output Signal Spctrum Conclusion This application not analys a polyphas modulation tchniqu that gnrats high-rquncy carrirs using Altra FPGAs with high-spd LVDS srialirs. This application not also discusss th construction o high-rquncy carrirs and th dsign o th polyphas iltr. Altra Corporation 3

14 Application ot 5: Polyphas Modulation Using a FPGA or High-Spd Applications Rrncd Documnts Documnt Rvision History This application not rrncs th ollowing documnts:. Rob Plt, Implmnting an FPGA-Basd Broadband Modm Using Modl-Basd Dsign, GSPx, ov F. J. Harris, Multirat Signal Procssing or Communication Systms, Prntic Hall, A. V. Oppnhim and A. S. Willsy and S. H. awab, Signals and Systms, nd d., Prntic Hall, A. V. Oppnhim, R. W. Schar and J. R. Buc, Discrt-tim Signal Procssing, nd d., Prntic Hall, Polyphas Modulation With Aliasing or Data Up-Convrsion Tabl shows th rvision history or this application not. Tabl. Documnt Rvision History Dat and Documnt Vrsion Changs Mad Summary o Changs Fbruary 008 v.0 Initial rlas. 0 Innovation Driv San Jos, CA Tchnical Support: Litratur Srvics: litratur@altra.com Copyright 008 Altra Corporation. All rights rsrvd. Altra, Th Programmabl Solutions Company, th stylid Altra logo, spciic dvic dsignations, and all othr words and logos that ar idntiid as tradmars and/or srvic mars ar, unlss notd othrwis, th tradmars and srvic mars o Altra Corporation in th U.S. and othr countris. All othr product or srvic nams ar th proprty o thir rspctiv holdrs. Altra products ar protctd undr numrous U.S. and orign patnts and pnding applications, maswor rights, and copyrights. Altra warrants prormanc o its smiconductor products to currnt spciications in accordanc with Altra's standard warranty, but rsrvs th right to ma changs to any products and srvics at any tim without notic. Altra assums no rsponsibility or liability arising out o th application or us o any inormation, product, or srvic dscribd hrin xcpt as xprssly agrd to in writing by Altra Corporation. Altra customrs ar advisd to obtain th latst vrsion o dvic spciications bor rlying on any publishd inormation and bor placing ordrs or products or srvics. 4 Altra Corporation