STF10N105K5, STP10N105K5, STW10N105K5

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1 STF10N105K5, STP10N105K5, STW10N105K5 N-channel 1050 V, 1 Ω typ., 6 A MDmesh K5 Power MOSFETs in TO-220, TO-220FP and TO-247 packages Datasheet - production data TAB Features Order codes V DS R DS(on) max. I D P TOT TO-220FP TO STF10N105K5 STP10N105K5 STW10N105K V 1.3 Ω 6 A 30 W 130 W 130 W TO Figure 1: Internal schematic diagram D(2, TAB) Industry s lowest R DS(on) Industry s best figure of merit (FoM) Ultra low gate charge 100% avalanche tested Zener-protected Applications Switching applications G(1) Description These very high voltage N-channel Power MOSFETs are designed using MDmesh K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. S(3) AM01476v1 Table 1: Device summary Order codes Marking Package Packaging STF10N105K5 10N105K5 TO-220FP Tube STP10N105K5 10N105K5 TO-220 Tube STW10N105K5 10N105K5 TO-247 Tube October 2014 DocID Rev 2 1/18 This is information on a product in full production.

2 Contents STF10N105K5, STP10N105K5, STW10N105K5 Contents 1 Electrical ratings Electrical characteristics Electrical characteristics (curves) Test circuits Package mechanical data TO-220 package mechanical data TO-247 package mechanical data TO-220FP package mechanical data Revision history /18 DocID Rev 2

3 STF10N105K5, STP10N105K5, STW10N105K5 Electrical ratings 1 Electrical ratings Symbol Table 2: Absolute maximum ratings Parameter Value TO-220 TO-247 TO-220FP V GS Gate- source voltage 30 V I D Drain current (continuous) at T C = 25 C 6 A I D Drain current (continuous) at T C = 100 C 3.78 A I DM (1) Drain current (pulsed) 24 A P TOT Total dissipation at T C = 25 C W I AR E AS Max. current during repetitive or single pulse avalanche Single pulse avalanche energy (starting T J = 25 C, I D = I AS, V DD = 50 V) Unit 2 A 140 mj dv/dt (2) Peak diode recovery voltage slope 4.5 V/ns dv/dt (3) MOSFET dv/dt ruggedness 50 V/ns V ISO T j T stg Insulation withstand voltage (RMS) from all three leads to external heatsink (t = 1 s; T C = 25 C) Operating junction temperature Storage temperature Notes: (1) Pulse width limited by safe operating area. (2) ISD 6 A, di/dt 100 A/µs, V peak V (BR)DSS. (3) VSD V -55 to 150 C Table 3: Thermal data Value Symbol Parameter TO-220 TO-247 TO-220FP Unit R thj-case Thermal resistance junction-case max C/W Thermal resistance junction-case max. 4.2 R thj-amb Thermal resistance junction-ambient max C/W DocID Rev 2 3/18

4 Electrical characteristics STF10N105K5, STP10N105K5, STW10N105K5 2 Electrical characteristics (T case = 25 C unless otherwise specified) Table 4: On /off states Symbol Parameter Test conditions Min. Typ. Max. Unit V (BR)DSS Drain-source breakdown voltage I D = 1 ma, V GS = V I DSS I GSS Zero gate voltage, drain current (V GS = 0) Gate-body leakage current V DS = 1050 V 1 µa V DS = 1050 V, T C = 125 C 50 µa V GS = ± 20 V; V DS = 0 10 µa V GS(th) Gate threshold voltage V DS = V GS, I D = 100 µa V R DS(on) Static drain-source on- resistance V GS = 10 V, I D = 3 A Ω Table 5: Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit C iss Input capacitance V DS =100 V, 545 pf C oss Output capacitance f = 1 MHz, 30 pf C rss Reverse transfer capacitance V GS = pf C o(tr) (1) C o(er) (2) R G Equivalent capacitance time related Equivalent capacitance energy related Intrinsic gate resistance V GS = 0, V DS = 0 to 840 V f = 1 MHz open drain - 65 pf 22 pf - 7 Ω Q g Total gate charge 21.5 nc Q gs Gate-source charge V DD = 840 V, I D = 6 A V GS =10 V 3.3 nc Q gd Gate-drain charge 15.5 nc Notes: (1) Time related is defined as a constant equivalent capacitance giving the same charging time as Coss when V DS increases from 0 to 80% V DSS. (2) Energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when V DS increases from 0 to 80% V DSS. Table 6: Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit t d(on) Turn-on delay time 19 ns t r Rise time V DD = 525 V, I D = 3 A, 8 ns - - t d(off) Turn-off-delay time R G = 4.7 Ω, V GS = 10 V 50 ns t f Fall time 21.5 ns 4/18 DocID Rev 2

5 STF10N105K5, STP10N105K5, STW10N105K5 Table 7: Source-drain diode Electrical characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit I SD I SDM (1) V SD (2) Source-drain current 6 A Source-drain current (pulsed) 24 A Forward on voltage I SD = 6 A, V GS = V t rr Reverse recovery time 345 ns Q rr Reverse recovery charge I SD = 6 A, di/dt = 100 A/µs V DD = 60 V µc I RRM Reverse recovery current 20.5 A t rr Reverse recovery time 540 ns Q rr Reverse recovery charge I SD = 6 A, di/dt = 100 A/µs V DD = 60 V T J = 150 C 5.05 µc I RRM Reverse recovery current 18.5 A Notes: (1) Pulse width limited by safe operating area. (2) Pulsed: pulse duration = 300 µs, duty cycle 1.5%. Table 8: Gate-source Zener diode Symbol Parameter Test conditions Min. Typ. Max. Unit V (BR)GSO Gate-source breakdown voltage I GS = ± 1 ma, I D = V The built-in back-to-back Zener diodes have been specifically designed to enhance the ESD capability of the device. The Zener voltage is appropriate for efficient and costeffective intervention to protect the device integrity. These integrated Zener diodes thus eliminate the need for external components. DocID Rev 2 5/18

6 Electrical characteristics 2.1 Electrical characteristics (curves) Figure 2: Safe operating area for TO-220 ID (A) 10 1 Operation in this area is Limited by max R DS(on) GIPG LM 100µs 1ms 10ms STF10N105K5, STP10N105K5, STW10N105K5 Figure 3: Thermal impedance TO-220 K 10-1 δ= GIPG LM Tj=150 C Tc=25 C Single pulse VDS(V) Single pulse tp(s) Figure 4: Safe operating area for TO-220FP ID (A) Operation in this area is Limited by max R DS(on) GIPG LM 100µs 1ms 10ms Tj=150 C Tc=25 C Single pulse VDS(V) Figure 5: Thermal impedance TO-220FP K GIPG LM δ= Single pulse tp(s) Figure 6: Safe operating area for TO-247 ID (A) Operation in this area is Limited by max R DS(on) GIPG LM Tj=150 C Tc=25 C Single pulse 100µs 1ms 10ms VDS(V) Figure 7: Thermal impedance TO-247 GIPG LM K δ= Single pulse tp(s) 6/18 DocID Rev 2

7 STF10N105K5, STP10N105K5, STW10N105K5 Figure 8: Output characteristics ID(A) GIPG LM 14 VGS=9,10, 11V 12 Electrical characteristics Figure 9: Transfer characteristics ID GIPG LM (A) 14 VDS=20V V V 2 6V VDS(V) VGS(V) Figure 10: Gate charge vs gate-source voltage VGS (V) GIPG LM VDS (V) VDD= 840 V 800 ID= 6 A Qg(nC) Figure 11: Static drain-source on-resistance RDS(on) GIPG LM (Ω) 1.60 VGS=10V ID(A) Figure 12: Capacitance variation C GIPG LM (pf) Figure 13: Normalized gate threshold voltage vs temperature VGS(th) (norm) 1.2 ID=100µ A GIPG LM Ciss Coss Crss VDS(V) TJ( C) DocID Rev 2 7/18

8 Electrical characteristics Figure 14: Normalized on-resistance vs temperature RDS(on) (norm) 2.5 VGS=10V ID= 6 A GIPG LM STF10N105K5, STP10N105K5, STW10N105K5 Figure 15: Source-drain diode forward characteristics GIPG LM VSD(V) 1 TJ=-50 C TJ=25 C TJ=150 C TJ( C) ISD(A) Figure 16: Normalized VBR(DSS) vs temperature V(BR)DSS GIPG LM (norm) 1.1 ID=1m A TJ( C) Figure 17: Maximum avalanche energy vs starting Tj EAS GIPG LM (mj) TJ( C) 8/18 DocID Rev 2

9 STF10N105K5, STP10N105K5, STW10N105K5 Test circuits 3 Test circuits Figure 18: Switching times test circuit for resistive load Figure 19: Gate charge test circuit Figure 20: Test circuit for inductive load switching and diode recovery times Figure 21: Unclamped inductive load test circuit Figure 22: Unclamped inductive waveform Figure 23: Switching time waveform DocID Rev 2 9/18

10 Package mechanical data STF10N105K5, STP10N105K5, STW10N105K5 4 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: ECOPACK is an ST trademark. 10/18 DocID Rev 2

11 STF10N105K5, STP10N105K5, STW10N105K5 4.1 TO-220 package mechanical data Figure 24: TO-220 type A drawings Package mechanical data _typeA_Rev_T DocID Rev 2 11/18

12 Package mechanical data Dim. STF10N105K5, STP10N105K5, STW10N105K5 Table 9: TO-220 type A mechanical data mm Min. Typ. Max. A b b c D D E e e F H J L L L L øp Q /18 DocID Rev 2

13 STF10N105K5, STP10N105K5, STW10N105K5 4.2 TO-247 package mechanical data Figure 25: TO-247 drawings Package mechanical data DocID Rev 2 13/18

14 Package mechanical data Dim. STF10N105K5, STP10N105K5, STW10N105K5 Table 10: TO-247 mechanical data mm Min. Typ. Max. A A b b b c D E e L L L øp ør S /18 DocID Rev 2

15 STF10N105K5, STP10N105K5, STW10N105K5 4.3 TO-220FP package mechanical data Figure 26: TO-220FP drawings Package mechanical data _Rev_K_B DocID Rev 2 15/18

16 Package mechanical data Dim. STF10N105K5, STP10N105K5, STW10N105K5 Table 11: TO-220FP mechanical data mm Min. Typ. Max. A B D E F F F G G H L2 16 L L L L L Ø /18 DocID Rev 2

17 STF10N105K5, STP10N105K5, STW10N105K5 Revision history 5 Revision history Table 12: Document revision history Date Revision Changes 07-Oct First release. 14-Oct Document status promoted from preliminary to production data. DocID Rev 2 17/18

18 STF10N105K5, STP10N105K5, STW10N105K5 IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ( ST ) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document STMicroelectronics All rights reserved 18/18 DocID Rev 2

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